Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Professor Rao Tummala to Present Keynote at 2009 International Wafer-Level Packaging Conference (IWLPC)

05/29/2009  Professor Rao Tummala, Advanced Packaging Editorial Advisory Board Member, will keynote the 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27–30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, CA.

The Riley Report

05/19/2009  Flip Chips and Flashlights by George A. Riley, Contributing Editor
With the industry's attention riveted on the next-generation of TSV- enhanced stacked - everything 3D marvels, we sometimes forget how microelectronics are changing everyday products in our world.

Memory sector upended, driven by 3D packaging tech, says Yole

05/15/2009  New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

Yole Report: Memory Packaging & Integration Trends

05/08/2009  The memory semiconductor industry is about to go through major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth, reports Yole. The study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

Simplicity Leads to 3D Packaging Success

04/14/2009  By Francoise von Trapp, contributing editor
3D embedded technologies just got closer to volume manufacturing. We've been hearing variations on the embedding theme for quite some time, but as of yet, none have made it to high volume manufacturing. However, one embedded solution, Imbera's integrated module board (IMB) technolog appears to be on its way, after the company's announcement of successful Series B funding, which the company expects will take it into high-volume production.

Plasma Cleaning and Surface Modification for Microelectronics

04/13/2009  By Gene Dunn, Panasonic Factory Solutions of America
Plasma technology offers a dry cleaning process that uses ionized gasses in vacuum chambers to remove contaminants for improved yields in gold bonding processes. Additionally, Auger electron spectroscopy (AES) is a useful analytical technique for determining the elemental surface characteristics and the effectiveness of plasma treatment to remove contaminants. This article discussed both.

Upcoming Boston Technical Events

03/20/2009  The SMTA Boston Chapter will cohost a technical presentation with IMAPS on April 21, preceding the opening of the SMTA Boston Academy, April 22-23. SMTA/IMAPS will present "Manufacturing & Reliability Challenges with QFN Packages in Pb and Pb-Free Environments." The Boston Academy will include seven courses on SMT, packages and components, PCBs, and lead-free and REACH.

Innovative Advanced Packaging Technologies Enable Leading-edge Wireless Products

03/16/2009  By Manish Ranjan, Ultratech Inc.
Leading-edge consumer electronic products demand innovative silicon and packaging solutions. While front-end silicon technologies have progressed at a pace defined by Moore's Law, the back-end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on the silicon side is significantly higher than the speed achieved on the printed circuit boards.

Intel gives nod to 40 top suppliers

03/04/2009  Intel has handed out its annual Preferred Quality Supplier (PQS) and Supplier Continuous Quality Improvement (SCQI) awards to more than three dozen of its key suppliers from its roster of thousands of supply-chain partners, ranging from capital equipment manufacturers to materials, components, and service providers.

Stenciling Platform

03/03/2009  Micro-engineered to meet the challenges of fine-pitch printing, DEK's VectorGuard Platinum is an enabling stencil platform suited to advanced applications such as wafer level packaging (WLP), direct chip attach, flip chip and ball grid arrays (BGAs). The process is reportedly capable of delivering aperture accuracies of less than 3µm, and positional tolerances of better than 20µm at pitches down to 50µm.

EPCOS's tiny sensor comes with MEMS packaging

02/21/2009  February 20, 2009: EPCOS AG is introducing what the Munich-based company is calling the world's most compact packaged sensors for barometric pressure measurement, and it comes with the firm's chip-sized MEMS packaging.

DNP Develops Slim Leadframe

01/29/2009  Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices. The leadframe enables known good die (KGD) semiconductor packaging with a thickness of 0.15 mm, using precision plating processes.

TSV First and Last: Through-Si Via Technologies for 3D SIC and 3D WLP

01/21/2009  Part 2
By Jan Provoost and Eric Beyne, IMEC
3D SIC uses a via first approach to connect circuits at the global IC level. 3D WLP uses a via last approach to connect circuits at the bond pad level. Both these approaches occupy a separate space on the 3D roadmap. This article, presented in two parts, offers both options and describes the process to realize them.

EAG agrees to acquire Nano Integrated Solutions

01/12/2009  DECEMBER 19, 2008--SUNNYVALE, CA--EAG and NanoISI expect to close the acquisition in January 2009. Financial terms of the transaction were not disclosed.

Comparing Package Bond Thermal Performance

01/01/2009  Thermal Simulation Cuts Cost.

Weathering the Storm Together

01/01/2009  What were the most significant technological advancements in our industry in 2008?

Gone Fishing

01/01/2009  I really like fly fishing. I’ve always wanted a fishing rod of my own, not one left over from an older brother’s stock of cast-offs, but a number 6 Orvis with just the right balance and flexibility for my style of trout fishing.

Learn, Explore, Share at BiTS Workshop 2009

12/11/2008  The Burn-in and Test Socket Workshop (BiTS), co-sponsored by Advanced Packaging magazine, celebrates its tenth annual gathering, March 8




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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