By Happy Holden, Mentor Graphics, Inc.
Category Archives: 3D Integration
(September 25, 2007) MUNICH, Germany— SUSS Microtec, NEXX Systems, and Surface Technology Systems (STS), manufacturers of semiconductor process equipment, announced their collaboration with Fraunhofer IZM to demonstrate integrated process solutions for 3D wafer-level packaging (WLP).
August 22, 2007 — Lam Research Corp. has shipped its first 300 mm 2300 Syndion etch system, designed for 3-D IC through-silicon via (TSV) etch applications.
TSVs provide the interconnects for die-to-die and wafer-to-wafer stacking, eliminating wire bonding to increase device packing density (smaller form factor) and improve performance (higher speed and lower power). TSVs are created during wafer fabrication or later during assembly and packaging, and process integration schemes vary widely.
“We believe we are the first supplier to ship a 300 mm system for TSV etch applications,” said Lam Research’s Jackie Seto, managing director, Software, MEMS, and 3-D IC Products, “and, by leveraging our extensive 300 mm and MEMS deep silicon etch production experience, we are taking a leading role in establishing the benchmarks for these challenging etch applications.”
The Syndion promises etch capability for a wide range of integration schemes, and uniformity across 300 mm wafers. It has reportedly etched vias ranging from 2 to 100 microns wide with depths of 20 microns to greater than 400 microns deep. Based on Lam’s high-density TCP planar plasma source, Syndion enables both 200 mm and 300 mm operation.
A polymeric spin-on coating, WaferBOND HT-250, temporarily attaches device substrates to a carrier substrate, enabling wafer thinning and subsequent processing. It will reportedly permit advanced packaging processes such as the creation of through-silicon vias (TSVs), 3D stacking, and other etching, plating, and follow-on processes.
(July 23, 2007) GRENOBLE and ANNECY, France — Alcatel Micro Machining Systems will provide two 200-mm deep reactive ion etch (DRIE) and low-temperature plasma-enhanced chemical-vapor deposition (LTPE CVD) systems at CEO/Léti-Minatec R&D institute under a joint development agreement. The parties will collaborate to develop and demonstrate a suite of turnkey silicon microvia technologies for 3D integration at wafer and die levels.
By Bob Haavind, editorial director, Solid State Technology
3D chip packaging with through-silicon vias (TSVs) will transform the industry over the next 3–5 years, based on presentations and discussions at SEMICON West. Using TSVs could enable compact packaging with increased performance.
July 19, 2007 — Amkor Technology, Inc., provider of advanced semiconductor assembly and test services, and IMEC, the Belgium-based independent nanoelectronics and nanotechnology research center, have announced a 2-year collaboration agreement to develop cost-effective, 3D integration technology based on wafer-level processing techniques.
“This collaboration with IMEC will enhance our continuing efforts to develop low cost, state of the art packaging solutions for our customers”, said Dan Mis, Amkor’s Senior Vice President for Wafer Level Advanced Product Development.
Luc Van den hove, IMEC’s Executive Vice President and COO, commented: “We are pleased that one of the leading semiconductor packaging service providers has joined our 3D system integration program that targets the development of post-passivation technology for 3D interconnects at the IC bond pad level.”
July 18, 2007
July 18, 2007 – IMEC has expanded its 3D packaging research program to fully exploit the potential of novel 3D technologies. Besides 3D interconnection technologies developments, the program is extended with research on system design methodologies. Both the technology and design sub-programs will be based on actual system requirements and closely coupled.
IMEC develops different 3D system integration concepts, each offering specific advantages for certain application domains. Current research focuses on 3D system-in-a-package (3D SiP), based on the classic packaging infrastructure; 3D wafer-level-packaging (3D WLP), based on the emerging wafer-level-packaging infrastructure; and 3D stacked IC (3D SIC), based on foundry-level 3D technology additions. Depending on the application and the systems requirements, a specific 3D solution needs to be chosen.
In the future, IMEC intends to extend its 3D system technology program with a 3D IC program which will investigate wafer stacking for interconnects at the IC local interconnect level.
By involving other companies such as e.g. fabless companies and EDA companies, IMEC aims to develop 3D architecture methodologies enabling 3D optimization across heterogeneous technologies. The technology development sub-program and the design methodologies sub-program will be tightly coupled.
Within the design sub-program, IMEC will explore the impact of 3D integration on the design of advanced systems. Methodologies to optimally partition and stack the different parts of the system will be developed and solutions for critical design issues. This will enable effective use of 3D interconnection on the system level. Design methodologies will also be explored for heterogeneous integration of intelligent 3D sensor systems.
July 18, 2007 – At SEMICON West, Amkor Technology Inc., a provider of advanced semiconductor assembly and test services, and IMEC, the independent nanoelectronics and nanotechnology research center based in Belgium, announced that they have entered into a 2-year collaboration agreement. They will develop cost-effective, 3D integration technology based on wafer-level processing techniques.
“This collaboration with IMEC will enhance our continuing efforts to develop low cost, state of the art packaging solutions for our customers”, said Dan Mis, Amkor’s senior VP for wafer level advanced product development.
Luc Van den hove, IMEC’s executive VP and COO, commented: “We are pleased that one of the leading semiconductor packaging service providers has joined our 3D system integration program that targets the development of post-passivation technology for 3D interconnects at the IC bond pad level.”