Category Archives: Materials and Equipment

December 16, 2008: A carbon nanotube-coated “smart yarn” that conducts electricity could be woven into soft fabrics that detect blood and monitor health, engineers at the University of Michigan have demonstrated.

“Currently, smart textiles are made primarily of metallic or optical fibers. They’re fragile. They’re not comfortable. Metal fibers also corrode. There are problems with washing such electronic textiles. We have found a much simpler way — an elegant way — by combining two fibers, one natural and one created by nanotechnology,” said Nicholas Kotov, a professor in the departments of chemical engineering, materials science and engineering and biomedical engineering.

Kotov and Bongsup Shim, a doctoral student in the department of chemical engineering, are among the co-authors of a paper on this material currently published online in Nano Letters.

To make these “e-textiles,” the researchers dipped 1.5mm thick cotton yarn into a solution of carbon nanotubes in water and then into a solution of a special sticky polymer in ethanol. After being dipped just a few times into both solutions and dried, the yarn was able to conduct enough power from a battery to illuminate a light-emitting diode device. The only perceptible change to the yarn is that it turned black, due to the carbon. It remained pliable and soft.

“This turns out to be very easy to do,” Kotov said. “After just a few repetitions of the process, this normal cotton becomes a conductive material because carbon nanotubes are conductive.

In order to put this conductivity to use, the researchers added the antibody anti-albumin to the carbon nanotube solution. Anti-albumin reacts with albumin, a protein found in blood. When the researchers exposed their anti-albumin-infused smart yarn to albumin, they found that the conductivity significantly increased. Their new material is more sensitive and selective as well as more simple and durable than other electronic textiles, Kotov said.


This carbon-nanotube coated smart yarn can conduct enough electricity from a battery to power a light-emitting diode device. Researchers can use its conductivity to design garments that detect blood.

Clothing that can detect blood could be useful in high-risk professions, the researchers say. An unconscious firefighter, ambushed soldier, or police officer in an accident, for example, couldn’t send a distress signal to a central command post. But the smart clothing would have this capability.

Kotov says a communication device such as a mobile phone could conceivably transmit information from the clothing to a central command post.

“The concept of electrically sensitive clothing made of carbon-nanotube-coated cotton is flexible in implementations and can be adapted for a variety of health monitoring tasks as well as high performance garments,” Kotov said.

It is conceivable that clothes made out of this material could be designed to harvest energy or store it, providing power for small electronic devices, but such developments are many years away and pose difficult challenges, the engineers say.

by Bob Haavind, Editorial Director, Solid State Technology

Dec. 16, 2008 – New memory concepts and the latest 32nm CMOS with metal gates and high-k dielectrics were highlights of the 2008 International Electron Devices Meeting (IEDM) in San Francisco, Dec. 15-17. A wide range of innovative device technology, including 3D wafer-level integration and a nanowire battery were also presented.

Rapid improvement in memory, especially flash memory now so widely used in digital cameras, notebook PCs, and other mobile devices, was described by Stefan Lai of Being AMC (formerly with Intel) in a plenary talk. He cited work to push flash toward 32nm and beyond, including the TANOS process from Samsung which incorporates a charge-trapping layer rather than a floating gate to minimize cell-to cell coupling, thus solving short channel effect problems. Another advancement from Kinam Kim from Samsung was the hemi-cylindrical FET where channel length extends above the planar silicon surface with the TANOS charge-trapping layer wrapping around. This will allow flash to be scaled down to sub-32nm nodes, Lai said, but at these sizes NAND flash faces a bigger challenge. Only a few hundred atoms are in the charge-trapping layer, and in a multi-layer cell (MLC) only tens of electrons separate storage layers. With leakage during cycling, these few electrons will quickly be depleted, which may be OK for some consumer uses, such as memory cards for cameras, but not for the solid-state disk (SSD) in servers, Lai pointed out.

Nevertheless, Lai expressed confidence that innovative memory advances would push beyond such barriers, like some being reported at the 2008 IEDM. He cited previous work on 3D NAND layers on a single chip by Samsung, Macronix, and Toshiba, using shared lines and making a whole stack of control gates in a single step in Toshiba’s bit-cost scaleable flash. Crosspoint memories can be stacked in 3D, but process temps must be kept within limits as each layer is added, Lai pointed out. If pushed beyond 400°C, tungsten may have to be used instead of copper lines, for example.

Lai cited work being reported by SanDisk and Toshiba at IEDM 2008 to enable what they call “super multilevel NAND flash” — still using a floating gate, but with tight Vth and sheet resistance control to push this technology to 32nm and beyond.

One solution to charge retention problems is to “get away from a charge storage transistor altogether,” Lai said. Device resistance may be changed by applying an electric field or current, he pointed out. A stack-friendly all-oxide 3D RAM, or resistance RAM, was reported by M.-J. Lee et al of Samsung, for example. It uses a GaInZnO peripheral TFT using low-temperature processing steps demonstrated by fabricating the devices on glass substrates. A specialized stacked-memory structure in a cross-point grid minimizes chip real estate.

A more exotic approach is a carbon-based resistive memory technology reported by Frans Kreupl, et al of Qimonda. The group demonstrated feasibility for resistive memory elements of graphene-like conducting and insulating carbon as well as carbon nanotubes. This report was part of an entire IEDM session devoted to work on graphene and carbon nanotube devices.

Most likely to reach commercial production first, however, according to Lai, are phase-change memories. In a PCM device, switch current from an electrode to a chalcogenide material heats the region around the contact, which makes it amorphous or high-resistance, and quenched to make it crystalline, or low-resistance. Study of such factors as retention loss and transient effects of delay, switching, and recovery, were reported at this year’s IEDM as these devices evolve toward smaller structures and tighter pitches to make them commercially competitive.

Lai suggested that these exotic multilayer memories require repetitive processing that may need only 10-15 process tools, so this might be done in a minimal fab while the layer of complex circuitry for drivers and read sensors might be farmed out to a foundry. He also pointed out that in memory there is no such thing as “perfect data,” so new system approaches may have to evolve to deal with defects. He cited work by Systems Genetics Inc., Longmont, CO, that uses a special processor and compensation engines in a systems approach to double capacity gain and greatly boost endurance for advanced NAND devices.

The hard-disk drive (HDD) field has a larger toolbox to deal with imperfect or noisy data, and their techniques might be adapted in future multilevel memories, according to Lai.

Three-dimension (3D) chip integration using through-silicon vias (TSV) also was an important topic at IEDM, including a report on a wafer-level scheme reported by F. Liu, et al of IBM. It incorporates 25μm TSVs with 17:1 aspect ratio drilled by RIE with tungsten interconnects. Lock-and-key structures ensure that there is no lateral shift between wafers during a hybrid copper-adhesive bonding step.

A novel multichip module integration approach using self-assembly with defined hybrid hydrophobic areas and liquid evaporation for positioning chips was reported by T. Fukushima et al of Tohoku U. in Japan. It achieved about 400nm alignment accuracy.

Nanowire battery technology for next-generation electronics was reported by Yi Cui, et al, of Stanford U. Energy density for batteries has been advancing only about 8% a year thanks to packaging improvements, but this is reaching limits so new concepts are needed, Cui reported. The graphite anode in lithium batteries has very limited charge storage capacity, but higher capacity materials like silicon or germanium swell too much during alloying in bulk materials. Nanowires, however, offer an alternate approach. Studies of potential nanowire structures showed most promise for lithium inserted into silicon nanowires, but there is a problem keeping the silicon crystalline through charging cycles. The group has devised nanowire structures in which a silicon core remains crystalline under constant charging for 145 cycles with 95% charge retention, and offering about 6× the storage capacity of carbon, which shows promise for commercialization, according to Cui. The group developed a CMOS-compatible process to fabricate these silicon-lithium nanowires for on-chip power sources.

Among reports on 32nm second-generation high-k metal gate (HK+MG) CMOS logic was a late paper by S. Natarajan et al, Intel, with enhanced channel strain, which achieves the highest drive current yet for nMOS. Another late paper by NEC reports a cost-effective approach to a 32nm CMOS platform using advanced single-exposure lithography with custom illumination to avoid the extra steps of dual exposure and double patterning. A gate-first HK+MG process was described.

Despite the weak economy, attendance for the conference remains fairly high, with over 300 attendees to the Sunday short course on 22nm CMOS technology, for example. — B.H.

Let’s Hope They Eventually Come Back
By Jim Walker, Gartner/Dataquest
Even though we all like to hear “Merry Christmas” and “Happy New Year” during this holiday season, our worldwide financial meltdown has made it much less cheerful. The outlook for 2009 is very bleak for worldwide economies and, more specifically, the semiconductor industry. I would love to say that Gartner/Dataquest’s outlook for the industry in 2009 will be optimistic, but I can’t. But I don’t want to say that the second Great Depression within a century is upon us yet, either. However, it definitely time to tighten the belt and save for a rainy day.

Never before has the semiconductor industry experienced two negative growth years back-to-back. And, never before has the semiconductor industry witnessed such a sharp one quarter drop in demand and orders. The bad news just keep getting worse as companies warn investors that the financial crisis will have an unprecedented impact on fourth quarter 2008 and year 2009 sales and profits.

Gartner expects Q408 semiconductor sales to show a record quarter-on-quarter drop of 24%, well beyond the 20% record set in the second quarter of 2001. Our 2008 preliminary semiconductor market share results revealed that 2008 revenue declined over 4.4%, much worse than our 0.2% growth we had forecasted just a month previous. For 2009, the outlook has changed substantially as well. Our most-like scenario indicates a 16.3% decline in revenue for the semiconductor industry in 2009, with the trend to our downside risk scenario of a 24.7% decline appearing to be more possible as the days pass.

Some of the end-product market segments will fare better than others for 2009. PC unit growth will be down 5%, with netbooks and notebooks doing much better than desktops. Cell phone units will be lower by almost 10%. Consumer products will retrench over 15%, as all of us begin to do without.

Memory, specifically DRAM, will be in a precarious position for 2009 as well. This part of the industry has been down in the dumps for over 18 months and the losses by the various companies in the market are nearing the $12B mark. The market is very unstable, with some suppliers asking for government assistance while trying not to be forced into bankruptcy or mergers.

Capital spending will be cut across the board in 2009. Semiconductor manufacturers are currently experiencing global recession, plunging demand, excess inventories, a severe credit crunch, and bankruptcies (especially memory, as mentioned earlier). Companies are responding by cutting capital spending drastically to protect what is left. Cash flow management is paramount. The result will be capital spending declining by over 34% in 2009. More specifically, we believe that wafer fab equipment will decline -33% in 2009. In addition, packaging and assembly equipment will contract by over -28%, while the ATE market will fall for the third straight year at almost a -20%.

So, with all the bleak news, what can one do to keep the doors open and the operations going?

The global recession came at a time when the overall semiconductor and semiconductor equipment industries were already in a vulnerable position. The excess spending in memory sectors drove the overall financial performance of companies in those segments to record losses even before the grim reality of recession had set in.

As the global economic recession continues on its downward spiral, this will accelerate contraction in the overall semiconductor market. Semiconductor suppliers across all segments of the industry have begun to lower production rates and close fabs that are not cost effective. Companies are instituting mandatory multiple week shutdowns which will affect Q4 08 and Q1 09 production rates. Previously planned fabs are being postponed. What little capex remains is being selectively focused on new technology. As 2009 progresses, we will see consolidation in all sectors of the industry, whether it be devices, equipment or manufacturing services.

We recommend manufactures prepare for the worst. The industry is in the midst of what will be remembered later as the worst crises in its young history. The industry will emerge looking leaner and better prepared for a future of long-term slower growth. One thing will be certain: the quest for new and more advanced technology will continue, and more advanced manufacturing will lead the way out of the current doldrums into a period of profitability.

JIM WALKER, principle analyst, may be contacted at Gartner Inc., 251 River Oaks Parkway, San Jose, CA 95134; [email protected].

December 15, 2008: It’s hard to study something with any rigor if the subject can’t be produced uniformly and efficiently. Researchers who study double-walled carbon nanotubes find themselves in just this predicament. Current techniques for synthesizing double-walled carbon nanotubes also produce unwanted single- and multi-walled nanotubes.

Two Northwestern University researchers have solved the problem using a technique developed at Northwestern, called density gradient ultracentrifugation, to cleanly and easily separate the double-walled nanotubes (DWNTs) from the single-walled nanotubes (SWNTs) and multi-walled nanotubes (MWNTs). The sorting method works by exploiting subtle differences in the buoyant densities of the nanotubes as a function of their size and electronic behavior. The results will be published online Sunday, Dec. 14, by the journal Nature Nanotechnology. The paper also will appear as the cover story in the January 2009 issue of the journal.

“Nanomaterials possess the unique attribute that their properties depend on physical dimensions such as diameter,” said Mark C. Hersam, professor of materials science and engineering in Northwestern’s McCormick School of Engineering and Applied Science, professor of chemistry in the Weinberg College of Arts and Sciences and the paper’s senior author. He collaborated with Alexander A. Green, a graduate student in materials science and engineering at Northwestern and lead author of the paper, titled “Processing and Properties of Highly Enriched Double-Walled Carbon Nanotubes.”

Using the Northwestern method, carbon nanotubes first are encapsulated in water by soap-like molecules called surfactants. The surfactant-coated nanotubes then are sorted in density gradients that are spun at tens of thousands of rotations per minute in an ultracentrifuge. Each nanotube’s diameter and electronic structure help determine the nanotube’s buoyant density, which enables the method to separate DWNTs from the SWNTs and MWNTs.

The double-walled nanotubes, the researchers discovered, were approximately 44 percent longer than the single-walled nanotubes. This longer length of the DWNTs results in a factor of 2.4 improvement in the electrical conductivity of transparent conductors.

Double-walled nanotubes also enable improved spatial resolution and longer scanning lifetimes as tips for atomic force microscopes and are useful in field-effect transistors, biosensing and drug delivery.

December 15, 2008: MIT engineers have developed carbon nanotubes into sensors for cancer drugs and other DNA-damaging agents inside living cells. The sensors, made of carbon nanotubes wrapped in DNA, can detect chemotherapy drugs, such as cisplatin, as well as environmental toxins and free radicals that damage DNA.

“We’ve made a sensor that can be placed in living cells, healthy or malignant, and actually detect several different classes of molecules that damage DNA,” said Michael Strano, associate professor of chemical engineering and senior author of a paper on the work appearing in the Dec. 14 online edition of Nature Nanotechnology.

Such sensors could be used to monitor chemotherapy patients to ensure the drugs are effectively battling tumors. Many chemotherapy drugs are very powerful DNA disruptors and can cause serious side effects, so it is important to make sure that the drugs are reaching their intended targets.

“You could figure out not only where the drugs are, but whether a drug is active or not,” said Daniel Heller, a graduate student in chemical engineering and lead author of the paper.

The sensor can detect DNA-alkylating agents, a class that includes cisplatin, and oxidizing agents such as hydrogen peroxide and hydroxyl radicals.

Using the sensors, researchers can monitor living cells over an extended period of time. The sensor can pinpoint the exact location of molecules inside cells, and for hydrogen peroxide, it can detect a single molecule.

The new technology takes advantage of the fact that carbon nanotubes fluoresce in near-infrared light. Human tissue does not, which makes it easier to see the nanotubes light up.

Each nanotube is coated with DNA, which binds to DNA-damaging agents present in the cell. That interaction between the DNA and DNA disruptor changes the intensity and/or wavelength of the fluorescent light emitted by the nanotube. The agents produce different signatures that can be used to identify them.

“We can differentiate between different types of molecules depending on how they interact,” Strano said.

Because they are coated in DNA, these nanotube sensors are safe for injection in living cells. In future studies, the researchers plan to use the sensors to study the effects of various antioxidants, such as the compounds in green tea, and learn how to more effectively use toxic chemotherapy drugs.

IEDM Day 1: Dense data on 22nm


December 15, 2008

by Dick James, senior technology adviser, Chipworks

Editor’s Note: Each day during IEDM, Chipworks’ Dick James will share his thoughts on what he saw as the best presentations.

Dec. 15, 2008 – Sunday at IEDM is always short course day, and this year’s two topics were on “22nm CMOS Technology” and “More than Moore: Technologies for Functional Diversification.” One of the courses is usually a focus on potential technologies for a couple of process generations ahead (e.g., 22nm). This is perhaps looking a bit far ahead, since 45nm is hardly well established yet; Intel and Panasonic have been the only two players until AMD’s recent entrance.

I took in the 22nm course, although there were a couple of sessions in the other I would like to have been at — Tom Lee and Albert Theuwissen are both entertaining speakers, and their respective perorations on RF/analog and CMOS imaging (both pretty hot market segments at the moment) would have been interesting.

The 22nm course was kicked off by the ever-genial Hiroshi Iwai, with a run-through of technology scaling through the lens of the 2008 ITRS. In essence, he detailed the changes to the 2008 update (due out at year’s end), in particular reflecting the slowing rate of scaling that we have seen in recent years, so that at 22nm Vdd, gate length, EOT, and xj will all be larger than predicted in the last ITRS. Correspondingly, the life of bulk CMOS and the adoption of multi-gate devices (MuGFETs) has been pushed out by eight years. And of course the k-value of interlevel dielectrics has slipped again — a bit ironic, since we have just found our first 2nd-gen low-k part using Fujitsu’s nano-clustering silica with a claimed k of ~2.25, putting them ahead of the ITRS prediction.

Iwai finished his talk with his personal roadmap of technologies beyond CMOS, with Si nanowires and germanium or III-V channel MOSFETs being the short-term prospects, and carbon nanotubes, graphene, and other prospects out “in the clouds”. Nanowires are his preference, because of better short-channel effects.

Next up was Kelin Kuhn of Intel, who gave the most amazing review of the challenges in achieving manufacturable 22nm from the device perspective — a hundred densely packed slides in an hour with well over a hundred references. She described the problems caused by increased resistance (SDE and silicides) and fringe capacitances, gave a detailed explanation of mobility and orientation effects, and discussed high-k/metal gate methodology and the pros and cons of planar CMOS vs. MuGFETs/FinFETs. She made one point about MuGFETs that hadn’t occurred to me — essentially they are quantised transistors, since larger transistors have to be made from many units of a single gate crossing the fin substrate, so a whole different modeling regime applies before you even get into the design cycle. At the end of this avalanche of information, Kuhn summarized by saying that 22nm is likely to be planar, evolved from current technology. MuGFETs won’t happen soon; there are just too many risks involved for them to become real in the next five years.

After lunch, Geert Vandenberghe from IMEC discussed the lithography options, covering wet lithography and EUV and the associated problems with mask and reticle design and manufacture. He also went through the different types of double masking and patterning — although strangely absent was the subtractive double patterning practiced by Intel, in which gates are first patterned as continuous parallel lines and then cut into dummy and functional segments by a second etch mask.

Jeff Gambino of IBM gave a good overview of the BEOL challenges, taking it beyond the usual problems with super-narrow lines and super-fragile low-k dielectrics, also discussing air-gap techniques, packaging including TSVs, and reliability problems.

Finally, Purdue University’s erudite academic Kaushik Roy reviewed device and circuit interactions. The inherent variability of processing and structures at nodes 45nm and below can make device operation unpredictable, never mind the increased leakage. He detailed some of the circuit techniques used to mitigate the problems, such as high- and low-Vt transistors, gated blocks of memory, and the like. Some of them have been around for a while, but the need at 22nm becomes even greater. Judging by some of his slides, he’s been working with Intel, and the comments on dual-Vt made me wonder if his work had an input into Intel’s SoC/Dual Vt paper to be presented on Wednesday.

By that end of the afternoon we were getting punch-drunk with an excess of information, but all in all, a good and informative day. I do have some criticism for the facility side of the course — too many of us crowded into too small a space, I gather there were over 300 attendees — and the coffee ran out! Not quite as bad as sitting in a full 747, but getting there.

For my money, Kelin Kuhn gets the Data Density of the Day award (definitely not a criticism); hers was an extremely well-structured talk, though most people would have taken a full morning to deliver it! Now for the conference proper. — D.J.

DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected], www.chipworks.com.

by Debra Vogler, senior technical editor, Solid State Technology

Results of a study slated to be discussed by SEMATECH researchers at this week’s IEDM highlight the importance of the process sequence on performance, variability, scaling, interface quality, and reliability for LaOx capped HfSiON/metal gate structures (“Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node,” J. Huang, P.D. Kirsch, et al.). The group found that an SiON interface layer (IL) is a valuable scaling aid with leakage current (Jg) >200× lower than with an SiO2/polySi IL. Reduced La diffusion to the IL, they note, is what enables an SiON IL to prevent performance degradation.

By optimizing the process sequence, the LaOx cap thickness, and the SiON IL, the researchers were able to address PBTI (positive bias temperature instability) and mobility degradation issues of a low Vt HfSiON+LaOx gate stack. A high Ion/Ioff (1250μA/μm/100nA/μm) performance of 0.31 Vt,lin nFETs was achieved without using a strain booster. The group concludes that such a gate stack is realistic for 22nm node LOP (low operating power) applications.

The group noted that previous work (S. Kamiyama et al., IEDM Tech. Dig., p. 539, 2007) had shown that, although Vt was low when using an SiOn/HfSiON+LaOx stack with 0.68nm EOT at 32nm half-pitch, Ioff was too high for the 22nm LOP application.

This type of gate stack is of interest to the logic community, particularly the low standby power and low operating power communities, according to SEMATECH researcher Paul Kirsch. “The reason we focused on low operating power is that we were able to meet both the gate current density and equivalent oxide thickness for that particular product offering,” he told SST — though, he added, “That’s not to say that it’s inappropriate for the high performance applications.”


Figure 1: Nitridation process sequence affects Vt tuning ability. Maximum Vt tuning is ~700mV. (Source: SEMATECH)


Figure 2: Mobility is degraded with LaOx thickness and nitridation process. (Source: SEMATECH)

A basic problem the industry has encountered, Kirsch explained, is a mechanistic understanding that a small amount of nitrogen in the bottom IL is quite beneficial over an SiO2 IL. However, there had not been the same understanding with respect to a high-k LaOx capped metal gate stack. Previously, the semiconductor community had put the LaOx on top of the high-k dielectric and it was done without understanding the nitridation process sequence. In the current SEMATECH paper, the data shows that with the SiON IL, the bias temperature instability reliability and the transconductance metrics are improved as is the amount of Vt tuning with the SiON IL, which is not possible with the SiO2 IL. “What we’ve shown here (see Figures 1, 2) is that it’s actually beneficial to put the LaOx cap down before doing any nitridation,” Kirsch told SST. “We’ve seen an advantage in the amount of Vt tuning and in the high-field mobility we can achieve.”


Figure 3: Ion/Ioff performance of 0.31 Vt,lin nMOSFET with 0.74nm EOT. (Source: SEMATECH)

According to Kirsch, the Ion/Ioff improvement achieved by the group (Figure 3) suggests that the industry will be able to scale down to ~0.7nm and continue to see Ion/Ioff benefits. Additionally, the researchers’ were able to achieve a Vt uniformity (Figures 4, 5) that is equal to a little better than 30mV across the wafer, which, Kirsch noted, is typically a metric of manufacturability of the technology. — D.V.


Figure 4: Optimized LaOx cap process type reduces Vt variation. (Source: SEMATECH)


Figure 5: Optimized LaOx cap process sequence reduces Vtvariation. (LBN = LaOx capped before nitridation; LAN = LaOx capped after nitridation.) (Source: SEMATECH)

The Riley Report


December 15, 2008

The 3-D Brawl
This month’s 3-D symposium at the MRS Fall Meeting showed that 3-D, whether based upon through-silicon via (TSV) or one of its rivals, has entered a new stage &#151 brawling. This is encouraging. Laboratory technologies, like newborn babes, require the full attention of their owners. It isn’t until the newcomers creep out of the lab to face their rivals that conflicts begin. By next December, some winners should be in production. The symposium’s six sessions, devoted to “Materials and Technologies for 3-D Integration,” covered integrated processes, vias, plating, wafer thinning, bonding, and applications.

Many choices must yet be made to reach integrated manufacturing. These include where (front end or back end), when (beginning, end, or somewhere in between), how (drilling, plating, thinning, bonding, packaging) and why (lower cost or higher performance) manufacturing should proceed. All of these topics elicited differing opinions and contrasting recommendations somewhere in the 45 or so papers.
The opening survey paper by Fraunhofer IZM presented an overview of 3-D process requirements and challenges. It concluded that many individual processes have been demonstrated, but the critical infrastructure elements have yet to be brought together to achieve acceptable time to market, cost, reliability, and performance for volume production.

A typical choice is between stacking wafers on wafers, versus stacking singulated die on wafers. MIT Lincoln Labs reported their wafer on wafer stacking of fully fabricated SOI wafers. Others voiced good reasons to assemble die on wafers. SUSS Micro Tec, who sells equipment for both approaches, suggested both: die-on-wafer to avoid differences in die sizes, wafer sizes, and KGD yields in mixing CMOS with other technologies; wafer on wafer to maximize throughput and minimize cost in homogeneous integration of high-yield devices. Pay your money and take your pick!

TSV dominated the interconnect choices. However, even TSV advocates are split between those who prefer high-aspect ratio vias to minimize wafer thinning, and those who prefer additional wafer thinning in exchange for lower-aspect vias. A Bosch presentation on the history and success of the widely used deep reactive ion etch ( “DRIE” or “Bosch” process), was followed by a paper from Xsil advocating diode-pumped solid-state laser drilling as a faster and simpler way to open fine-pitch vias for plating.

Plating itself presented many variations. Those of us unfamiliar with plating think of it as a simple process: mix up a proper bath, turn on the switch, and on it goes. Semitool provided a concise education in the complexity of deep via plating. The problem is to uniformly fill the vias from the bottom up without voids, despite the dynamic changes occurring during deposition.

Semitool’s plating solution (pun intentional) is precise control of the bath components, and continuing adjustments of the electrical current. They find that each wafer type requires a unique recipe, based upon the number of vias, their size, and their pattern density.

IMEC identifies uniform filling of the vias as only part of the problem; reducing the plating time while maintaining void-free quality is the real challenge. IMEC also reported statistical comparisons of four common thinning methods (rough grinding, fine grinding, CMP, and plasma etch) on silicon wafer strength. A major unexpected conclusion is that the grinding mark orientation plays a key role in determining resulting wafer strength.

CEA-Leti presented daisy-chain testing results statistically relating plating process parameters to the electrical performance of the resulting TSV. Their test vehicle vias are 3 to 5&#181m in diameter and 12 &#181m long, on 30&#181m pitch. They achieved yields above 90% for daisy chains with 3,200 TSVs.

STMicroelectronics has developed thin silicon film layer transfer as a solution for deep submicron-diameter via layer interconnections. Monolithic integration with sequential processing avoids the limitations that prevent alternative current approaches from addressing these dimensions.

Ziptronix reported extension of their proprietary Cu-Cu direct bonding technology to 1.5 &#181m pitch. The planar oxide bond technology requires only simple alignment and placement to bond wafers or die which have received a suitable surface activation.

In conclusion, these clashes of ideas are a vital step in developing integrated manufacturing for 3-D assembly. I look forward to hearing from the survivors next December.

Contact George RIley

December 12, 2008: People said it couldn’t be done, but researchers from the University of Pittsburgh and the U.S. Department of Energy National Energy Technology Laboratory (NETL) in Pittsburgh demonstrated a molecular chain reaction on a metal surface, a nanoscale process with sizable potential in areas from nanotechnology to developing information storage technology. The researchers report in the Dec. 12 edition of Science that a single electron caused a self-perpetuating chain reaction that rearranged the bonds in 10 consecutive molecules positioned on a gold surface. As each molecule’s original bond was broken by the reaction, the molecule rearranged itself to form a new molecule.

Study coauthor Kenneth Jordan, a Distinguished Professor of Chemistry in Pitt’s School of Arts and Sciences and co director of the University’s Center for Simulation and Modeling, said that the ability to initiate molecular chain reactions and self-assembly has potential applications in information storage and in nanolithography, a process used in producing microchips and circuit boards.

Because the demonstrated reaction involved several molecules on a surface, it reframes researchers’ understanding of surface-based chain reactions. “The conventional wisdom held that a surface reaction would fizzle soon after the electron was introduced,” Jordan said. “Our work, however, shows that reactions on metal surfaces can be sustained over long distances.”

Jordan and his colleagues worked with dimethyldisulfide molecules — two CH(3) methyl groups bonded by two adjoining sulfur atoms. The added electron split the bond between the sulfur atoms of one molecule, creating a highly reactive free radical that attacked the sulfur-sulfur bond of the neighboring molecule. The radical split the bond, resulting in a new molecule and a new radical that proceeded to the sulfur-sulfur bond of the next molecule. The process repeated itself through a series of molecules.

The ProberBench Operating Environment, from SUSS MicroTec Test Systems, is a full-featured software suite designed for efficient, intuitive and safe wafer-level probing. Development of the interface and architecture was reportedly based on a three-month user study in the laboratories semiconductor design houses and manufacturers, who expressed needs such as less confusing interfaces, automated procedures, and easy-to-read feedback.

The new software includes a control center, which places navigation and control elements at the user’s fingertips and providing instant feedback about wafer and probe positions. Also included is the SPECTRUM Vision System, which is the main vision application and supports up to four live video feeds like ContactView &#151 a horizontal view of the probe tips and wafer for eliminating probe card and wafer damage &#151 and an upward-looking camera for viewing the tips of fine-pitch, vertical probe cards.

Optional automation tools include a tool for automatically aligning the wafer and generating a wafer map. It is also designed to communicate with test executive software like Agilent’s IC-CAP, Keithley’s KITE, ProPlus’ BSIMPro and many others. Combining this feature with SUSS MicroTec’s unique Automated Thermal Management and ReAlign Technology enables unattended test routines over multiple temperatures that can be run overnight and on weekends. SUSS MicroTec Test Systems Dresden, Germany, www.suss.com.