By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 3D ASIP conference, one of the themes of this years conference was the coming of age of 3D stacked memory which now comes in several flavors from several vendors. This week, we’ll look at the Yole review and next week finish off with a look at the presentations by Toshiba, Hynix, Micron, AMD and Tezzaron.

Yole

In the plenary presentation, Thibault Buisson of Yole spoke on the “Comparison of new Memory Architecture -3D TSV Memory Packaging trends!” Some of the recent product and technology announcements are shown below. After MEMS and CIS, stacked Memory has become the next segment to see adoption of TSV technology. Graphics has been the first application using 3D stacked memories.

All of the major memory suppliers ow have TSV based memory stacked products.

Yole estimates that the SK Hynix HBM stack price with an assumption of 50% gross margin will range from $12.68 to $18.01 per stack.

They further conjecture that the AMD Radeon pricing rages from $191 to $258 with the GPU dies represening 43% of the component cost; the (4) HBM stack representing 28% , the silicon interposer representing 14% and the package subsrate 12%

Toshiba has announced the world’s first NAND flash memory packages integrating (16) 128 Gb NAND memory devices connected together using TSV. The multi-layer chips feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50% less energy on write operations, read operations, and I/O data transfers than Toshiba’s current memory products. (see more below)

The stacked memory supply chain is also clarifying.

1. The HBM stack (memory dies, logic die) is made by Memory Manufacturer
2. The GPU die is manufactured by wafer foundry
3. The interposer is also manufactured by wafer foundry (could be a different one compare to GPU)
4. The PCB package substrate is made by a substrate manufacturer
5. The final assembly (HBM, GPU, interposer, interposer on PCB, passives assembly and BGA balls) is performed by an OSAT.

X-sect comparison of Hynix HBM to Samsung stacked DDR4 is shown below.

On the Passing of Moore’s Law

Every once in awhile you find an article and say “this is great, this is exactly as I would have written it”

I recently found such an article on the passing of Moore’s Law …or…as the author Peter Bright states it

“…Moore’s Law has passed away at the age of 51 after an extended illness” [link]

I hate to take up space just quoting him, but as I said I couldn’t have written it any better, so…

“In the 2000s, it [became] clear that … geometric scaling was at an end, but various technical measures were devised to keep up the pace of Moore’s law…. At 90nm, strained silicon was introduced; at 45nm, new materials to increase the capacitance of each transistor layered on the silicon were introduced. At 22nm, tri-gate transistors maintained the scaling.

Even with EUV, it’s unclear just how much further scaling is even possible; at 2nm, transistors would be just 10 atoms wide, and it’s unlikely that they’d operate reliably…as the transistors are packed ever tighter, dissipating the energy that they use becomes ever harder.

The new techniques, such as strained silicon and tri-gate transistors, took more than a decade to put in production. EUV has been talked about for longer still. There’s also a significant cost factor. Technology may provide ways to further increase the number of transistors packed into a chip, but the manufacturing facilities to build these chips may be prohibitively expensive.

Compounding all this is that all these extra transistors have become increasingly hard to use. In the 1980s and 1990s the value of the extra transistors was obvious: the Pentium was much faster than the 486, the Pentium II much faster than the Pentium. Those easy improvements stopped coming in the 2000s. Constrained by heat, clock speeds have largely stood still, and the performance of each individual processor core has increased only incrementally. What we see instead are multiple processor cores within a single chip. This increases the overall theoretical performance of a processor, but it can be difficult to actually exploit this improvement in software.

These difficulties mean that the Moore’s law-driven roadmap is now at an end. ITRS decided in 2014 that its next roadmap would no longer be beholden to Moore’s “law,” and… the next ITRS roadmap, published next month, will take an approach it describes as “More than Moore.”

IFTLE is in full agreement, as you know IFTLE thinks technologies like 2.5 and 3DIC have replaced Moore’s Law. May Moore’s Law rest-in-peace…

Those who continue to preach that “Moore’s Law is still alive and well” are akin to those who claim to have seen Elvis yesterday on the streets of Nashville!

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Samsung announces 4GB HBM2 DRAM

Samsung Electronics announced that it has begun mass producing the industry’s first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, and enterprise servers. [link]

The newly introduced 4GB HBM2 DRAM, uses Samsung’s 20nm process technology and is reportedly more than seven times faster than the current DRAM.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains > 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Samsung’s new DRAM package features 256 GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

Samsung also plans to produce an 8GB HBM2 DRAM package in the next 12 months. Offering designers a 95 percent space savings vs GDDR5 DRAM.

Samsung announced that production volume of HBM2 DRAM will increase over the remainder of the year.

The second-generation HBM (HBM2) technology is outlined by the JESD235A standard. It uses 128-bit DDR interface, 1024-bit I/O, 1.2 V I/O and core. Just like HBM1, HBM2 supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks). HBM Gen 2 expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 2 Gb/s per pin.

Continuing our look at the 2015 3D ASIP Conference…

Prismark

Brandon Prior of Prismark addressed the “Status of 2.5/3D and other high density packaging technologies”.

2.5D / Silicon Interposer is an effective fine-pitch solution to provide >10,000 die-to-die connection. Currently used for:

– ASIC/FPGA die partition

– GPU/CPU/ASIC + memory

– For L/S <2μm and vias <5μm, Si interposer is the only available approach

• Several notable production developments with 2.5 and 3D technology in 2015

– All major DRAM players with production capability of TSV memory stacks; but focus remains on “near memory” requiring extremely high bandwidth

– Si Interposer adoption by AMD for “gaming enthusiast” GPU

– Continued work with TSV for Image and other sensors for backside access

• Increased adoption of 2.5 and 3D TSV dependant on cost and alternatives

– Si Interposer most relevant to server/telecom CPU and ASIC products

– TSV for portable processors still under review, but LPDDR5 is more likely

• Companies such as Sony, Toshiba, Aptina, ST have been shipping image sensors with TSV for back side access since 2009/2010
• Sony is first to ship using die stacking “hybrid” approach in 2012/2013; economical only for 8 – 13MP designs

ADVANCED PACKAGE SUBSTRATE DESIGN RULES

• Substrate technologies continue to progress

– 10-12μm L/S in HVM for MPU

– 8μm L/S capabilities in process at Kyocera, Ibiden, Shinko and others

• Sub-5μm on organic is a challenge

– RDL technologies used in FO-WLP or Si Interposer are looking to displace build-up substrates

• Ibiden and Shinko working on “organic interposer”

– Internal qualification now down to 2μm L/S and vias 10-25μm

– Yield remains a challenge, so Si Interposer remains compelling alternative

FO-WLP MARKET STATUS

• Expectation is that Apple will proceed with TSMC InFO FO-WLP for A10 in 2016

– Tool orders and capacity seen in supply chain

– Speculation on second location/source being required

• OSATs see uptick in interest for products outside application processor

– OSATs: JCET/STATS, ASE, SPIL, Amkor, Nanium, PTI, DECA and Inotera

– Possible Customers: Marvell, Qualcomm, Mediatek, Dialog, Renesas, Infineon,

Freescale, Avago, Analog, Spreadtrum, Maxim, HiSilicon

• Most focus on smaller die/packages: 3×3 to 8x8mm

– “Large die FO-WLP remain too expensive and yield challenged”

– Expect 1 and 2 die packages with hundreds of I/O in 2016 from multiple applications and companies

– Most production of FO-WLP focused on 1-3 layer RDL at 5-15μm L/S.

– 300mm reconfigured wafers remains dominant approach for now

• Intel and Samsung remain skeptical of FO-WLP

– At this time, neither have plans to install fan out capacity

– Not seen as cost effective means to make a thinner package

Northrup Grumman / DARPA DAHI Program

After DARPA program Manager Dan Green gave an introductory presentation on the DARPA goals for DAHI (Diverse Accessible Heterogeneous Integration) [see IFTLE 206, “COSMOS and DAHI Herald the Era of 3D Heterogeneous Integration” ] Augusto Gutierrez-Aitken detailed DAHI activity in NGAS.

DAHI seeks to create circuits from various CMOS nodes with SiGe, GaN and/or InP.

They have developed a basic foundry infrastructure allowing external design teams to generate multiple technology heterogeneously integrated circuits

• Developed a process to integrate multiple compound semiconductor technologies to CMOS wafers
• Demonstrated three-technology integration between IBM 65nm CMOS, NGAS TF4 InP HBT, and NGAS GaN20 HEMT
• Demonstrated integration of third-party technology

A typical NGAS DAHI flow is shown below.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Beginning coverage on the 2015 3D ASIP (Architectures for Semiconductor Interconnect and packaging) conference sponsored by RI Int which is the final major high density packaging conference of the year.

This years technical Chairs were Prof Mitsumsa Koyanagi from Tohoku Univ. and Rama Alipati from GlobalFoundries.

Professor Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the Conferences first recipients of the “3DIC Pioneer Award”. After more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, 3D ASIP management were convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first to recognize what 3DIC could do, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Sony

Hirayama of Sony detailed their work on 3DIC based CMOS image sensors.

AS shown below, the color pixels require fewer metal interconnect layers and high voltage, lower temperatures during processing and longer anneal times whereas the logic portions of the circuit are quite the opposite needing many more layers of interconnect and low voltage, higher processing temps and shorter anneal times. It therefore makes sense to fabricate these layers separately and stack them.

This separation of circuits and functions is shown below.

Sony introduced this technology in 2012 and by 2015 had more than 2/3 of their shipped CIS using this method of fabrication.

In the future, Sony sees introduction of processors and memory to this stack.

SPIL Acquisition

Digitimes estimates that more than $893MM worth of SPIL orders are moving to other OSAT companies due to the potential acquisition by ASE [link].

As we have discussed previously [see IFTLE 252 ‘ASE Makes Bid for Siliconware Shares…” ], ASE has previously acquired a 25% stake in SPIL through an unsolicited tender offer, and has launched another tender offer to buy more shares of SPIL which will bring its total ownership interest in the company to almost 50%. ASE has also disclosed its goal is to acquire the rest of SPIL shares, i.e a complete takeover as IFTLE initially projected. .

SPIL now reports that fabless “..chip vendors such as Qualcomm, Broadcom and MediaTek all try to diversify their suppliers to reduce supply risks”. Thus the other IC assembly and test services companies will benefit from ASE’s potential takeover of SPIL. SPIL points to Amkor, China-based Jiangsu Changjiang Electronics Technology (JCET) and Taiwan’s Powertech Technology (PTI) as the beneficiaries.

Consolidation of Notebook computer vendors.

Digitimes also reports that Japan-based PC vendors Sony, Toshiba and Fujitsu are reportedly finalizing talks to merge their notebook businesses into one company [link]. Post merger Sony, Fujitsu and Toshiba would account for 30% of Japan’s notebook market, compared to 29% held by the NEC/Lenovo joint venture.

For all the latest in 3DIC and other high advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Finishing our look at IMAPS 2015…

ULVAC – TSV etching

ULVAC has developed an etch tool capable of both Bosch etching and their “direct etch” process. Direct etch uses a mix of SF₆ and O₂ and can result in either a sloped or straight sidewall as shown below. They claim that the direct etch results in significantly shorted PVD time and that the taper vias can result in 80% less electro dep time when filling the vias.

Tanaka Kikinzoku – Gold sealing technology

Tanaka Kikinzoku shared their results on hermetic low temp sealing for MEMS and WLP. They developed a wafer level hermetic sealing process using a rim structure covered with sub micron gold particle paste by stencil printing as shown below. The maximum leak rate was found to be 10^-14 Pa·m³/s (He)

Asahi Kasei Electronic Materials

Asahi Kasssei (AKEM) shared their studies on the thermal cycle testing of organic passivations for WLSCP…well really they didn’t share them and I have a few comments about that. Through the years I have complained about reports that fail to fully identify exactly what they are examining. Many of us know them as A,B,C,D papers ….you know “A was much better than B and somewhat better than C and D.” This complaint is not pointed only AKEM, but rather at the many companies and institutes who publish such papers.

Granted such papers can lead us in the right direction if they are commenting that certain properties lead to better results, but they can never be reproduced since no one else knows what it was that was examined.

AKEM introduced their studies by indicating that previous studies had found that PBO failed thermal cycling tests (TCT) earlier than PIs and they wished to know why. The problem is that there are many different types of PIs and PBOs. The examples you choose to compare will totally control the results that you get. The only hints we get is that their PI is a low cure version (“imidization of our specific PI is finished at 200C”) Would it have hurt to give us an experimental or commercial designation ? since AKEM has not chosen to share the structure of this material with us. Even worse is the identification of the PBO. The comment is made that “..the cure temp of the typical photo PBO is over 300 °C …” It is not clear that this is the kind of example that they used and certainly not clear why they used a high temp cure PBO to compare to a low temp cure PI. Those of us in the field know that there are many low temp cure PBOs to choose from.

As an example their examination of strain change vs time (fig 11) they state that “strain is effected by the polymer difference. Equivalent strain in the case of PBO is larger than PI because the modulus of PBO is lower than PI.” Would it not be better to test two known PIs and two known PBOs of differing modulus to make this case? Since I do not know the identity of the two materials that they chose to compare, I cannot draw a clean conclusion about any of their results. I think you see the point.

ORMET – Transient Liquid Phase Sintering (TLPS)

Ormet has been around our industry since the late 1990’s optimizing their TLPS products. ORMET has recently been acquired by Merk. They view their materials as solder replacements for either hierarchical soldering (consecutive joints are soldered at sequentially lower temps) applications where solder remelt is a problem such as MEMS lid attach, SIP and PoP.   Also for high operating temp market segments such as power electronics. Basically the TLPS pastes consist of a high mp metal (copper), a low melting point alloy ( SnBi) and a flus-polymer phase. As the temp is raised the alloy begins to melt and reacts with the high mp metal to form high mp alloys or intermetallics until there is no longer a molten phase at that temp. Pastes are formulate specific to the application.

They have worked with Kemet to develop a line of pastes for MLCC attach (multi layer capacitors) for high temp applications. Such materials have passed high temp storage (175 C for 2000 hrs); thermal cycling (-40 to +175 for 2000 cycles) and temp humidity bias (50V, 85C/85%RH 2000 hrs) without any failures. Brittle Cu/Sn intermetallic phases are found to initiate some cracks but appear to terminate on the Cu particles.

For all he latest on 3DIC and other advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.

Unimicron

Unimicron discussed their continued development of < 5/5 L/S for polymeric interposer applications.

While silicon can meet fine line (< 5/5 L/S) requirements easily by wafer level processing, silicon processing cost is a barrier to many applications.

There are two types of processes available to meet fine line requirements on organic substrates, traditional semi-additive processing (SAP) or laser embedded technology. They are shown in xsect below. Unimicron reports that current status for SAP is 8/8.

UV YAG lasers allow for maskless ablation processes by ablating trenches and blind vias simultaneously, but the throughput becomes slow as the features get larger. Throughput of eximer lasers is independent of pattern features since they are defined by the mask. The aspect ratio (h/w) for eximer laser was 1.2 for 3/3 in build-up film with fine filler particles and for 5/5. In general, the finer the filler particle size, the deeper the trench. Since they found that eximer laser ablation was much slower than lithography, the next developments will be with photo build up dielectric to replace the laser ablation. IFTLE should note that this is how it was done during the MCM era in the mid 1990’s, like the IBM SLC technology.

Princo – System on film

In yet another chips last packaging solution, Princo described their system on film technology. Following the figure below they 200mm glass wafer that is first surface treated with a PI and then a silane release coating then another PI layer. Steps 4 to 7 are a lift of copper metallization sequence (6/4um L/S ; 11um thick). Next comes a dielectric layer ad then laser formed vias. These steps are repeated for further layers (up to 8 so far). In step 14, the structure is released from the carrier. This RDL film wafer is then flipped over and the pads are opened through the PI layer and ENIG coated. Die are flip chip mounted, underfilled, overmolded and balls attached and balls placed.

They describe two modules. Module #1 consists of a µprocessor, LPDDR SDRAM / NAND flash combo memory and power management IC on a 6 layer 20 x 17mm module. The second module consists of a µprocessor and a bluetooth 4 dual mode chip packaged in a 4 layer 9.5 x 7.3mm thin film package.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.

YOLE

Advanced packaging has increased in complexity over the years, transitioning from single to multi die packaging there are several platforms now available as summarized by Beica of Yole in the following figure. When choosing a package solution, typically the most mature and established will be considered first.

When looking at flip chip ~ 37% of the cost is attributed to the substrate. The substrate also increases the thickness of the package.

Fan out packaging offers increased I/O but also a thinner package since the substrate is not required. Initially limited to eWLB licensees from Infineon (Nanium and STATSChipPAC) the market is expected to explode in the next few years as ASE, SPIL, Amkor TSMC and DECA bring fan out capacity online.

Yole’s Ivankovic compared expectations for glass/silicon interposers vs polymeric substrates. Glass interposer technology is still immature. Polymeric sub 10um L/S substrates are promising but need cost reduction and further L/S reductions. The sweet spot for silicon interposers appears to be up to ~ 3/3.

IFTLE feels that silicon interposers with coarser L/S can surely be manufactured but will not compete on a cost basis. A substrate technology gap exists between 10 and 1um. This will be where the battle for business will be fought.

ASE FOCLP

Chen of ASE escribed their new Fan out Chip Last Package (FOCLP) which they see as a low cost alternative to eWLB FOWLP solutions. Copper pillar bumped die are mass reflowed onto a low cot coreless substrate, followed by overmolding, which also serves to underfill the die. The Cu pillars allow die connection at 50um or below, negating requirement for RDL n the die. The Cu pillars are bonded to one side of the copper trace (down to 15um L/S) and solder balls are directly bonded to the other side. This makes the “substrate” be effectively as thick as the copper in the traces and allows the final package to be as thin as 400um. Implementation with multiple die, inclusion of passives and 3D structures can all be implemented.

STATSChipPAC – High Density eWLB

Currently eWLB devise are used in baseband processors, RF transceivers, power management ICs, NAND memory controllers, on 2 node and ramping on 20nm. In a number of cases STATS reports a 20-40% reduction in package size and a 50% volume reduction due to its slim form factor.

STATS presented their work on with Qualcomm defining eWLB technology with high density ( 2/2 L/S ) and multilayer RDL. Their test structure contained 3 layers of RDL with 2/2, 5/5 and 10/10um L/S.

These structures were built and passed std JEDEC reliability testing.

Nanium – Advances in eWLB

NAnium described new developments in eWLB technology. Kroehnert indicates that the first eWLB based products have been qualified for wafer level SiP and WLPoP with embedded multi die, discrete passives, already packaged components sensors and optical elements.

Nanium eWLB Placement before Overmolding

As thin 300mm reconstituted wafers are not stable enough to be handled in traditional equipment, temporary bonding of recon wafers was developed. They found significant impact from bot the temp bond adhesive and the carrier composition.

The majority of work being done is to enable higher density integration:

– finer L/S

– multilayer RDL routing

– multi die placement with smaller inter chip distances

For all the latest in 3DIC ab=n other advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

IMAPS 2015 also known as the 48^th International Symp on Microelectronics was held this past Oct in Orlando, FL. Umi Ray of Qualcomm was General Chair and Erika Folk of Northrup Grumman was Tech Chair. There were 30 sessions, > 150 presentations and > 135 exhibit booths. Certainly, in terms of microelectronic packaging, this is the largest annual exhibition in the USA. In the next few weeks we will take a look at some of the presentations that caught the eye of IFTLE…

First, let’s first take a step back to one of the best boxing movies of all time, ROCKY. In 1976, Sly Stallone (who by the way spent his early years growing up on my block in Hell’s Kitchen, NYC) wrote and starred in this rags to riches American Dream story of Rocky Balboa, an uneducated but kind-hearted boxer in the slums of Philadelphia who gets a shot at the world heavyweight champion Apollo Creed, and looses the fight. The film earned three Oscars, including Best Picture. In 2006, the film was selected for preservation by the Library of Congress as being “culturally, historically, or aesthetically significant.”

Anyone who saw the film at the time will never forget the single line that ended the movie. As the ring announcer is proclaiming Creed the winner, Rocky, with both eyes swollen shut, is shouting out “Adrian!, Adrian!“ calling for his girlfriend (Talia Shire) . It brought grown men and women to tears. [link]

Anyway after many sequels, none of which came anywhere near the quality of the original, fast forward to 2015 and the movie “Creed” where Adonis Creed, Apollo’s son asks Rocky to become his trainer after no one else will work with him. In a strange twist of fate Creeds son also ends up fighting against the champion and looses but “…though he lost the fight, Creed won the night”. For his performance, Stallone has been nominated for the Golden Globe Award for Best Supporting Actor in a Motion Picture, his first nomination since the original Rocky, 40 years ago. Certainly a comeback for Rocky!

So you ask yourselves where is IFTLE going with this? Be patient.

I want to start our look at IMAPS 2015 with the presentation by the new Yole Developpement packaging team on the technology and market trends for WLP. You may wonder why I focus on this technology which was Leading Edge literally 20 years ago. Certainly it is near and dear to my heart since many of my most exciting days in technology were shared with the WLP pioneering groups at Flip Chip Technologies (FCT) and Microelectronics Center of NC / Unitive as this initial wafer level technology was being conceived and developed with my team developing BCB. These two small startup companies certainly were underdogs, and they were using my new dielectric, also an underdog, but within 2 years we were in nearly every cell phone made in the world.

Since it’s inception by Rajen Chanchani at the Boston IMAPS conference in 1994 to the commercialization of the UltraCSP by Pete Elenius of FCT in 1998, what was at first one of many chip sized package solutions evolved into wafer level chip scale packaging and then more simply into wafer level packaging or WLP.

[for a complete history of bumping and WLP see “On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging,” A. Huffman, P. Garrou, (link)]

By the early 2000’s it became obvious that WLP had unmatched advantages in both form factor and cost and the technology was quickly licensed by all the key OSATS and OEMs worldwide and adopted in nearly all mobile phone products. 20 years ago this was the leading edge and those working in the area and finding success felt like this [link]:

“Trying hard now…It’s so hard now…Trying hard now”

“Feeling strong now…won’t be long now…getting strong now”

“gonna fly now….flying high now…gonna fly…fly… fly ! “

Yole points out that although WLP has been seemingly out of the spotlight with the advent of higher density packaging solutions such as copper pillar bump, 2.5 & 3DIC and fan out and embedded packaging, WLP remains a highly important and constant presence. The mobile market continues to be the main driver for WLP with over 90% of all fan in packages being found in handsets and tablets.

Since the WLP eliminates the need for WB, substrates, FC bumps and in most cases mold compound, it still results in the shortest interconnects, lowest parasitics, and best electrical performance in terms of speed and frequency. Bump pitch of 0.35mm are currently in high volume production with 0.3 and 0.25mm under consideration. Most fan-in die are below 7 x 7mm and below 200 I/O. In general warpage and board level reliability for larger dies remains a concern. If your die is relatively small and your I/O demands relatively low, this is the best packaging solution.

Fan-in WPL units hit 35B in 2014 with a 9% CAGR. BT + WiFi + FM combos, CMOS image sensors and Rf transceivers account for ~ 50% of all WLP applications.

Yole has identified more than 70 high volume fabless and IDM companies implementing their designs in fan-in WLP along with over 20 fan-in manufacturing companies.

What the Future Holds for WLP

In the future IoT (Internet of Things) will eventually succeed mobile phones as the microelectronic driver…the big dog. However, there have been many unjustified presentations over the last few years detailing, without any support data, how IoT will drive leading edge, high end technologies like 3DIC. IFTLE does not agree with that conclusion but rather contends that IoT will be low I/O and will demand two things – small form factor and low, low cost. As such IoT will generate a huge potential market for fan-in WLP.

Back in the mid 1990’s, WL-CSP was an underdog who proved itself and became an integral part of cell phone manufacturing and, now after being somewhat overshadowed by newer leading edge technologies for a while, is about to make a comeback due to the inherent strengths of this technology. Anyone care to bet against it?

For all the latest in 3DIC and other advanced packaging technologies, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a quick look at the 12^th annual Int. Wafer Level Packaging Conference (IWLPC) which was held in San Jose in October. But before we do, a Christmas message from my granddaughters:

IWLPC 2015

The 2015 IWLPC technical focus consisted of   1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose.

DECA

We have looked at the activity of Deca several times since their initial pronouncements in 2012 [see IFTLE 124, “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP” and IFTLE 175, “2013 IWLPC; 450mm on Hold?”]

Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay difficulties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.

In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.

After the Adaptive Patterning design files are created, fan-out processing can commence. The build-up proceeds through polymer 1, RDL, polymer 2 and UBM layers, with the lithography system implementing unique designs at the polymer 1 and RDL layers on a per panel basis. Finally, ball attach and package finishing are performed to produce singulated fan-out packages.

The board level reliability was examined for a 8mm X 8mm package with 324 IOs on a 0.4mm pitch. The packages were mounted to 1mm thick printed circuit boards (PCBs) with non-solder-mask defined PCB pads. Standard JEDEC conditions were used for temperature cycling and drop testing. First cycling failure occurred at 665 cycles and with no failures observed up to 250 drops.

SPTS – Plasma Dicing

Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conventional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.

Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.

IMEC / KLA Tencor

IMEC / KLA Tencor shared their results on investigations to determine the best way to insure µbump presence and co-planarity. µbump dimensions are being scaled down to 20 um pitch (10 µm in width and 8 µm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of µbumps at both die-level and wafer-level is a must for this technology to become a viable industrial option.

Bump co-planarity is defined as the difference between the heights of the tallest and the shortest µbump within a die as shown below.

A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mislocated bumps can lead to the wrongful classification of the die as suitable for asembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.

One of the challenges in constituting a meaningful subset for measurement is to define a population of µbumps which is large enough to be statistically significant and to select µbumps from areas in the die which will represent height range and coplanarity of the full die.

Nanium / EVG

Nanium and EVG shared some information on Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP.

In order to achieve a cost competitive position related with other packaging technologies, FOWLP has been using 300mm diameter reconstituted wafers, which brings challenges related with its mechanical and thermomechanical properties like wafer bow, wafer warpage and wafer expansion. Nowadays, more FOWLP designs require reconstituted wafers with thickness below 400um. When wafer thickness drops below 400~450um, the reconstituted wafers acquires a flexible behavior that does not allow self-supporting handling anymore.

Adding to this challenge, the need for RDL processing on both sides of the eWLB wafer, for 3D and PoP constructions, requires the temporary protection of one RDL side while the other is being built. Solutions such as temporary wafer bonding for 2.5/3DIC technology , cannot be copied-exact for eWLB wafers because of the very high and non-linear thermomechanical behavior of such wafers and to the temperature limitations the molded material imposes. For example, Si wafers failed as carriers due to the mechanical mismatch to eWLB wafers and with adhesives with bonding process temperature above 200ºC . The selection of carrier wafer and adhesive material are key elements to the success of any temporary bonding and debonding technique for eWLB or fan out in general.

Based on their studies we are not told what the preferred carrier or temp adhesive are, but we are led through several solutions and told what properties lead to the best results.

For all the latest on 3DIC and other advanced packaging options, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

IMAPS now “Googleable”

Of upmost importance to researchers at Universities, Research Institutes and even Commercial Companies is the ability of others to find their publications.

For years, a pet peeve of mine with IMAPS (the International Microelectronics and Packaging Society) is that once your work was published it was …well…lost. Mind you I was Technical VP and then President of the Society in 1997 so I’m not some complaining outsider. I have been saying this for more than 20 years. Certainly their journal and proceedings are “archival” in the technical sense of the word. Both are bound and printed and available to individuals and libraries for posterity, but many of their conferences containing key publications are only available if you know they exist and go to the IMAPS web page to download them.

In the 1990s most of the key papers on multichip modules (MCMs) were put into the conference of the same name that many of us sponsored through IMAPS. It was a great Conference, but try finding those papers now unless you have copies of all those proceedings.

Nothing has changed more in my lifetime then how we write reports and share data. In 1975, my first year in industry, we wrote report drafts on yellow legal paper and gave them to the office secretarial pool to type for us. They went back and forth a couple of times (since they couldn’t read my handwriting) and figures were added after they were drawn on a draft board.

Literature searching was done in the library where you combed through books and journals till you found what you were looking for. Once you found a key paper you went through all the references in that paper and went backwards like that till you were pretty sure you had found everything that was worthwhile.

All that changed with the computer and the internet. The computer which we got individually in our offices ~ 1985 (best I can recall) caused the unemployment of a lot of young women in the secretarial pool, but it sure increased my productivity in terms of putting a report together. Internet searching of the scientific literature came a bit slower, but by the late 1990s, or certainly by the time Google Scholar came into being in 2004, most researchers simply put their queries into the Google and up popped more references than you could read.  Everything was now available, well everything that Google searched. You can also easily see where this leads. If everyone only references things that are searchable in Google, then after a few years the only references you can find are those that are searchable by Google. Not so great for scientists publishing in non searchable sources.

The Europeans caught on to this problem first and we saw IMAPS conferences in Europe requesting co-sponsorship of IEEE so that their work would be put into IEEE Explore (yes its Google searchable).

It has taken awhile, but after a lot of bitching by myself and others and a lot of hard work by IMAPS staff everything is now searchable back to 2010. Not only the journal and the annual fall meeting but also key conferences like the Device Packaging Conference (DPC). YES – all the slides presented at the DPCs (since 2010) are now searchable and downloadable. I have tested this out myself and sure enough Google now finds them. For more details try www.imapsource.org/

Georgia Tech Interposer Conference (GIT 2015)

Finishing up our look at the GIT, lets look at Intels EMIB and the SPIL / Xilinx SLIT

EMIB

Intel is still keeping design flow and ground rules for EMIB (embedded multi die interconnect bridge) close to the vest and I did not see much new from Bob Sankman.

Certainly the EMIB eliminates a chip attach operation since there is no Si interposer, but the BGA substrate sure looks a whole lot more complex to me. It certainly is an elegant solution, but I’m not convinced it is the low cost solution till I hear from customers what these modules will really cost. It certainly is of interest that Altera has announced a Stratix 10 to be done with EMIB.

SLIT

Xilinx and SPIL were he first to announce TSV free high density interconnect more than a year ago. See IFTLE 215, “STATS Acquisition; Will SLIT replace TSV?”]

Xilinx indicates that the UMC/SPIL version of CoWoS, SSIT is ready for production.

SLIT offers

– 65nm BEOL design rules                                                                                                                                             – non TSV interconnection                                                                                                                                                    – reduced CAPEX                                                                                                                                                                              – less inspection metrology steps                                                                                                                                             – SLIT patent issued to Xilinx

Xilinx compares SLIT to other solutions below:

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The GaTech group ad many of their members have been studying the applicability of glass as 2.5D interposers for several years now. Some of the papers presented at this year’s meeting updated the industries status in this area.

LPKF Vitrion

LPKF Vitrion updated the attendees with their latest Through Glass Vias (TGV) technology status which is shown below.

Shinko

Shinko updated their 2014 presentation on the status of Glass interposer R&D and manufacturing. Shinko is looking at glass as an alternative to silicon interposers. Their proposed process flow is shown below.

An example of a fully assembled glass interposer is shown below.

Shinko points out that there are voids inside the TGVs and they are very difficult to avoid. These voids increase the via resistance ~ 8.5%. They are in the process of determining what the acceptable void content is.

They are capable of 2um L/S RDL on the glass. They are in the process of reliability studies and failure analyses.

They are currently examining 250mm sq panels which increase unit production 2.7X vs 200mm wafers.

Unimicron

DC Hu from Unimicron shared their perspective on glass technology readiness. Hu lists the following requirements for glass mass production readiness:

Based on 510 x 510mm panels and 2/2 L/S fine line capability

– glass process readiness

• Thin glass handling
• Via forming technology
• Via filling technology

– production equipment readiness

– reliability

He compared TGV formation from Via Mechanics, LPKF, Corning, Schott and Asahi Glass and via filling by seed and plate vs screen printed paste technologies. The paste technologies appear capable of 20um vis on 50um pitch.

While plating can be done on a 500mm sq panel, fine line patterning (2um L/S) requires a large panel stepper.

Technology status vs silicon is shown below.

TDK

TDK discussed what they claim is the first glass based Rf modules. Rf integration is clearly the key enabler for next gen smartphones. Key technologies for Rf modules are shown below.

The glass Rf module concept, which is being developed with GaTech, is shown below.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…