By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 SEMICON Taiwan. This week, let’s look at some interesting presentations on fan-out packaging.

Amkor – Fan Out Solutions for Today and Tomorrow

Ron Huemoeller of Amkor addressed the status and future of fan out solutions. Amkor expects 2B fan out packages to be shipped this year.

Traditional WLFO applications and drivers are shown below.

Huemoeller reports that advanced Fan Out offers the following value proposition:

– reduced Z height and form factor           – enhanced signal integrity

– superior impedance matching                 – optimized power distribution

– improved thermal performance/junction temp

– ability to address multi die heterogeneous integration (i.e. SiP)

Traditional fan-out is reportedly gaining momentum in mobile market, i.e. RFIC, CODEC and PMIC

The table below shows their assessment of Amkor Advanced fan-out (SWIFT) vs FC CSP solutions.

 

They see advanced FO (i.e SWIFT and TSMC’s InFO) being used in mobile applications such as

– Apps processor               – Baseband (logic + memory)

– power management     – display driver SiPs

Right now they claim that traditional fan out has cost parity with FC CSP at 0.5mm die size.

K&S – Equipment Selection for Fan-Out Process Flows

Strothmann of K&S detailed considerations to make when determining equipment for fan-out process flows.

• Past and current FOWLP is typically the Infineon eWLB variety but also can be Motorola RCP or Deca versions.

– Lower I/O count devices

– Mostly single die, some multi-die and a few die with passives

– applications include Baseband, Power Management, RF, Analog, Bluetooth

• High Density FOWLP is expanding rapidly

– Competing technologies in an unsettled market space

– High density I/O capable

– Application Processors, Memory, Multi-die Si Partitioning, Heterogeneous Integration

• Wafer vs Panel formats are also being examined

Strothmann notes the following FOWLP process flows in HVM today:

• Face Down, Die First: Typical Infineon licensed eWLB process, highest volume
• Face Up, Die First: Similar to flow used by TSMC and others, HVM potential
• Face Down, Die Last: Similar to Amkor’s SWIFT or SLIM process
• Accuracy and UPH are Key Metrics for equipment selection in all flows

• Face down typically has the highest position shift but also has the highest UPH (lowest cost)
• Face up die placement accuracy can be improved with application of heat and force to lock die position
• RDL first allows for high accuracy due to metallurgy and die position being locked prior to reconstitution

FOWLP manufacturing today is primarily driven by a round 300mm format.

Panel format requires new processes and equipment to be developed

– Panel size has not been set as an industry standard

– Maximum panel size appears to be 650x650mm but many potential smaller sizes

– Difficult for equipment suppliers to prepare

– Immediate TAM is quite low due to die volume per panel

• Panel lines require significant loading for full utilization
• Larger package size is required to drive panel volume (SiP, IoT?)
• Adoption of mainstream panel processing remains a few years out

Strothmann suggests the following equipment selection criteria by process flow:

Yamada – Wafer Molding for Fan-out Packages

Katsuyama-san of Yamada discussed wafer molding systems for fan-out packaging. Yamada has been around since 1953 working on standard lead frame packaging.

Their fan-out assembly process flow giving 5 sided protection is shown below. This is achieved by cutting grooves into the wafer isolating the components and backfilling them with molding compound as shown below:

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at Advanced Packaging in SEMICON Taiwan 2016.

AMKOR – Lasers for the Manufacture of WLCSP

WL Huang of Amkor examined the use of lasers in the manufacture of WLCSP (fan-in WLP). As we all know by now Huang pointed to size, weight, cost and performance as the drivers for WLCSP.

In the following chart, Huang shows that the same 7.6 x 7.6mm chip with 28 I/O saves a lot of real estate when packaged in a WLCSP and that the bulk of such fan in WLP are projected to be for analog and mixed signal devices.

The main applications for laser in WLP are:

Laser marking

• Scribe product info on die backside for traceability

–Laser dicing

• Separate product from wafer form to die form

–Advanced process node low-k wafer (90 nm and below). Delamination can be easy observed by blade saw due to low-k material being more brittle

–Saw street design issues – reduce topside chipping and peeling

–Saw street width shrink – By shrinking saw street width, gross die per wafer would be increased which can reduce unit cost, ex. RF switch, LNA products

Two kinds of laser cut can support saw street width down to 20 μm: Stealth dicing (SD) and full laser cut.

The stealth dicing process is shown below:

The key to full laser cutting is minimizing the HAZ (heat affected zone).

ITRI – Emerging Trends & Apps for IoT

Ray Yang of ITRI examined the “Emerging Trends and Applications of IoT in the Post Smart Phone Era”. This presentation started with two interesting slides depicting Taiwan’s electronics revenue.

2014 Semi industry ranked first in value-added among Taiwan’s manufacturing sectors. The foundry business contributes the most to the Taiwan IC industry as shown in the breakout below.

Taiwan IC packaging and test accounts for more than half of worldwide assembly and test revenues.

When examining the future of autonomous vehicles he broke out the requirements into the 3 functions: sensing, understanding and action as shown below.

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Micross Components Acquires RTI Int. Fab and Packaging Group

Micross Components of Orlando, FLA announced the acquisition of RTI International’s Microsystem Integration and Packaging group and fab in Research Triangle Park, NC. Some of you may recall this RTI site as The Microelectronics Center of NC (MCNC) in the late 19080s through early 2000’s.

Micross is a provider of bare die and wafers, custom packaging and assembly, component modification services, electrical and environmental testing to manufacturers and users of semiconductor devices. The 35 year old company serves the Defense, Space, Medical, Industrial, and Fabless Semiconductor markets.

This acquisition brings the RTI wafer bumping, 2.5D/3D packaging and interconnects technologies to the hi-reliability electronics platform of Micross. Micross plan is to expand its capabilities to serve customers in the defense and medical electronics sectors with these newly acquired advanced packaging technologies.

The Micross “Advanced Interconnect Technology” ( AIT )” team will be led by VP Dr. John Lannon , Director of Operations Rex Anderson and Director of Engineering Alan Huffman.

The financial details of the acquisition were not revealed.

Teledyne Details Heterogeneous Integration using Ziptronix DBI

In IFTLE 303, we indicated that Sony was using the Ziptronix DBI process in their image sensors for the Samsung Galaxy S7 [link]

We have recently discovered that Teledyne, under the DARPA DAHI program, has demonstrated 3D integration of high- performance compound semiconductor devices and Si CMOS using similar technology. Teledyne’s Miguel Urteaga indicates that “… Adding the complexity and integration density of CMOS to Teledyne’s ultra-high speed Indium Phosphide bipolar transistor process enables new classes of mm-wave and sub-mm-wave electronics for future DoD and commercial applications” A cross-section is shown below.

SEMICON Taiwan

Over the next few weeks we will review some of the highlights of the recent Semicon Taiwan Conference. This week we will look at the “market trends” forum moderated by Elizabeth Sun of TSMC.

Handel Jones – Int Business Strategies 

IBS projects the Semiconductor market to decline in 2016. He market broken out by product type is shown below:

 

IBS projects that 3D NAND flash will overtake 2D NAND Flash in 2018. 64 layers should be in volume production in 2017. Samsung appears 12-18 mo ahead of its competition.

 

Wafer fab activity in China shows a strong emphasis on memory as shown below. However Chinese DRAM vendors are not expected to have a large impact on supply before 2020.

Dan Tracy – SEMI Equipment & Materials Outlook

Of the 21 fabs beginning construction, 11 will be in China.

200mm capacity is expanding with 8% growth expected between 2015 and 2019.

The wafer materials forecast is shown below:

The packaging materials forecast is shown below. “Other” includes solder balls and WLP dielectrics.

A key factor here is that laminate based substrates will begin to feel the pressure of FOWLP packaging as they take market share.  

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Qualcomm Negotiating to Acquire NXP

Long time readers know that IFTLE has been following the consolidation in our industry for more than 8 years now based on the basic laws of economics telling us this was going to happen. [see IFTLE 241 “Simply Obeying the Laws of Economics”]

Reports from multiple financial sources indicate that NXP Semiconductors has hired an investment bank to help them deal with recent acquisition offers. Qualcomm is viewed as the likely acquirer. According to the Wall Street Journal (WSJ) the deal would be worth over $30B. [link]

Qualcomm and NXP both supply Apple. Qualcomm apparently has its eye on NXP’s position in the automotive supplier business based on its Freescale takeover in 2015. The automotive chip business will reportedly show above average future growth.

 

Bloomberg reports that others who could possibly jump in with bids includes Broadcom, Intel and Samsung [link].

According to the WSJ, the deal would reshape Qualcomm. While Qualcomm currently derives most of its revenue from designing and selling chips, the company earns more than half of its profits from licensing its wireless patents to nearly all makers of mobile phones.

HBM IP at Open Silicon

TSMC’s Open Innovation Platform (OIP) Forum was held Sept. 22nd at the Santa Clara Convention Center.

A recent discussion on Semiwiki [link] by Tom Simon indicated that Open Silicon discussed their IP for HBM memory stacks on 2.5D interposers at the meeting.

This topic is discussed in detail on the Open Silicon web page [link].

Open-Silicon’s subsystem IP solution comprises the HBM Controller, PHY and 2.5D interposer IO addressing interoperability and 2.5D design, test and SiP packaging challenges. The HBM IP claims to be suitable for graphics, high-performance computing, high-end networking and communication applications that require low power and small form factor.

Open-Silicon claims their HBM IP is the industry’s first solution for integrating HBM into ASICs for high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. The Open-Silicon HBM IP fully complies with the HBM-Gen2 (2 Gbps per signal) JEDEC standard.

Back to the OIP presentation, Simon reports that Open-Silicon has implemented an HBM reference design in 16nm. According to Open Silicon 16 nm FinFET is the key to unlocking the full benefits of HBM since it can potentially reduce power and boost performance by 50% relative to 28 nm.

In the current design Open Silicon replaced (24) DDR3 1600 with 1 HBM stack, the power consumption went from 1.0 mW /Gbit to 0.33 mW. The data rate climbed from 4 GB/s up to 256 GB/s.

To effectively shield the 0.85 um signal lines from cross talk, ground wires of 0.5um were placed 2.1um to the side of each signal wire. This left 2.1 um for each signal line.

IEEE 3DIC Conference

 

 

The IEEE 3DIC conference, which I helped put together several years ago, is back in SF this year and will be held Nov 9 – 11^th. [link]

Topics will include:

– 3DIC Processing                            – Design and Applications

– Thermal Analysis                           – Bonding

– Reliability and Stress                  – Power & Signal Integrity

– CAD

Next week we will start our coverage of SEMICON Taiwan packaging activities. For all the latest in Advanced Packaging, stay linked to IFTLE…