By Dr. Phil Garrou, Contributing Editor

IBM to share technology with China

In IFTLE 222, we discussed the recent announcement by China that they are becoming a major predator of the IC business. This is exemplified by recent acquisitions of STATSChipPAC (see IFTLE 222)(link),  FlipChip Int (FCI) (link) and Omnivision.

Now, according to Reuters, IBM Corp has announced that they will share technology with Chinese firms and will actively help build China’s industry. “IBM’s new approach allows Chinese companies to build everything from semiconductor chips and servers based on IBM architecture, to the software that runs on those machines”.

Apple A9 Orders Shift to TSMC

EE Times reports that TSMC will take more orders for Apple’s A9 processor (for the iPhone 6S) at the expense of Samsung, which reportedly is having yield problems. Apple originally gave Samsung about 80% of the A9 orders and the rest to TSMC. Now reports are that TSMC will get about 70% of Apple’s overall business starting in the third quarter of 2015 (see previous discussions in IFTLE 228).

There are reports that TSMC’s 16nm yield is better than Samsung’s 14nm yield (both using finfet technology).

This will be the first time that Apple has split the foundry service of the same processor at two suppliers. Equipment and materials will likely see rush orders from TSMC to meet demand. TSMC will also need to work more closely with OSATS such as ASE and SPIL for the full solution.

Because of the reported overheating issue in Qualcomm’s 20nm Snapdragon being made at TSMC,  Qualcomm is reportedly cutting its 20nm orders at TSMC and is accelerating its transition to 14/16nm at Samsung. Since Qualcomm accounts for 40% to 50% of TSMC’s 20nm demand, this will have a significant impact on TSMC revenue.

This has also caused issues at Sony who recently reported overheating Issues were stalling release of Sony’s Xperia Z4 smartphone (link).

“The Xperia Z4 is expected to be an extremely thin smartphone; thus the need for successful heat dissipation is important. The Xperia Z4 tablet is also powered by the Snapdragon 810; however, there is more surface area for heat dissipation on this 10-inch tablet than the small smartphone”.

Fujitsu Puts Liquid Cooling in Smartphones

Many manufacturers struggle with removal of heat from chips in phones and tablets. Unless that heat is removed, hotspots can form when devices are in use, causing thermal damage.

Engineers at Fujitsu have now developed a liquid cooling solution for smartphone devices (link).

Fujitsu has built a microscale heat pipe, less than 1mm thick. It’s comprised of two parts — the first is an evaporator that absorbs heat from a heat source and the second is a condenser that dissipates the heat away, with the two parts connected by pipes.

 

Capillary action to drive flow. Inside Fujitsu’s device, the tubes are filled with pores that are just the right size to get fluid to circulate. Fujitsu reports that “Compared to the previous thin heat pipes and material of highly thermal conductive sheets, this new device allows for approximately five times greater heat transfer,” The technology allows CPUs and other parts to function at low temperatures while preventing heat concentration within localized areas. Fujitsu reports the technology should make its way into smartphones around 2017. Fujitsu adds that it’s also looking into potential applications in communications infrastructure, medical equipment, and wearable devices.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The IMAPS Device Packaging Conference in Ft McDowell, AZ is an annual meeting where we have grown to expect major new technical introductions from the OSAT and materials community. This year’s meeting was no exception with key new package introductions from Amkor and ASE. This week we’ll look at the ASE FOCLP (fan out chips last package) and next week we’ll take a look at the new offerings from Amkor.

ASE FOCLP

We’re all aware that miniaturization has driven our industry  for decades until we finally reached the WLCSP (wafer level chip size package) where the size of the package became the size of the chip. At this point we all looked at the vertical dimension and became focused on stacking chips (to gain x,y area) or thinning chips and package to produce thinner lap tops and or  cell phones.

John Hunt offered this interesting slide showing the thinning of the Apple I phone plotted against the increase in use of WLPs.

 

As chips have been shrunk to the 22nm node and beyond there is not a lot of room under the chips for I/O, thus the focus on fan out WLP (FOWLP).  ASE addressed the question, “How do we reduce the cost structure in fan out packaging ?”

By moving to a totally laminate based solution they have been able to combine coreless laminate substrate, copper pillar bumping and molded underfill to produce a low cost ultra thin ( < 375um) package.

 

• Chip Last vs Chip First for Higher Assembly yields
• Fine Pitch bumping direct on die pad without RDL
• Thicker Copper (15-50µm)allows higher current
• Thin Package < 375µm

The single layer coreless substrate utilizes embedded traces and pads for fine feature resolution.

 

Fabrication is done on a 510mm x 410mm panel which is assembled in strip form similar to what is done for BGAs. No fan out wafer fab investment is required.

 

FOCLP can be identical in size, thickness, foot print, trace layout and performance as FOWLP while using only lower cost  laminate packaging technologies. Electrical Simulation shows comparable performance.

 

Multiple actives and passives can easily be included in FOCLPs using existing volume production equipment. Thermal Heat spreaders can be included in molded FOCLPs. Thick Copper can be used for high current and/or thermal transfer. Standard packages such as SiP and PoP will be transferrable to WLCLP.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the Semi 3D Summit in Grenoble we’ll look at the presentations of Besi, IMEC, AMS, Asahi Glass and Yole.

BESI – 3D Stacking with Thermocompression Bonding (TCB)

Hugo Pristauz of Besi updated the attendees on the advances in 3D Stacking with thermocompression bonding (TCB).

Thermocompression bonding which requires both heat and pressure is contrasted to mass reflow bonding (also simply called solder reflow) where no pressure as to be exerted. The latter is a high productivity process whereas the former is known for slower throughput.  It is usually accepted that TCB is required at pitches less than 40um.

TCB may be done with capillary underfill or more recently with NCP (substrate side) or NCF (chip side) as shown below.

 

Besi indicates that TCB is being used for Micron HMC production.

IMEC – 3D Technology Depends on Application

Eric Beyne of IMEC examined mapping 3D technology to 3D applications.

For instance,

–        Logic + wide I/O density: high interconnect density

–        Mixed signal/MEMS : lower interconnect density

Interconnect technology options include:

 

A high bandwidth interconnect bus requires a ref/shielding plane for signal integrity and reduced cross-talk which would mean:

 

Choices will depend on the interconnect density that is needed.

[added note from IFTLE] All interposer products announced thus far are still requiring the high density dual damascene interconnects.

AMS AG – Sensors for Smart Systems

Martin Schrems of AMS AG reported on “3D Sensor Integration for Smart Systems”. Certainly we would all agree that sensors are a major part of what will make smart systems smart. AMS offers the following as a standard block diagram for a smart system:

 

For instance, indoor air quality sensors measures standard  temperature, humidity and carbon dioxide (CO2) levels as well as the amount of volatile organic compounds (VOCs), such as smoke, cooking odors, bio-effluence (body odor), outdoor pollutants or human activities. While temperature and humidity are easy to measure, sensors for measuring CO2 (IR absorption) can be expensive.  VOC detection uses micromachined metal oxide semiconductor (MOS) technology to detect a broad range of VOCs while correlating directly with CO2 levels in the room.

 

The motivation to move to 2.5D packaging is the size reduction advantages.  At this point these systems are still at the R&D conceptual stage.

Asahi Glass – Update on glass for 2.5D Interposers

Asahi Glass is one of the glass producers putting their money where their mouth is in terms of funding R&D and development into the use of glass as a 2.5D interposer material. We have discussed in length their investment into Triton, a start-up looking at manufacturing  commercial glass interposers [ see IFTLE 141 “IFTLE 141 100GB Wide IO memory; AGC Glass Interposers; Nvidia talks stacked memory”]

At the 3D Summit in Grenoble Shin Takahashi of Asahi Glass reviewed the status and challenges of glass interposer activity. Below we can see their listed technical and manufacturing challenges.

 

With thin silicon (100um) they are now able to create 25-30um tapered TGV (through glass vias) on a 50um pitch.

 

For via filling, they are looking at both conformal copper plating and copper paste filling where their capabilities are currently 50um dia. on 130um pitch.

Reports on panel based processing, which is viewed as the primary means of lowering the cost structure on interposers, is seen as lacking infrastructure.

Yole Developpement – Wafer Level continues market penetration

During her overview of the industries packaging efforts, Rozalia Beica of Yole indicated that wafer level processing will this year account for 20% of all semiconductor IC wafers.

 

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at presentations from the Grenoble SEMI 3D Summit which took place in January lets look at an interesting presentation by ATREG consultants on the future of Assembly & Test.

ATREG – The Future of Assembly & Test

Barnett Silver from ATREG Inc. discussed their thoughts on “The Future of Assembly and Test…” They base their predictions on the following themes which are in alignment with what you all have been reading in IFTLE for the past 230 blogs.

• Packaging and test is an enormously important component of semiconductor manufacturing.
• Technology and economics are driving convergence / consolidation between front-end and back-end manufacturing.
• Prior concepts inhibiting front-end / back-end convergence / consolidation are fading
• In the future the packaging landscape will look different from today.

They proposed the following sequence time line for the evolution of the packaging and test industry  : stage 1 – fully vertically integrated companies did their own chip design, manufacture, test and packaging; stage 2 – back end packaging and test began to separate into assembly companies ; stage 3 – foundries and fabless companies created a period of specialization and separation of tasks; stage 4 –(which ATREG indicates starts around 2010) they see  re-integration.

IFTLE sees it slightly differently with convergence of package and test skills into the foundries but not a reintegration for fabless or IDMs.

 

Of the total industry COGS of $205 billion, ~25% (or $51 billion) is spent on assembly & test.

 

Five firms dominate outsourced packaging, accounting for over half of the total OSAT industry and 25% of the total back-end spend of $51B.

 

It has normally been assumed that since foundry margins are significantly higher than OSAT margins, traditional OSAT business would be unattractive to foundries. With a few exceptions, foundry / OSAT acquisitions would be dilutive to foundry’s gross margins yet foundries show interest in aspects of A&T.

 

This perceived dichotomy can be understood by looking at the difference between packaging margin on standard chips vs advanced chips. In fact, over the last five years, OSAT firms have delivered better returns for investors than foundries partially because assembly houses spend far less per year on capex than foundries [ i.e. 18% vss35% in 2013].

As prostheliytized by IFTLE,  the economics of the latest node chip fabs are limiting those who can move forward with such expendatrures, and products are being customized  by the packaging that is being chosen. It is quite likely that this will be  where margin will come from in the future. 

Customers will be choosing between a turnkey model controlled by the foundry (proposed by TSMC) or a collaborative model where the foundry and the OSAT remain as separate entities (proposed by GlobalFoundries).

 

Among other things ATREG concludes that:

• Foundries, OSATs, and IDMs will fight over the $51 billion A&T market.

–        IFTLE agrees that foundries will battle with OSSATS but is not yet convinced that IDM are getting back into the fray.

• As technology drivers change, there will be significantly more focus on the back-end industry.

–        IFTLE absolutely agrees.

• There will be re-integration and convergence between front-end and back-end.

–        IFTLE agrees through both convergence (which some now call “mid end”) and consolidation.

•Disruption in the OSAT industry will increase.

–        IFTLE agrees again through convergence and consolidation.

• IDMs / fabless may invest in advanced packaging

–        IFTLE is not convinced.

In conclusion, although IFTLE agrees with ATREG on most point (and has been documenting these facts for many years) we are not convinced that IDMs and the fabless are looking to get back into the packaging business.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…