Current FO-WLP practitioners include licensees of the Infineon e-WLB [embedded wafer level BGA] including ST Micro, ASE, STATSChipPAC and Nanium (Qimonda Portugal) and Nepes which has licensed the Freescale RCP [redistributed chip package] technology which is similar.. Amkor and others are known to have similar products in development.


The 2010 marketplace for FO-WLP, as determined by Yole Development, is shown below.

Their technology will first be used in microcontroller (MCU) products, which require small chip size and high interconnect density. Their listed specs include: interconnect density (L/S = 15/10 μm, interlayer via pitch = 50 μm); chip size (5 mm �? 5 mm or less) and thickness (0.3 mm) package.

The process flow involves following steps: (1) Photo PI is deposited on a Si support wafer and the patterned; (2) Cu RDL is deposited and patterned using a semiadditive process; ( design rules for Cu wiring were 15 μm in width, 10 μm in space, and 5 μm in thickness); (3) Cu pillar bumps (CPB) with Sn-Ag solder caps were formed at relevant positions on the top Cu wirings; (4) IC chips were separately prepared with electroless Ni/Pd/Au plating on I/O pads; (5) chips attached by die-to-wafer bonding; (6) MUF (molded underfill) of the chip-bonded RDLs on the support wafer; (7) The Si support wafer was removed from the chip-bonded RDLs to form a chip-embedded resin wafer with RDLs; (8) The wafer was diced and separated into an individual packages (Before dicing, additional metallization for external terminals such as Au plating, solder ball mounting, or solder paste printing occurs).

For all the latest in 3D IC integration and advanced packaging stay linked to Insights from the Leading Edgeâ??¦.

Remembering VLSI Japan


VLSI Japan was an outstanding technical conference which promoted the sharing of information and ideas through the 1990’s and 2000’s. My own memories bring me back to the 2000 VLSI meeting that George Harman, Len Schaper, Jan Vardaman and I attended from the US.

There were several interesting and informative 3D related papers presented at the IEEE CPMT Japan Symp this year that are worth reviewing.


Toray


3D stacks are usually joined by metallic bonding using techniques such as solder or Pb free solder bumps, Cu/Sn eutectic or Cu/Cu thermo compression bonding. Non conductive underfill can be used to fill in the space in and around the interconnections to mechanically support the interconnect. It is difficult to flow traditional underfill materials into such narrow gaps and to control material flowing out from the chip edges.


Pre applied non conductive filler (NCF) doesn’t need to flow into the small gaps or flow out over the chip edges. Lamination on structured surfaces demands a fluid nature for the NCF while a rigid material is required for dicing. This combination of properties can be obtained from materials that have temperature dependant viscosity. Such NCFs can flow into the narrow spaces between bumps and be cut with a standard dicing saw.


Pre applied NCF must be transparent, to allow viewing of alignment marks, and must not remain between the bump and the pad during bonding. Toray developed a transparent, low CTE underfill by using nm sized filler particles as shown in the figure below.

To insure that the bump / pad area is clean during bonding, the chip with NCF should be heated up to the temp where the NCF changes to a flowable liquid and then pressed into contact with the pad on the other chip in the bonder.


As an alternative solution Toray has also developed a negative tone photo NCF to insure the contact areas are free of underfill material during joining. The material flows at ~ 200 C and has a 1% wt loss temp of 300 C.


Hitachi Chemical


When filling TSV with Cu, the overburden is usually removed using CMP. The Cu thickness and topography requires a optimized Cu CMP process for removing the thick Cu layers. Hitachi studied friction force requirements and chemical additives for various slurries in order to develop a high speed removal process specifically for 3D processing. The table below shows both the target values and the ultimate product (HS-C935) performance.

ASET

We have discussed Japan’s ASET consortium several times in the past [ see PFTLE 104, “3D From the Land of the Rising Sun”] For the Dream Chip program Renesas and Rohm are studying thinning and pick-and-place technology for die to wafer constructions. Their specification is to achieve 10 +/- 1 µm wafer thickness stability after thinning and dicing 300 mm wafer devices.


Thinning to 10 µm requires a hard support (carrier) and an adhesive that would both be uniform and is thermally stable enough to resist degredation during grinding and backside processing.

To achieve the 10 +/- 1 µm 300 mm wafer thickness,variation must be controlled in the Si wafer, the adhesive and the carrier as shown below.

Epoxy adhesive with a reported thermal stabilty of 200 – 230 C was examined. After thining to 10 µm no edge chipping or cracking was observed, but swelling of the adhesive and resultant cracking of the thin Si is seen when the adhesive is baked for an hour at 230 C so in reality the material for this application is really only stable to 200 C.

Pick and place of these thinned chips is also a significant technical issue. They evaluated the slide-and-peel method shown below.

When the chip overhang is small the adjoining chip is damaged during the pick operation. When the overhang is to large the lower vacuum attach area becomes too large and he chip cannot be picked up. Conditions were found where the chips could be picked up by the vacuum collet.

Although it will require significant engineering, it appears that there are no insurmountable challenges when it comes to thinning and pick up. It will be very interesting to see the details on the stacking step !

MEPTEC Roadmaps Meeting

MEPTEC will be having a “ Semiconductor Packaging Roadmaps: Applications Driving Requirements” symposium on November 10 at the Biltmore Hotel in Santa Clara,CA. You can find out more about this meeting at their web page.

It will include:

Session 1: Semiconductor Industry Roadmaps: Carving out the Decade Ahead Session Chair: Rich Rice, ASE (US)

Session 2: Panel Discussion — SATS Technology Development: Merging Internal and Customer Roadmaps Panel Moderator: Joel Camarda, National Semiconductor

Session 3: System-Level Implications on IC Package Design Session Chair:Gary Catlin, Plexus

Session 4: Packaging Roadmaps for Emerging Applications Session Chair: Jeff Demmin, Tessera

For all the latest information on 3D IC and advanced packaging technology stay linked to Insights From the Leading Edgeâ??¦â??¦..



Initial WLP products manufactured under the FCT UltraCSP license (i.e Amkor, ASE, SPIL, STATSChipPAC, National, etc. )used BCB dielectric, Ti/Al/Ti RDL and Al/NiV/Cu UBM. Larger chips and more difficult reliability requirements have seen a shift to PI and PBO type dielectrics which have higher elongation and are considered “tougher”, a shift to Cu RDL and a shift away from sputtered Al/NiV/Cu UBM.


At the recent IEEE ESTC (Electronic System-integration Technology Conference) in Munich, John Hunt of ASE detailed dielectric, RDL and UBM change options for their WLP technology.

Hunt concludes that in both the temp cycling and drop test results, cell 8 shows the highest first fail and Weibul 63.2% cycle to failure data. Cell 5 would rank 2nd. Overall both cells have 7.5 um of dielectric in both the first and second RDL layers . Cell 5 uses PI and performs slightly better in the temp cycle tests and cell 8 which uses PBO performs better in the drop test.


All cells with 5 um dielectric performed poorly. Al/NiV/Cu sputtered UBM performed poorly. PBO 2 (lower cure temp – 250 C) performed better in TCT than in drop test. Higher elongation, lower modulus PBO 1 gives better drop test results.

For all the latest information on 3D IC and advanced packaging stay linked to Insights from the leading edge, IFTLE……

Siliconware
In the past, SPIL has been rather silent about their plans for 3D IC. During his presentation at the 3D Forum, Carl Chen, VP of R and D, remarked that TSV solutions will be used short term for form factor driven reasons , mid term by performance and long term for cost considerations. This sequence is dramatically similar to the acceptance of wafer level packages (WLP) in the last decade.
SPILs roadmap shows single chip logic on interposer use in late 2010, memory stacking and logic and memory on interposer in 2011 and heterogeneous stacking post 2012. Chen commented that their 3D technology will “turn on in the very near future, depending on some technological breakthroughs and cost level”
Siliconware is calling their 2.5D interposer “TSI” for through silicon interposer. They offer the following chip-to-chip (interposer) and chip-to-wafer (interposer) sequences.

The current status of their copper pillar joining technology is shown in the figure below.

Nokia has been using MEMS microphones and camera modules both fabricated with TSV since 2006 and 2007 respectively.
Kauppi Kujala, Sr Tecnology Mgr at Nokia reports that memory stacking with TSV can offer miniaturization opportunities, performance improvements and power reduction.

Kujala sees Interposers (2.5D) being driven by die /substrate pitch miss match and low  K mechanical fragility. Kujala, however warns that cost will be a major item in the adoption of interposers for 3D.
Nokia sees the need for standardization in areas like chip interfaces. Nokia is very supportive of JEDEC wide I/O standardization which reportedly will be ready in late 2011.

Yole Developpment

JC Eloy, CEO of Yole released their newest roadmap showing timing including initial qualification and first product on the market.

Qualcomm

Fabless Qualcomm has been a strong proponent for 3D IC over the past few. At Semicon Taiwan 2010 Nick Yu, VP of Engineering indicated that Qualcomm would like to see 3D HVM with 3D IC by 2013.


Qualcom is also a strong proponent of standardization in order to accelerate adoption of the technology. Qualcomm is suggesting specific standards in the following areas and suggested which standards bodies (JEDEC, Sematech, Semi, IEEE, Si2, ANSI) should be involved.


Design
– layout compatibility – data base compatibility
– modeling compatibility
Materials
– materials compatibility
QA
– incoming spec
Process Flow
– handling spec
Test


Qualcomm is looking for active industry professionals to contribute to these standards development programs and suggests the following venues:


3D design will be a focus area at the following 2010 events:
– Sematech 3D Stress Workshop : 19 Oct 2010, Dresden, Germany
– IEEE 3D-TEST Workshop: Nov 4, 2010, Austin, USA
– IEEE International 3D SIC Conference: 16 Nov, 2010, Munich, Germany
3D manufacturing will be a focus at the following 2010 events:
– IEEE International 3D SIC Conference: 16 Nov, 2010, Munich, Germany
– 7th RTI 3D ASIP Conf: 8 Dec, 2010, San Francisco, USA


For all the latest on 3D integration and advanced packaging stay linked to IFTLEâ??¦â??¦..

The Semicon Taiwan 3D Technology Forum was chaired by Ho-Ming Tong, General Manager and CTO for ASE. Speakers included representatives from Yole, Nokia, Qualcomm, UMC, SIliconware, Verigy, Applied, ITRI, IME and Sematech. The next two blogs will cover significant material from this meeting.

ASE

Dr. Tong, who some say coined the term "2.5D" for the use of silicon or glass interposers with TSV, indicated that this technology “..is ready to move to the next stage” Tong expects commercialization of 2.5D chip technology to take place in two years.

Tong notes that 2.5D IC should not be regarded as a transitional integration technology. 2.5D will enable packaging of chips in the 32-22 nm nodes where the fragile mechanical stability of the low-K dielectrics used in these products will require their bonding to an intermediate silicon interposer before final placement in a standard package.

Tong believes that commercialized products made using 2.5D IC and 3D IC technologies, including smartphones and computing applications, will hit the market in the next five years. This last comment made headlines at several news outlets [ link], which Quoted Dr. Tong as saying “ Despite tremendous progress in recent years, 3D IC with through silicon vias (TSVs) still presents significant challenges in cost, design, manufacturing, test and supply chain readiness and the technology is still three to five years away from mass production”.

After checking with Dr. Tongs colleagues in ASE I have been assured that these comments were meant to indicate that widespread use in products is still 3-5 years out but that ASE stands by the recent roadmap they shared at Semicon West this summer [ see IFTLE 9 “3D In and Around the Moscone Part 1” ] which indicates that 2.5 D readiness is imminent and full 3D for wide IO DRAM / logic bonding would be coming in the 2011 timeframe.

UMC

Shan-Chieh Chien, VP of ATD at UMC called 3D stacking with TSV the “big elephant” technology for foundries. UMC, which recently announced an alliance with Elpida and Powertech [ see IFTLE 8 “3D Infrastructure Announcements and Rumors” ] commented that logic + wide IO DRAM stacking will occur in 2011-2012 consistent with the comments of his other Asian colleagues. UMC also sees a significant future for silicon interposers indicating that UMC will use their Cu dual damascene BEOL process for passive device and fine pitch RDL on these interposers.

We’ll finish up looking at the 2010 Semicon Taiwan 3D Forum next week

the CMOS Image Sensor Market

A new IC Insights image sensor market report forecast that CMOS image sensors sales will rise 34% in 2010 to $5.2 billion from ~ $3.9 billion in 2009. Between 2009 and 2014, CMOS image sensor sales are projected to increase at a 17% compound average growth rate (CAGR), reaching $8.3 billion by 2014. CMOS image sensors dominate portable systems applications, such as camera phones, webcams in notebook computers, and other embedded cameras in handheld products, but higher-speed CMOS imagers are also being aimed at automotive systems, medical equipment, and wireless video security networks.