By Dr. Phil Garrou, Contributing Editor

In the next two weeks, we’ll take a look at some of the more interesting presentations from the SEMI 3DIC Summit in Grenoble last month.

Oerlikon – Capabilities of Highly Ionized Sputtering (HIS)

Juergen Weichart of Oerlikon Systems discussed the capabilities of highly ionized sputtering.

It has been known for many years that filling of high AR TSV required ionized plasmas as shown below.

 

Cross sectional analysis shows that HIS which deposits 462um of Ti adhesion/barrier layer on the Si top surface and 17um in the bottom of the TSV only results in a 10-12nm coating on the TSV sidewalls.

 

Deposition rates, step coverage deposit resistivity and stress for both TSV and RDL processes are compared in the table below.

 

ST Micro – Interposers for Networking ASICS

Georg Kimmich of ST Micro gave a presentation on Network packaging trends.

Below we see the current typical packaging for a networking ASIC chip

 

Higher I/O density and memory bandwidth, required for future Networking ASIC chips, can be handled by use of 2.5D packaging with high density interposers. Both Hynix high bandwidth memory (HBM) and Micron Hybrid  memory cube (HMC) memories are suitable for such networking applications.

Memory can be inserted into the packages with the following silicon and laminate interposer options.

 

While the Hybrid Organic Substrate solutions (2.1D) are the most promising in terms of cost and supply chain simplicity technologically they are less advanced.

They conclude that the very high cost of ASIC, HBM and high density interposers results in very high pressure to achieve high assembly yield. The supply chain for HBM integration are ready for prototyping now and volume production in the H2 2016 time frame.

Qualcomm – Partitioning of Large Die

Mustafa Badaroglu of Qualcomm addressed the topic of “2.5 and 3D Integration: Where we have been, where we are now and where we need to go with much the same presentation that Riko Radojcic gave at the Ga Tech Interposer Workshop in November.

They conclude that large dies can be economically partitioned into smaller dies and repackaged with several options including (1) low cost SI interposer with no substrate, (2) fan out WLP or (high density organic interposer as shown below.

 

• Split die requirement: 2um L/S between die

Required to support ~ 2000D2D connections

• PoP memory requirement: PoP via + RDL

Required to leverage standard PoP package

• Si form factor : two ~12mm x ~6mm die
• Electrical Requirement: 3LM interconnect

Required for signal, PoP and PDN/SI needs

• Package = 15mm x 15mm x <1mm

Required to meet the usual SP constraints

• Cost requirement < 1c/mm2 in HVM

 

SoC large die partitioning challenges

–What function goes on which die

–Balance of die areas

–Power-performance trade offs

 

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The SEMI ISS (Industry Strategy Symposium) brings together industry leaders to share their opinions on where our industry is going. The US meeting is held each January in Half Moon Bay, CA.

The new darling of the microelectronics industry is obviously the Internet of Things (IoT). Many of the speakers focused on this topic though there was far more predicting than there was hard data. The thing that we know least about is always promoted as the next savior…correct ?

VLSI Research

Andrea Lati VLSI research showed an interesting slide on their opinion of what went right and what went wrong in 2014.

Capex continues to be concentrated in the big 3 with Intel, Samsung, Global Foundries and TSMC responsible for 72% of capex expenditures.

 

Assembly and Test capex remains a fraction of IC expenditures:

 

Assembly equipment sales are not expected to get back to 2010 levels till 2018.

 

Intel

Frank Jones, Vice President, GM of the internet of things group in Intel gave their perspective on IoT.

This is the first time I have seen anyone break out the predicted chip requirements by number of units and price. My presumption has always been that IoT would require super low cost technologies. Make of these projections what you will.

 

Broadcom

Scott McGregor CEO of Broadcom concurred with the IFTLE oft quoted theme that 28nm may be the sweet spot in terms of scaling lowering the cost per transistor.

 

IFTLE had been quoting the NRE costs of design at the 22nm node as $150MM. We now see that the projection for design at 16nm is up to $350MM making it even less accessible to most electronic device manufacturers.

 

An interesting conclusion that Broadcom has reached is that cost reductions in the future will result from better design engineering rather than better process engineering.

Samsung

Jim Elliot, VP of Samsung memory, pointed out that while cell phoned has just about saturated the market globally, smartphones are only in the hands of 30% of the world’s population.

 

I especially liked their photo of a cargo plane being required to transport a 3.75 Mb IBM disk drive in 1956.

 

Linx

Mike Corbet, Managing Partner for Linx examined the wafer fab materials (ALD, CMP, CVD, ECD, Litho, PVD, SOD and Process Chemicals) market. The following plot shows that litho materials will dominate logic wafer fab materials cost as we move forward.

 

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Let’s take a break from the conference circuit to take a look at some significant Samsung goings on in the industry.

Battling over Apple

Not since the Garden of Eden have we seen so much activity generated by an apple?

Recall, Apple signed up TSMC back in 2013 to produce its future A series processor chips while undergoing legal battles with Samsung their current provider. However, Apple has not been unable to completely disengage from Samsung. Both TSMC and Samsung produced the 22nm A8 processors for the iPhone 6  though TSMC had the majority of the order.

Now, according to South Korea’s Maeil Business Newspaper, Apple has turned back to Samsung to manufacture its A9 chip. Reports are that Samsung will get 75% of the chip production for the next iPhone [link].

Samsung reportedly began production of Apple’s A9 in their Austin TX plant using the 14nm FinFET technology. Samsung has 14nm FinFET production capability in both Austin, and Giheung, Korea, but will produce A9 only in Austin initially. IFTLE guesses that this “technically” makes the chips “made in the USA.”

Rumors of Samsung dropping Qualcomm Snapdragon in next Galaxy phone

 

Samsung also is putting significant pressure on Qualcomm with the pervasive rumors that Samsung will use its own microprocessors in the next version of the Galaxy S smartphone. Both Qualcomm and Samsung have declined comment.

Citing “people with direct knowledge of the matter,” Bloomberg has reported that that Samsung, “…tested the new version of Qualcomm’s Snapdragon chip, known as the 810, and decided not to use it”. Qualcomm’s Snapdragon processors, combined with its cellular baseband chips, have dominated the market for smartphones in recent years.

Qualcomm has faced rumors in recent months about potential overheating in the 810. While it is believed that Qualcomm has solved the 810’s overheating problems, the issue has put Snapdragon 810 production a few months behind schedule [link].

Qualcomm has publically confirmed that it will no longer supply chips for a “large customer’s flagship device”. While the company did not confirm that this was Samsung, the firm in question is big enough for Qualcomm to lower its 2015 outlook in its first quarter fiscal financial results [link].

It remains possible that Qualcomm will convince Samsung that they have fixed the overheating problem and be reinserted into the Samsung phone.

Samsung mass producing high-density ePoP memory for Smartphones

Samsung has announced that the company will be mass producing the extremely thin ePoP (embedded package on package) memory, a single memory package consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller for use in high-end smartphones [link].

The 3GB LPDDR3 mobile DRAM inside the ePoP operates at an I/O data transfer rate of 1,866Mb/s, with a 64-bit I/O bandwidth.

 

Because of its “thinness and special heat-resistant properties,” Samsung claims that the smartphone ePoP does not need any space beyond the 225 square millimeters (15 x 15mm x 1.4mm high) taken up by the mobile application processor. A conventional PoP (also 15 by 15mm), consisting of the mobile processor and DRAM, along with a separate eMMC (11.5mm by 13mm multimedia card) package, takes up 374.5 square millimeters. Replacing that set-up with a Samsung ePoP reportedly decreases the total area used by approx. 40%.

Samsung is basically stacking all the memory, both RAM and NAND, on a single ePoP module that’s then positioned on top of the processor, rather than beside it as shown below.

 

The use of such ePoP chips seems to be a likely choice for the upcoming Galaxy S6. It is intended to be used in mobile devices packing 64-bit processors and 3GB of RAM which is  what’s rumored to be spec’ed in the Galaxy S6 and other top mobile devices later this year.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE.

By Dr. Phil Garrou, Contributing Editor

Closing our look at presentations from the RTI ASIP Conference lets check out what Rozalia Beica had to say about the latest tech buzz word “the Internet of Things.”

Yole – Internet of Things

Rozalia Beica is defining IoT as “Objects becoming interactive information sources…..while the internet connects people…..IoT will primarily connect machines.”

Sensing applications include:

 

Yole predicts that the main applications of IoT sensor devices will be:

 

Yole lists the following as IoT challenges:

 

Invensas

During Sitaram Arkalgud’s presentation on assembly challenges in 2.5 and 3DIC, he addressed the issue of unbalanced interposer warpage. As we see in the table below, backside RDL dielectric thickness and balance can have significant impact on substrate warpage.

 

What’s going on with TSMC and  Qualcomm

From our friends at Digitimes comes rumors that Qualcomm is having problems on multiple fronts

Taiwan Semiconductor Manufacturing Company (TSMC) will reportedly be facing  tough questions at its upcoming investors conference to be held on January 15…. TSMC chairman Morris Chang is expected to host the January 15 conference

TSMC is expected to address speculation printed in the Chinese-language Liberty Times on January 14, that Qualcomm has put a halt on trial production of 16nm FinFET at TSMC. According to a Chinese-language Economic Daily News (EDN) report, citing sources in TSMC’s supply chain, TSMC has postponed the installation of its 16nm production lines to the 2^nd half 2015 instead of the 1st half as originally planned,.

Further rumors indicate that Qualcomm’s Snapdragon 810, the first  20nm Snapdragon chip manufactured by TSMC, is suffering from overheating issues. The overheating issue is likely to cause delay of Snapdragon 810 shipments, the Liberty Times reported. The chips are scheduled to be shipped starting March.

TSMC also reportedly plans to temporarily reduce the production of its 20nm process by 20%.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…