By Dr. Phil Garrou, Contributing Editor

Let me start by saying this year’s IWLPC presented what I consider to be the best program in their history. Congrats to the organizing committee for upgrading the technical content of this conference. Collecting and sharing both the presentations and the papers was an added benefit to attendees.

We will first take a look at presentations that described new polymer dielectric advancements.

HD Micro

Matsukawa of HD Micro described their “Low temp curable PI/PBO for Wafer Level Pkging”.

For next generation advanced packaging technologies, the most important requirements for dielectric materials are low temperature curability, high lithographic performance, high chemical resistance, and low warpage. They report on new low temperature (<200⁰C) curable PI and PBO.

Conventional photosensitive PIs and PBOs have required curing temperatures greater than 300ºC to complete cyclization as well as advance polymerization. To formulate low temperature curable materials, they re-designed the polymer backbone in order to enhance cyclization and changed the cross-linker to form a strong network structure even when cured <200⁰C. They presented the following table comparing “conventional PI” (what ever that is ??) to the new generation PI as shown below.

Generally positive tone photo-definable materials are composed of a PBO precursor, a photo acid generator, cross-linker etc. Regarding the new positive tone PBO, a suitable photo acid generator and cross-linker combination was selected to increase the resolution while also improving the adhesion to Cu, which has been a significant problem for past generation products. Properties are shown below.

Toray

Araki of Toray discussed their “Novel Low Temp curable positive tone photo dielectric material with high elongation for panel processing”.

Dielectric materials for redistribution layers (RDL) are one of the most important materials for fan out panel level processing (FOPLP). Toray introduces a low-temperature curable positive-tone photosensitive dielectric material with the high elongation property for fabricating RDL on FOPLP. The high elongation property was achieved by the introduction of flexible molecular skeleton in the base polymer backbone to increase the entanglement of each polymer chain. Cured films showed elongation up to 80%. This positive-tone photosensitive material offers fine pattern (3 um trench and 5 um line and space) with good sensitivity (300 mJ/cm² (i-line)) and shows high chemical resistance toward resist strippers. Properties of their new PI are shown below.

Hitachi Chemical (HC)

Fukuhara of Hitachi Chemical described their “Photo-sensitive Insulation Film for Encapsulation and Embedding” Conventional PoP with flip chips mounted on BGA like substrates is shown below compared to a fan out PoP.

In order to make a high density connection between upper and lower packages, it is necessary to form fine pitch through holes on the bottom package. These through hole vias can be formed by laser drilling. HC has developed a laminate photo film which allows encapsulation of the die and subsequent photo formation of the required vias through the film as shown in the process below.

 

Reliability results are show below.

Onozeki of Hitachi Chemical discussed “Wafer Level Packaging Materials and Processes” where he examined the influences of the material properties of temp bond adhesives (TBA) and epoxy mold cmpds (EMC) on the warpage of FO-WLP during the fabrication process by both of the experiments and finite element analysis.

For TBA, it was found that “the deformation of TBA results in relatively free shrinkage of EMC on the support, and Young’s modulus of TBA influences on the warpage most significantly. The small Young’s modulus TBA suppressed the warpage regardless of the support materials”. As for the EMC, “…the low Young’s modulus, low CTE and low Tg are effective to reduce the warpage after post mold curing. The warpage after grinding EMC was smaller than those after post mold cure and there was no big difference in the influence of the mechanical properties”. As for FO-WLP structure, the wide die pitch, thin EMC and thick die are effective to reduce warpage. Especially, the wide die pitch contributes to reduce the warpage. 4 layers re-distribution layer with line and space of 2 and 2 μm was successfully fabricated. The layers were interconnected with small diameter filled Cu vias of 5 μm. The vias were formed in the photosensitive dielectric material. A bias HAST test revealed that this material had enough insulation reliability.

JSR

Okamoto from JSR discussed “Fine Pitch Plating Resist for High Density FOWLP”.

For the next generation of high density FO-WLP, RDLs as low as 2um are reportedly required to support more I/O’s and multiple RDL layers. In this situation, RDL plating resists have to provide higher resolution with a wider common depth of focus margin than conventional resists because there are often large topographic gaps between the chip and the mold substrate. The plating resists must also be applicable for various plating solutions under each recommended process condition. JSR describes the development of a resist that has resolution to 0.7um L/S at 5um film thickness and has excellent resistance to various plating solutions.

For all he latest on Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Hope all my readers in the USA had a great Thanksgiving. For those of you around the world, this holiday occurs in late November in the US when families get together for a 4-day weekend. I was with my two sons and my granddaughters Hannah and Madeline (who you have watched growing up ) in Houston and it was great to spend some time together. Younger son Christopher, who is a Chef in Maine, joined us and helped with the cooking activities.

 

Now let’s finish our look at the 2017 IMAPS Conference.

Northrup Grumman

Under the DARPA/MTO SHIELD program Northrup Grumman led a team of GaTech, Sandia, Kilopass and RFID Global solutions have developed a supply chain traceability and authentication method to protect against counterfeit electronic parts. The solution consists of the incorporation of a 100 x 100 x 20um “chiplet” (they call dielet) fabricated in 14nm CMOS. Authenticity is verified using an Rf probe to energize and communicate with the chiplet. Putting the size of the chiplet into perspective, the pic below shows the chiplet on the head of Lincoln on the back of a penny.

The chiplets are manufactured using GlobalFoundries 14nm FinFet technology. The 300mm wafers are thinned and the 20um dicing streets result in ~ 4MM chiplets per wafer. Pick and place of these tiny chiplets is “challenging” but they have developed a technique to insert them into the host packages. Process flow is shown below:

Shinko

Kyozuka of Shinko discussed the “Development of Thinner PoP Base Packages by Die Embedded and RDL Structure.”

PoP structures can achieve thinness by embedding a die (or dies) into a package thus achieing height reduction for devices like APS (application processors). Their “die embedded with RDL” structures are shown in the fig below with design specs.

The process flow is shown in the fig below.

The FC process is done by TCB (thermos-compression bonding) followed by capillary underfill . After die mounting the cover layer of laminate is vacuum laminated and vias are laser drilled to make connection between the substrate and the top RDL. Expected issues with warpage were controlled by controlling layer thicknesses and copper density on the layers.

Via formation included laser drilling, desmear, electroless and electrolytic copper plating. Vias were tested under condition B (-55 to 125◦C) with 75 and 100um visa passed such testing.

IMEC

Bart Vereecke of IMEC discussed “Investigation of wafer level packaging schemes for 3D Rf interposer multi-chip module”. The fig below schematically shows the structure with a GaAs MMIC mounted on the silicon interposer. The interposer consists of two metal levels sandwiched around a MIM cap layer. A Cu/Ni/Sn seal ring is designed in for bonding Si cap layer. The interposer is made of high resistivity Si to minimize Rf losses.

They examined different wafer level packaging approaches for fabricating the interposer and populating them using either D2D or D2W bonding of the MMIC components followed by wafer level encapsulation. These are compared in the table below. All of the process flows appear to have issues.

Axus Technology

Bob Roberts of Axus presentation “Technology transfer for MEMS and Adv Packaging” was a nicely written review of the use of CMP and the thinning of silicon wafers which I can recommend to those wanting a refresher on the technology.

For all the latest on Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Before we get back to the IMAPS 2017 conference, a few important items:

Consolidation – and the beat goes on

We have talked a lot about consolidation and why it is happening. [see IFTLE 255 “Consolidation continues …” and IFTLE 241 “Simply Obeying the Laws of Economics” ]

On November 6th Broadcom announced its intention to buy its rival, Qualcomm, for ~ $130B, including debt. If successful, it would be the largest deal in the history of the technology acquisitions. Following the consolidation trail, NXP acquired Freescale and Qualcomm is trying to acquire NXP and Broadcom is trying to acquire Qualcomm. Certainly a sequence that no one could have predicted a few years ago. If Broadcom successfully acquires Qualcomm, the combined group would become the world’s third-largest chipmaker, behind Intel and Samsung. If they combine, with no divestments, Qualcomm and Broadcom would control between 50%-60% of the market for Wi-Fi chips and 27% of radio-frequency chips for mobile devices.

The Economist offered the following table listing mega mergers (consummated and in process) [link]

The Economist also offers the comment that “with Qualcomm’s pending purchase of NXP and Broadcom’s of Brocade, what looks at first glance like a merger between two giants is actually a four-sided deal. It would be difficult to unite so many different divisions and business units all at once” It certainly will be interesting to see what happens here!

Continuing our look at IMAPS 2017

InFO like FOWLP from ASM Pacific & partners

John Lau representing ASM coauthored the presentation “Fan out Wafer Level Packaging of Large Chips with Multiple Redistribution Layers” with a long list of co-workers. The design is a chips first face up process looking a lot like the TSMC InFO. The detailed descriptions of the processing are much appreciated. The overall process flow is shown below.

 

As is the case for InFO the key processing sequence is plating up the contact pads on the wafer (30um), molding the wafer and hen grinding back the mold cmpd to expose the copper pads much like you would a TSV. Their mold compound is Nagase R4507 a liquid EMC with 85% filler content and an average filler particle size of 8um.

Subsequent processing of the RDL layers is shown below. The smallest L/S features on the bottom RDL layer is 5/5.

 

From this groups 2^nd paper “Characterization of fan-out WLP” we learn that

– die attach accuracy and pitch compensation are the key issues that need to be controlled for accuracy in the RDL process

– die tilt is an important factor that affects the contact pad reveal so the die bonder should be optimized to control leveling

– molding concerns include die shift, warpage and voids. Mold cmpd choice will affect warpage results.

Namics & Hitachi Chemical

The presentation “Development of Liquid Compression Molding (LCM) Materials for Low Warpage” by Namics and Hitachi Chemical detailed the properties required for a low warpage LCM. They were able to substantially reduce LCM warpage by using aliphatic, flexible epoxy resins with low modulus and low cross link density.

Hitachi Chemical

Hitachi Chemical also detailed their studies on “Highly Reliable Cu Wiring Layer for 1/1um L/S using newly Designed Insulation Barrier Film.”

It is generally agreed upon that organic substrates fabricated by the semi additive plating process is limited to 8um L/S . To achieve finer interconnect pitch required by future FOWLP Hitachi Chem has studied trench wiring to create such high density structures. This sequence is typically laser ablation of the trenches in the dielectric, copper plating and subsequent planarization by CMP. Barrier metal is required to minimize copper migration so the seed layer for plating is generally 50nm of Ti followed by 100nm of sputtered Cu. The processes are compared below. For reliable HAST testing of 2/2 L/S they have found that covering exposed Cu with a Ni barrier layer is required.

They have also examined chemically amplified, negative tone, photosensitive dielectrics to achieve below 2/2 L/S. This processing includes the use of an insulation barrier film which shows low moisture absorption, low anionic impurities and high hydrolysis resistance. Using this combination they were able to achieve 1/1 L/S.

For all the latest in advanced packaging, stay linked to IFTLE…