According to Wu, the 53 years old semiconductor industry now accounts for 0.6 percent of worldwide GDP. He sees the semiconductor growth rate converging to ~ 7%. For the period 2011-2015 he is forecasting four years of stability with “mild growth” He sees this as a period of consolidation where only bold companies (“the bold ones”) will continue significant R&D and CAPEX spending. Wu described growth in the semiconductor industry over the past several decades as being driven by key applications. Aerospace in the 1970s, mainframe computers in the 1980s, PCs in the 1990s (global penetration now ~ 20%) cell phones in the 2000s (global penetration ~ 60%) and smart appliances in he 2010s . Wu noted that all of the applications are still running in huge volumes today.

Wu sees the industry polarizing into two factions ; (a) the infrastructure faction consisting of manufacturing heavyweights and (b) a systems faction [ IBM, HP, Apple] using software to interweave their product solutions and worrying about “branding “ their products. To quote Wu “The manufacturing heavyweights are driven by the systems power houses”

When comparing front end and back end operations Wu quoted figures showing that from 1980 to today $500B in CAPEX has been spent on the front end operations (avg of $26B/yr) whereas only $133B has been spent on the back end.

Lerner also indicates that their new product family “AquiVantage” which provides metallization
for 3D Interposer and via last (backside) packaging is showing significant cost reduction for these applications.

AquiVantage uses the same basic technologies as the Alchimer’s wet processes for TSVs, reportedly providing concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating CMP and dry deposition steps. It also supports smaller vias with higher aspect ratios. On the backside, the AquiVantage process allows selective maskless growth of the on-silicon isolation layer, eliminating an expose/develop/etch/clean lithography process cycle.

EVG

Wimplinger noted that they have 1 customer already in production and that several are very close. Although they are wary to name names without customer approval , we have all seen their joint announcements with Amkor and their equipment installed at the joint programs of Leti / ST Micro and Fraunhofer Dresden and Global Foundries.

When asked to sum up their activity in the now retired EMC-3D consortium of which they were a co-founder, Linder indicated that the EMC-3D roadshows were helpful to show the industry that there is a supply chain for 3DIC and that the technology was doable. Linder reports that by the end, there was a clear consensus on a std process flow and all in all he views this as a very successful collaboration.

EVG has recently announced that they have joined the Ga Tech 3D Systems Packaging Research Center as a Manufacturing Infrastructure Member. Linder indicates that their mission is to develop “â??¦technologies that will make silicon and glass interposers with TSVs a truly affordable packaging solution." EVG’s temporary bonding and debonding, chip-to-wafer bonding and lithography technology and process know-how will be included in the PRC’s Silicon and Glass Interposer Industry Consortium research program.

EVGs new inline metrology module reportedly allows customers to implement in line process control for thin wafer processing. The in line metrology module can detect a variety of process irregularities and defects during temporary bonding and debonding including the TTV (total thickness variation) of the carrier wafer, adhesive layer, bond stack and thinned wafer; bow/warp of the boded stack and voids in the bond interface.

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They claim that a finer chip I/O pad-pitch is achieved due to better CTE  matching between the die and support wafer and that the high-cure-temperature resins used, make the RDLs more reliable. Their name for this is SiWLP for SiP (system in package) WLP. Another acronym I greatly dislike since it will always be interpreted as "silicon WLP" for obvious reasons.

Several of you at Semicon West requested that I make the figures larger (i.e more readable). I am stuck with the limitations of "blogger" software which is very HTML sensitive but I will try.

Anyway, this week we will continue to take a look at packaging activities at the 2011 ECTC.

IMC formation in fine pitch microbumps

Samsung found that Ni₃Sn₄ IMC formations at interface between SnAg solder and their 4µm Ni UBM degrades the mechanical properties of solder joint, and increases resistance of solder bump. IMC growth rate and Ni UBM dissolution rate were calculated.

Thin IMC changes into thick IMC during HTS. During 150°C annealing for 1300 hours, Ni UBM was converted into Ni₃Sn₄ IMC. Even though there are such microstructure changes, resistance of micro bumps were not changed during HTS 150°C. Resistance started to degrade after 1000 hours at 180°C due to void formation at interface between IMC and Al trace line. They found that open failure occurred when Ni UBM completely consumed and failure time is consistent with total consumption time of Ni UBM.

ITRI reported similar results on their 12µm microbumps (5µm Cu/3µm Ni/2.5µm SnAg) on 20µm pitch. The intermetallic phase formed at the interface was identified as Ni₃Sn₄, the thickness of this layer increases with time and/or temperature in agreement with the results of Samsung. They also found problems with seed undercut during processing. When the thicknesses of the Cu seed layer sputtered on the wafer was reduced from 5000Å to 2000Å and a dry etching was used to remove the seed layer after bump plating and PR stripping, the undercut of Cu posts could be confined to less than 10%. A dramatically undercut Cu pillar (left) takes on the appearance of mushroom plating.

ITRI reports that conventional reflow with flux is seldom used for the assembly of microbumps because the gap size between chip and interposer, i.e. 20µm, makes it difficult to remove flux residues which could cause void formation within the underfill and degrade the reliability.

Copper pillar bump on lead

Qualcomm and STATS ChipPAC reported on the unique combination of copper pillar bump and bump on lead (more accurately called bump on trace). Their suggested acronym CuBOL just doesn’t identify the structure well enough for me, so I prefer and humbly suggest CPBOL for copper pillar bump on lead.

The technology which utilizes the fcCuBE technology of STATS ChipPAC (see USP 7368817), involves using Cu pillar bump attached to a narrow trace or "bond-on-lead (BOL)" without any solder resist confinement (open SR) in the peripheral I/O region of the die. This enables improved routing efficiency on the substrate top layer thus allowing 4L to 2L reduction in the substrate without compromising functionality. The cost of the FC package is lowered by means of reduced substrate layer count, removal of solder on pad (SOP) and solder mask and relaxed design rules. BOL or narrow pad which takes significantly lower space on the top layer allowing more area for escape routing; thus enables relaxed Line / Space (L/S) design rules which in turn help to lower the substrate cost significantly. Similarly, the ‘Open SR’ concept in CuBOL further allows additional escape routing to be fit in the same bump-to-bump spacing; which offers increased routing efficiency and I/O density on the top most layer. The combination of BOL and Open SR together thus allows conversion of 4L substrate design into 2L without compromising I/O density.

Fluxless chip-on-wafer (C2W) bonding

ITRI reported on their studies fluxless joining of 30µm pitch Cu/Ni/Sn-Ag bumps. In this study, the Ar + H₂ plasma treatment was applied on the C2W process for the purpose of tin oxide removing and enhancement of the bondability. During bonding they found that gap control was very important since poor control could lead to a narrow necked joint ( c) or solder ozzing out of the joint and possible causing shorts (b).

After bonding and underfilling, temperature cycling test (TCT), high temperature storage (HTS) at 150°C, highly accelerated stress test (HAST) and electromigration (EM) reliability were performed on the chip stacking module to evaluate the reliability of solder micro bump interconnection assembled by the C2W process. Without underfilling a significant number of samples failed . With underfilling HTS greater than than 2000 hrs; TCT greater than 3000 cycles and HAST testing were confirmed.

Reliability of Xilinx interposers

Xilinx shared some of the reliability data on their 28nm FPGA with interposer structured. Recall the chips and the interposer are manufactured by TSMC, the interposer is bumped by TSMC, and the chips are bumped by Amkor. The final assembly is done by Amkor [see IFTLE 23, "Xilinx 28nm multidie FPGA…"]

The silicon interposer test chip with thousands of micro-bumps at 45µm pitch has been fabricated.

The silicon interposer is 100µm thick, and is mounted on a 42.5mmÃ??42.5mm substrate through 180µm pitch C4 bumps. The TSVs are typically 10-20µm in diameter and 50-100µm deep. The walls of the TSV are lined with SiO₂ dielectric. Then, a diffusion barrier and a copper seed layer are formed. The via hole is filled with copper through electrochemical deposition. The interposer wafer is thinned to expose the TSV from the bottom side. The Cu overburden is removed by CMP followed by passivation and UBM process. C4 bump is electroplated and reflow soldered on top of the UBM layer. FPGA wafers are bumped to ultra-fine pitch in the range of 30-60µm using Cu pillar bump technology. The FPGA dies are diced and attached to the interposer top pads. The gap between the interposer and the FPGA die is filled using underfill material to protect the micro-joints. X sections of the overall assembly, the interposer and the micro joints are shown below.

Main focus of this study was to understand the impact of moisture and temperature cycling on the microbumps and adhesion of the underfill to top FPGA die and thin TSV interposer substrate. Underfillls were first evaluated and found to perform better with no clean flux. Plasma cleaning was implemented before underfilling and gap height was increased to improve underfill flow.

With improved gap height and plasma cleaning, no delamination was observed either in L5 preconditioning or after 264 hrs of HAST at 110°C. All the samples passed 1000 cycles of TCB. Cross-sectioning of interposer after 1000 cycles confirmed that there was no protrusion of TSV. An example of cross-section of micro joint after 1000 TCB cycles.

Fraunhoffer through mold vias

Fraunhofer IZM examined chip embedding into polymer by molding and redistribution by PWB technologies for highly integrated low cost packages.

The general process flow starts with the lamination of an adhesive film to a carrier. This adhesive film has one pressure adhesive side and one thermo-release side (heating the tape, the thermo-release side of the tape loses its adhesion strength). Dies are placed, active side down, towards the carrier. Molding is done by large area compression molding. For chip redistribution, resin coated copper is used. After lamination of the RCC film on both wafer sides in one step, micro vias are laser drilled to the die pads and through mold vias in the same process step to connect to and bottom side. By plating both, via filling and die pad connection to the copper layer and the top copper layer to the bottom copper layer are achieved.

Mold materials with small filler particles (maximum filler particle size of 25µm) allow the fabrication of vias with a very precise and smooth via surface but materials with finer fillers currently have higher viscosities and lower filler content leading to a higher CTE.

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In late June Elpida announced what it claims is the thinnest available DRAM device, a new 0.8 mm four-layer package of 2GB DDR2 mobile RAM chips, assembled using package-on-package (PoP) technology. [link]

Customers have been using two-layer 0.8mm packages, rather than the thicker 1.0mm four-layer PoP, so systems needing 8GB of DRAM needed two stacks of 4GB product. Now they can get four layers of 2GB in one package. Yields and cost are reportedly the same as for existing 1.0mm products. Advantages of PoP for mobile devices includes: mounting space is reduced, individual packages can be tested, less wire bonding used (minimizes losses. Volume production ramp is slated for 3Q11.

A few days later Elpida, who exactly a year ago made headlines as the first to announce commercialization of memory stacked with TSV, [ see IFTLE 8, “3D Infrastructure Announcements and Rumors”] has now announced that it had begun sample shipments of DDR3 SDRAM (x32-bit I/O configuration) made using TSV stacking technology.[link]

The device is a “low power 8-Gb DDR3 SDRAM that consists of four 2-Gb DDR3 SDRAMs fitted to a single interface chip using TSV”. Target applications reportedly include tablet PCs, extremely thin PCs and other mobile computing systems. The new TSV DRAM will reportedly enable significant energy savings as well as making portable electronic devices smaller, thinner and lighter. Elpida believes that the new devices in notebook PCs will demonstrate a 20% reduction in operating power and a 50% reduction in standby power compared with systems that use the standard SO-DIMM configuration which use standard wire bonding technology. Power consumption is reduced because the TVSs shorten the interconnect between the chips, thus reducing parasitic resistance and capacitance.  In addition, chip height is decreased and the DIMM socket is eliminated. Chip mounting area is reportedly reduced 70%.

  For all the latest in 3D IC and Advanced Packaging stay linked to IFTLEâ??¦..