Finishing up our look at the Suss Technology workshop at SEMICON West.

Nanium

Ricardo Gai, head of eWLB engineering at Nanium gave a presentation on wafer level fan out packaging, FO WLP. Nanium, headquartered in Portugal, is derived from the following bloodlines:

Nanium has been in 300mm HVM of  FO WLP since Q3 2010 and has shipped more than 350MM packages. For a complete discussion of eWLB see IFTLE 124, “Status and the Future of eWLB.”

Process Challenges with eWLB:

• Warpage

– Warpage and shape changes during processing; stiffness is a key parameter to control;

– Equipment modifications are required to handle FO-WLP wafers

– hardware – new end effectors and new chuck sealing

– software – upgrades for warpage handling

• Die-Shift – In case of complex devices like (Multichip SiP), mask aligners are not capable of overlay requirements and a stepper is required.

Multi-Layer RDL for multilayer RDL the overlay must be smaller than the die shift. This also requires stepper technology.

Fine RDL Line Width / Space and Fine Ball Pitch – – better resist technology is necessary to achieve L/S = 10/10

• Cost Pressures

– more die per carrier by using smaller edge exclusion zone

– larger substrate sizes

– 300mm and large panel processing to reduce costs.

• Future Challenges:

– thinner substrates will require temp bonding and front side protection

GlobalFoundries

Jon Greenwood of GlobalFoundries gave a presentation on 2.5/3D readiness for HVM. Global Foundries is dedicated to support the Collaborative Partner Model:

They are creating a supply chain where GF is responsible for the wafer processing and backside integration (BSI) and assembly is owned by the OSAT partners.

As we have discussed before [see IFTLE 142, “GlobalFoundries2.5 / 3D at 20nm…” ] 2.5D interposer work is ongoing in Singapore and 3D activity is in NY. In June 2013, they announced a certified set of design flows for 2.5D interposers. As the next slide shows, by 2015 they hope to offer TSV “in all nodes.”

Greenwood announced that GF thinks their 2.5D and 3D packaging capabilities are proven and their primary focus moving forward is yield and COO reduction.

Amkor Ron Huemoeller Sr VP of Advanced Product Development at Amkor presented their position on 3D/2.5D Market readiness.

Design capability status – established

– Mass production of optical sensors since 2008

– Worlds first fully integrated MCM TSV product started production in 2011

– System integrated architecture proven on many platforms such as:

– multiple logic on Si  interposers

– logic + memory on Si interposers

– memory / memory stack

– memory / logic combination

Manfacturing Capability

– fine pitch Cu pillar in HVM

– wafer thinning equipment and infrastructure in place

– TSV etch equipment and infrastructure well-established

– Backside passivation – equipment and infrastructure well-established

– Backside bumping – equipment and infrastructure well-established

– wafer support – equipment and infrastructure in place but still needs improvement

– Assembly can be done chip-on-substrate, chip-on-wafer or chip-on-chip

– more work is needed on testing memory prior to committing to package stack.

Memory

– End customer chooses memory supplier (only primary memory sources today)

– Receive as KGM on tape and reel

– receiving 2, 4 die stacks in wide IO format

Amkor now sees interposer use reaching “value markets” post 2015.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

Finishing up our look at the presentations at ECTC 2013 in Las Vegas.

Shinko and CEA Leti detailed their presentation entitled “Warpage Control of Silicon Interposer for 2.5D Package Applications.”

Large silicon-interposers when attached to an organic substrate can cause significant warpage problems. Shinko / Leti examined several warpage control techniques including:

– Using a  “chip first process” where chips are mounted on the interposer first  vs “chip last process” where the silicon-interposer is mounted on the organic substrate first and chips are mounted onto the interposer last.

– using various underfill resins.

– using Sn-57Bi solder and thus lowering peak temperature 45-90 degree C. This reduced warpage after reflow to 75% of that using SAC305.

Comparison of warpage using different assembly sequences is shown below.

Warpage of silicon-interposer using three types of underfills (shown below) for  0 level assembly (micro bumps) is shown below. Maximum warpage using U.F. A1, A2 and A3 were 108, 123 and 132mm, respectively. The lowest warpage was obtained at using U.F. A1. With U.F.A3, solder bump open failures were observed. The authors conclude that “… using underfill material with low Tg and high storage modulus for 0 level leads to high reliability.”

TSMC and customer Xilinx presented “Reliability Evaluation of a CoWoS-enabled 3D IC Package” which used FEA to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Focus was especially on the fatigue failures of the C4 and BGA joints. Experimental data collected on CoWoS test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme.
Results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid.  While a  thicker lid has the higher stiffness and better co-planarity, the higher constraint from the thicker lid induces higher stress inside the package which negatively impacts  C4 bump fatigue and the micro-bump Ti/Al delamination.

C4 bump layer underfill with Tg of 70 C or 120 C, were studied. The underfill with lower Tg has higher driving force to C4 bump fatigue. When temperature is above Tg, the underfill has much lower Young’s Modulus which has much lower capability to protect C4 bump; and therefore the underfill with lower Tg has higher driving force to C4 bump fatigue. On the contrary, the underfill with lower Tg has lower driving force to Ti/Al delamination in the micro-bump structure. TheC4 underfill with lower stiffness can play as a buffer layer and results in lower driving force to Ti/Al delamination in microbump.

IMEC reported on “Key Elements for Sub-50μm Pitch Micro Bump Processes.”
Scaling the ubump pitch from hundreds to a few tens of microns is not straightforward. Several process parameters need to be taken into account to allow a reliable Cu(Ni)Sn ubumping process. One of the challenges for fine pitch Cu(Ni)Sn stacking is to obtain a high bump uniformity. The non uniformity prevents Cu and Sn from having good contact and subsequent intermetallic formation and increases the risk of underfill entrapment.

A bump scheme that offers better margin for alignment error is better based on a scheme where the size of top die bumps is smaller than the size of the bottom pads. For example it is better to achieve  20μm pitch with 7.5μm bump on 12.5μm pad than with 10μm bump and pad because  equal bump and pad diameter can tolerate only 2μm misalignment whereas the  7.5μm/12.5μm bump/pad can tolerate 5μm. This is a significant difference when working close to the stacking tool’s limit of alignment accuracy.

Details on the plasma treatments necessary when attempting to plate into these fine featured plating resists are also discussed.

RTI  detailed a process for the fabrication and bonding of 100 and 200um  thick silicon interposers with filled 4:1 AR copper filled TSVs and front side and backside multilevel metal copper/ thin film polymer  routing layers in their presentation ”Fabrication and Testing of Thin Silicon Interposers with Multilevel Front side and Backside Metallization and Cu-filled TSVs.”

For most applications, the desired thickness for Si interposers is below the thickness at which unsupported wafers can be safely handled through the necessary fabrication processes (i.e. 100 -200um). In these cases a temporary wafer support system, consisting of a carrier wafer and a layer of a temporary adhesive, must be used.

3M’s Wafer Support System (3M WSS™) and Brewer Science’s WaferBOND 9001™ were the temporary bond materials selected in the RTI program. Multilevel metal was done on either side of the interposer using polymer thin film dielectrics. The front side of the device wafers was patterned with two layers of Cu and three layers of polyimide (HD-4100 from HD Micro). After frontside patterning, the wafers were bonded face-down to temporary carrier wafers coated with temporary adhesive. Backgrinding and CMP were used to thin the wafers to a nominal thickness of 100 um. After thinning, a backside Cu routing pattern was formed between two layers of either  BCB 4024-40 (Dow Chemical), HD-8930 (polybenzo-bisoxazole [PBO] HD Microsystems), with curing temperatures of 250˚C and 200˚C, respectively, at or below the temperature limit of the temporary adhesive. The polyimide that we used for the front side MLM structure has a recommended cure temperature of 375 C which would be incompatible with any currently offered temporary adhesive.

Both the 3M and the Brewer wafer bonding solutions were found to be compatible with the processing of the different spin-on dielectric materials used to fabricate frontside and backside MLM structures. Successful debonding of the carriers was done both at the wafer level before dicing and at the die level after dicing and bonding to a substrate.

In both, the 100um and 200um interposer thicknesses with 25um or 50um diameter TSV respectively, an annealing step was found to be successful in preventing Cu from extruding from the TSVs during the subsequent polymer curing steps. Electrical testing before and after thermal cycling showed the high yield and stability of all of the interposer structures irrespective of the dielectric materials choice.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…