By Dr. Phil Garrou, Contributing Editor

At the recent 2015 Int Image Sensor Workshop, Ray Fontaine of Chipworks presented a review of “The State-of-the-art of Mainstream CMOS Image Sensors” Chipwork’s estimate, from other market research firms, is that the CIS market in 2014 was ~ $9B. Of this total it is estimated that Sony, Samsung and Omnivision hold > 66% market share driven by mobile phone and tablet camera chips.

Their look at the patent literature shows the field continues to grow with 2500 patents filed in 2014, the majority of them being processing patents.

Stacked Chip CIS

3D stacked CIS became a reality in 2012 when Sony announced the worlds first stacked chip CIS in consumer cameras. In 2013 they introduced the 8 MP ISX014 in a tablet computer [ref]

[P. Jagodzinski, “Sony ISX014 ¼ inch 8 MP 1.12um pixel size Examor RS stacked back illuminated CIS imager process review” Chipworks March 2013 ]

The first gen chips employed via last TSV to connect pads on the Sony 90nm CIS die to the pads on the Sony 65nm ISP. The die stack was partitioned such that most of the functionality of a conventional system-on-chip (SoC) CIS was implemented on the ISP die; the CIS die retained the active pixel array, final stage of the row drivers, and comparator portion of the column-parallel ADCs. The CIS (left) and ISP die (right) are shown below.

Click to view full size.

Sony’s 13 MP IMX214 second generation stacked CIS chips were fabricated using its 90/65 nm (CIS/ISP) technology generation. The key work on the second generation stacked process was to use the CIS silicon only as the active pixel array substrate and move the column readout chain and peripheral transistors to the underlying ISP die.

In 2014, Sony announced they were using TSMC as a foundry for the 40nm ISP wafers on the Apple iPhone 6/6 Plus iSight cameras. These chips incorporate Sony 90 nm CIS wafers and TSMC 40 nm ISP wafers.

In 2015, Samsung and OmniVision have both been sampling small-pixel, stacked chip CIS.

Given the continued, aggressive stacked CIS development underway from independent device manufacturers (IDM) and foundries it’s predictable that stacked chip adoption will occur very rapidly over the next few years.

IEEE 3DIC Conference Sendi Japan Aug 31^st

Click to view full size.

The IEEE International 3D System Integration Conference (3DIC) will be held in Sendai, Japan August 31-Sepember 2, 2015. After the first conference in San Francisco in 2009, the 2nd IEEE 3DIC Conference was held in Munich in 2010, and then Osaka in 2012. The forth conference was back in San Francisco in 2013 and the fifth conference in Cork, Ireland in 2014.

IEEE 3DIC 2015 will cover all 3D integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications. The conference invites authors and attendees to submit and interact with 3D researchers from all around the world. Papers are solicited in subject topics, including, but not limited to:

• 3D IC Process Technology
• 3D IC Circuits Technology
• 3D Applications
• 3D Design Methodology

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Amkor recently held a customer Symposium covering their activities. Let’s take a look at some of the interesting points that they covered on their fan out package platforms.

2014 Amkor revenue is clearly dominated by the communications segment.

When looking in general at the evolution packaging they see the largest focus on filling the gap between 1 and 10um as shown below.

Their packaging roadmap to address this gap area is shown below and is tied to their Swift and Slim product families. Such ultra thin packages will have to be handled by temporary bonding to a rigid substrate in order to process them.

From a mobile products standpoint they see the 5+um range filling most of the needed requirements for density/IO, whereas the SWIFT product line will be needed for < 5um BB module (SiP) requirements.

The SWIFT and SLIM processes are depicted below. SWIFT interconnect is carried out on an RDL bumping line by Amkor whereas 2-5um SLIM interconnect is fabricated by foundry.

Since interconnect is fabricated first, higher densities can be achieved, i.e. 2-8um L/S for SWIFT vs           8-15um for traditional chips first FOWLP.

In summary depending on the requirements of the application, different technologies are available and/or are being developed to meet those requirements.

Click to view full size.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

At the recent ConFab meeting in Las Vegas, aside from all the talk about consolidation (see IFTLE 241), Bill Chen from ASE and Li Li from Cisco put together a great Advanced Packaging session.

(L to r) Bill Chen (ASE), Ram Viswanath (Intel), Kevin Tran (Hynix), CP Hung (ASE), John Knickerbocker (IBM) and Li Li (Cisco)

CP Hung, VP of R&D for ASE discussed “Integrating 3D IC into the IC Packaging DNA” Hung proposed that 2.5D IC significantly extends FCBGA technology as shown in the fig below.

Kevin Tran of Hynix announced that HBM (high bandwidth memory) has completed the qualification for mass production in March 2015. Each application has different memory requirements, but most common are high bandwidth and density. He indicated that packaging technology has become a key enabler for high performance, small form factor, low cost memory solutions.

Hynix is readying HBM 2 which will be applied for HPC, graphics, servers and network computing. High end graphics products have already been announced like Pascal at Nvidia and Greenland at AMD. Can Intel be far behind? IFTLE thinks not.

Ram Viswanath of Intel pointed out that “…the ability to monolithically integrate diverse functionality on the die has become impractical due to technology complexity and affordability” and that “on package integration is playing a key role in bringing diverse functionality into smaller form factor.” Key focus is on delivering

– performance for servers

– form factor for wearable products

– cost/form factor for client products

-low cost for future IoT products

Intel’s evolution of dense interconnect is shown below. The Xenon Phi for HPC uses memory stacks on an interposer (reportedly Micron HMC).

Intel compares  side-by-side multichip packaging to 2.5D interposers to 3D stacking in the table below. (note – IFTLE cannot support some of the conclusions on EMIB without seeing the actual data first).

*2.5D designs are comparable

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Following up on the recent blog by my comrade, Dick James.

There are laws and then there are laws. “Moore’s Law” to me is more of an observation. Gordon Moore simply noticed what was going on and commented on it.  Powerful laws, to me, are usually laws of physics like Newtons law of gravity or Einsteins Law of relativity.

When we consider the laws of economics, many economists would contend that consolidation is a law,   i.e. a natural process which has happened consistently to all industries since the industrial revolution. Through consolidation a mature industry usually has only a few (2-3) players ( for instance Boeing and Airbus in the aircraft manufacturing business) whereas young industries like the internet may initially have hundreds.

So what does this have to do with microelectronics you might say. Well, just ask the former employees of Altera and Broadcom. If this were the early 1990s James Carville (Clintons spinmeister) would respond “It’s consolidation stupid” [I was not a Carvile fan as you can tell by the picture I picked out !] Consolidation is what happens as industries mature. We are in the midst of it, it’s natural and probably unstoppable.

Lets first take a look at what’s happened in the hard disk drive segment of our industry.

Greater than 200 companies have been in the hard disk drive business since the 1960s. They initially competed on data density and latency and smaller form factors. Most of that industry has vanished through bankruptcy, mergers and acquisitions. Surviving manufacturers are Seagate, Toshiba and Western Digital. Seagate  acquired Samsung’s HDD business in 2011;  Western Digital (WD) merged with Hitachi’s HDD business in 2011. This gave Seagate 40% of the HDD market and WD ~ 48%. The remaining ~ 12% was owned by Toshiba who acquired Fujitsu’s HDD business in 2009. Thus by 2012 what was several hundred players had been whittled down to 3 by, I contend, the laws of economics.

Now let’s look at DRAM.

In 1980 there were 40+ DRAM fabricators but by 2015 we are down to Samsung, Hynix and Micron. See the trend?

The best description of whats happening, that I have seen is the 2002 Harvard Business Review article “The Consolidation Curve” by G K Deans et. al. Their main point is that all industries have similar life cycles and knowing where your company stands in the process can help you plot a winning strategy.

They divide up the stages of all industries as follows:

Stage 1: the combined market share of the three largest companies is between 10% and 30%. Companies in stage 1 industries aggressively defend their first-in advantage by building scale, creating a global footprint and establishing barriers to entry, i.e. protecting proprietary technology or ideas. Stage 1 companies focus more on revenue than profit, working to amass market share.

Stage 2: Stage 2 is all about scaling. Major players begin to emerge and buy up competitors.  The top three players in a stage 2 industry will own 15% – 45% of their market, as the industry consolidates. The companies that reach stage 3 must be among the first players in the industry to capture the most important markets and expand their global reach.

Stage 3: companies focus on expanding  core business and continuing to aggressively outgrow the competition. The top three industry players will control between 35% and 70% of the market with five to 12 major players remaining. This is a period of large-scale consolidation plays. Companies in stage 3 industries focus on profitability, and pare weak businesses units. The well entrenched in this phase will attack underperformers. Recognizing start-up competitors early on allows market leaders to decide whether to crush or acquire them. Stage 3 companies should also identify other major players that will likely survive into the next, and final, stage and avoid all-out assaults on them which could leave both players injured.

Stage 4: In stage 4 the top three companies claim as much as 70% to 90% of the market. Large companies may form alliances with their peers because growth is now more challenging. Companies in stage 4 must defend their leading positions. They must be alert to the danger of being lulled into complacency by their own dominance. Stage 4 companies must create growth by spinning off new businesses or buying into aligned fields to broaden their market presence.

When you understand this then headlines like the recent “The next three chip firms to be acquired: Atmel, Lattice and Cavium are the top take out candidates for the rest of 2015”[link]

As most of the segments of our industry enter late stage 3 or early stage 4 the only question is whether you will acquire or be acquired, or as Carville said “ It’s the economy stupid!”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…