ALLVIA claims they are now ready for scaling to volume production. Good luck to them in this endeavor.

Novellus – Finally Putting 3D IC in their sights

When looking at the ECD (electrochemical deposition) landscape in relation to 3-D IC, the names Semitool, Nexx and Ebarra come to mind. They are attending 3-D conferences, making 3-D presentations and are engaged with customers on 3-D scaleups. When you look at this list one big copper plating player is noted by its absence – Novellus. Their equipment offerings include PVD and CVD Cu and W solutions and well as Cu plating technology. Their ECD copper tool “Sabreâ??¢” was one of the first on the market to meet the demands of dual damascene copper 12+ years ago.

I’m now glad to tell you that this lack of focus on 3-D IC seems to have been reversed in the last several months. Last July Novellus and the University at Albany’s College of Nanoscale Science and Engineering (CNSE) announced that they had formed a $20M partnership to conduct next-generation R&D into sub-22nm semiconductor manufacturing technology. As part of the agreement, Novellus will install three advanced thin film deposition tools-a VECTOR® plasma-enhanced chemical vapor deposition system (PECVD), a SABRE® copper electrochemical deposition system, and an ALTUS® tungsten chemical vapor deposition (CVD-W) system-at CNSE complex. It was announced that a team of Novellus researchers, located at CNSE, will be conducting leading-edge research into among other things copper fill for interconnects and copper TSV fill for 3-D IC.

On March 9th Novellus announced an advanced copper barrier-seed physical vapor deposition (PVD) process for the TSV market. The process uses Novellus’ INOVA platform to produce highly conformal copper seed films that are reportedly four times thinner than conventional PVD seed approaches. Novellus claims the process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent electroplating step. The ionized PVD process chamber causes a larger fraction of the sputtered film to land on the sidewall, which in turn results in a more conformal deposition. Novellus’ process can reportedly achieve void-free feature fill in a 60 micron deep, 10:1 aspect ratio TSV feature with vertical sidewalls using a 2000 angstrom thick copper seed layer. The conventional PVD approach requires an 8000 angstrom thick seed layer to achieve the same result. The 4X thinner TSV seed layer results in a substantial increase to system throughput and reduces the cost-of-consumables by greater than 50 percent as compared to conventional PVD approaches.

This was followed up a week later with an announced joint development program with the IBM “to design a manufacturing-worthy, copper-based, three dimensional (3- D) semiconductor Through-Silicon Via (TSV) process using Novellus’ SABRE(R) copper electroplating and VECTOR(R) plasma-enhanced chemical vapor deposition (PECVD) systems.”

Novellus has reportedly developed a unique, high performance SABRE ElectrofillTM TSV process that uses Novellus hardware and chemistries to achieve void-free fill with minimal copper overburden. Copper overburden is reportedly reduced by 75 percent, allowing conventional chemical-mechanical polishing (CMP) to be used instead of custom polishing slurries. They also claim that the SABRE TSV chemistries have faster plating times, resulting in higher throughputs.
To address the requirement of lower temperature dielectrics, Novellus’ VECTOR platform enables the deposition of stable dielectric films at temperatures <>

[from l to r: Vic Lozada, Raj Pendse, Flynn Carson, Lisa Lavin and Seung Wook Yoon]

Rumors are circulating that Freescale management, seeing the success that eWLB has been receiving, has revived their RCP process group and are looking to obtain further licenses. Rumors are that Broadcom is looking seriously at the RCP based devices. Talking with STATS who claims yields “..are already in the 90’s” for the 5-10MM units they produced in Q1 2010, it became clear that the reconfiguration step is not as simple as it looks on a power point slide. Molding compound shrinkage requires that the chips be unequally spaced across the wafer before molding compound is applied and cured and the subsequent RDL mask must match this unequal spacing – obviously. Multi die eWLB (i.e SiP ) have been qualified by the STATS team who now have stacked, (two sided) eWLB solutions in development. In any event, fan out WLP has officially taken off and will unquestionably become a major packaging option in the future.

Global Technology Development Focus Remains on 3D IC

I counted more than 25 presentations involving TSV based 3D IC. Although there were no commercial announcements, there was continued steady progress by nearly all the major players in the industry. By the way, I’m seeing more and more use of the acronym 3DIC so when doing lit searches you better use both.

I saw nothing to change my mind that the industry has narrowed process options down to vias middle (from the foundry) and vias last backside (from the OSATS). The latter mainly for devices such as CMOS image sensors which are already in full commercial production at players such as Toshiba, ST Micro and Samsung.

You can be sure that not having a source of chips with vias middle TSV is slowing down product development work. Currently, only those with their own IC fabs can gets chips containing built in TSV. While everyone is awaiting TSMC, Global Foundries and others, there appears to be a significant opportunity for R&D IC lines that can deliver test chips with vias middle TSV for developers to work with. IMEC has shown this capability, but who else out there can make such structures available ??

Please send me your info if you are or could be supporting this need.

ASE focus on 3D IC

It appears that with Cu wire bonding completely installed at ASE they can now focus on 3D IC. I’m told the EE Times article indicating that 3D at ASE was imminent [ASE Breaks Ground on New Packaging Plant] stirred significant activity at the ASE sales offices . Reports to IFTLE indicate that the new building in Kaohsiung (K 15) will indeed be used to bring all 3D equipment together, under one roof. Current D2D and D2W assembly from Chung Lee will be moved to Kaohsiung. BUTâ??¦.I’m also told by those who should know, there will be no 300 mm 3D instillations till 2011 so commercial 3DIC assembly is unlikely before 2012, if then.

IBM 3D rumors

Last December at the RTI ASIP in Burlingame, IBM confirmed that there was no commercial qualified 3D line running yet. Speculation at the ECTC was that a TSV containing product will be introduced into their server line. Product would come off the R&D line. An announcement will come if performance meets expectations.

TSMC

Recent announcements of their open innovation platform indicates that TSMC is putting the pieces together to enable 3D design [TSMC adds 3D, ESL tp Platform Efforts]. Their design plans will first deal with Si interposers and it will subsequently support full 3D stacking capability. IFTLE conversations with TSMC personnel indicate that their initial roadmap announcements showing vias middle in 2011 was (as PFTLE had predicted) extremely aggressive . They view silicon interposers as a faster solution for their graphics chip customers and will switch them to full 3D stacking later. The fact that long time TSMC partner ASE will not have 300 mm equipment in place till 2011 confirms this conclusion.

3D IC Bonding

There were 10 papers at ECTC dealing with various aspects of Cu-Cu and Cu-Sn-Cu bonding including papers from IMEC, IBM, Leti, Samsung, RTI, Univ Tokyo, Nanyang Univ, / Globalfoundries. As PFTLE noted many years ago, the low COO choice of bonding techology will be limited to choices that result in mechanical and electrical connection at the same time. While the OSATS have been focused on developing Cu/Sn intermetallic technology for 3D strata bonding, there is still significant commercial interest in copper-copper bonding, perhaps due to the lower resistance connections. Cu-Cu bonding comes in white or black i.e. thermocompression or direct bonding. Actually there is enough data out there now that is becoming evident that a continuum exists between the two – shades of grey -which are dependent on the variables of surface finish, temp and pressure. A full blog will be coming up in a few weeks discussing all of this information.

Thin Film Dielectrics

Michael Toepper, Fraunhoffer IZM dielectric expert, discussed thin film polymers to a standing room only crowd and concluded that materials with the highest tensile strength and elongation were best suited for reliable fan in and fan out WLP structures.

Fan out WLP require lower temp curing materials since the chips are embedded in low temperature molding compounds. Most of the practitioners IFTLE is aware of are using JSR ( WPR 5100 series ) which are epoxy novolacs with rubber filler or the new HD Micro low cure temp PBOs ( HD 8900 series ).

The Asahi Glass group (AGC) has focused application work for their ALX polymer on fan in and fan out WLP. This material is in trials at IME, IZM and RTI and looks very promising as a BCB substitute with double the elongation and curing at 190 â??¦C.

[Hijiri Kuriyama, Alan Huffman (RTI), IFTLE, Takeshi Eraguchi ]

Coming up soon:
– Finding the Beef and Addressing 3D IC
– Sematech Addresses 3D Stress
– A Date in Dresden

For all the latest on advanced packaging and 3D IC stay linked to Insights From the Leading Edgeâ??¦â??¦â??¦â??¦â??¦â??¦â??¦..

Like the Phoenix rising from the ashes Perspectives from the Leading Edge, PFTLE, rises from the internet black hole that it was thrust into to become Insights from the Leading Edge, IFTLE. Not much will change except the blog location. IFTLE will try to bring you weekly insight into the technical and business comings and goings in the 3DIC and IC packaging segments of our microelectronics community.

First a little background on what happened. Unbeknownst to me, Reed Elsevier the owner of Semiconductor International, owned a portfolio of magazines with a broad reach of topics. When the board decided to exit the magazine business they decided to simply close down many of them. Thus on April 16th I received a message from "headquarters" thanking me for my activities with them and terminating me and all the rest of the Semiconductor International staff. After a few seconds of shock I contacted Aaron Hand (Editor) and Dave Lammers (News Editor) and received confirmation that, indeed, Semiconductor International was no more.
I quickly tried to get back onto the web site to add some verbiage to let all of you know what had happened and tell you that I would be looking for another site to host PFTLE, but alas, I had been locked off the web page (no hard feelings, I’m sure I would have done the same thing if the situations were reversed). Having worked for a 25+ billion dollar company for most of my career, I had watched many a "big dog" get escorted off the company grounds after being told that they were terminated ….that’s simply the way it is done. Two weeks later and the web site semiconductor.net was closed and links to 3 years worth of my material now pointed into a black hole !

Emails from friends and readers began coming in questioning what was going on and pointing out that their links to my stories and blogs were now pointed no where.

The good news is that while the blogs are legally "work made for hire", my contract allows me a "worldwide, perpetual license to publish , display and distribute the works after 3 months of exclusivity". So I’m in the process of reloading the 128 blogs. By your readership of 7000 – 10,000+ hits per month, I think many of you would agree that these blogs contain a lot of worthwhile information that all of us would like to continue to access.

I will continue to refer back to these in IFTLE, and will give you all the URL to the site as soon as everything is locked down and tested. The plan is to index these so you will be able to access any and all information about a given company or topic from this new web site.

I have decided to join forces with Solid State Technology. Editor Pete Singer, while with Semiconductor International , was actually the person who gave me the opportunity to do all of this back in the summer of 2007. I look forward to working with Pete and his competent staff as IFTLE moves forward.