This year’s IMPAS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. We’ll first take a look at some of those and then look at several key presentations from the conference.

Qualcomm

Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.

Handset thickness continues to be reduced and is now approaching 6mm. Since the battery and the screen are not shrinking chip packaging and the substrate board must make up the difference. Most of these packages are FC and WLP. Bezuk commented that 5 years ago very few of the packages were WLP but now this category accounts for near 50% of the packages IC.

Molded FC die on thin core or coreless substrates are approaching 750um thick and warpage issues are becoming significant.  Warpage is dependent on :

– core thickness, CTE and modulus

– EMC thickness over die

–  die thickness (ratio of Si/EMC).

Solder balls have become a significant fraction of the total package height.

Tighter pitch requirements ( < 140um) have necessitated  a move to copper pillar connections which in turn need thermocompression bonding to overcome warpage/flatness issues in such structures.

Thinner packages require thinner EMC above the die which results in increased warpage and requires EMC with higher mold shrinkage and higher modulus.

Bezuk reports that typical HVM substrate properties in 2014 are as follows:

	Current 2014 HVM
Patterning Method (µm)	SAP (15/15)
Min FC pitch (µm)	40/80
Core material CTYE (ppm)	3
Decouling solution	Embedded caps
Buildup dielectric	Prepreg, ABF

Having reached a core CTE of 3, reduction in substrate core CTE is no longer an option so the industry is turning to develop materials of increased modulus.

Bezuk proposed that the next move (time undefined) will be from today’s FC PoP structures to 2.5/3D moving first to wide IO DRAM on logic and next to logic-on-logic. Although he added that there was no clear infrastructure answer for where interposers will be coming from.

Prismark

Brandon Prior of Prismark continued on the theme of “Mobile packaging and Interconnect trends.” Their analysis of the Apple 5S smartphone confirms the Qualcomm comments about increased use of WLP as can be seen in the fig below.

Despite all the talk about high density laminate technology approaching < 5um L/S, Prior indicated that the Apple 5S was the first device to use 50um L/S and CSPs on a 0.4mm pitch. It is also interesting that caps continue to shrink. 01005 is 0.4 x 0.2 x 0.13mm which is extremely hard to assemble.

The Apple A7 processor is packages in PoP with the memory package being 1Gb of LPDDR3. The substrate has 27um L/S and 150/170um bump pitch. Memory chips are Ag WB which is a lower force assembly process than Cu WB. While these memory chips are still WB, Prismark stated that they expect performance DDR to go FC at the big 3 memory suppliers and expect 5B units shipped by 2018.

Prior showed the following application processor roadmap for phone/tablet low end vs high end products.

Transition to 0.4mm packages

FBGA and WLP are in high volume production at 0,4 and 0.35mm pitch. Wafer CSP moving to 0.3mm and below. Prismark forecasts > 28% of CSP/WLCSP to be 0.4mm or less by 2018.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

The word “lecture” is one of those wonderful English words with multiple meanings. Lecture can mean “a talk or speech given to a group of people to teach them about a particular subject,” but it can also mean “a talk that criticizes someone’s behavior in an angry or serious way.” In IFTLE 185, lecturing means both!

Those of you that are regular followers of IFTLE know that every once-in-awhile, I’ll stop reviewing the latest technology presentations to try to bring home a point. The latter is necessary right now.

Some may call this one of my “rants” but the online dictionary defines a rant as “…an argument fueled by passion and not shaped by facts.”  I can assure you this rant will be shaped by both passion and facts.

What triggered IFTLE 185 was a panel session held at the recent IMAPS Device Packaging Conference in Ft McDowell AZ. A good panel session experts discuss controversial topics but that is not exactly what happened here.  This panel session degraded into a school yard verbal battle (panel members and audience) over what certain terms mean. If you really want to follow the chronology of the discussion you can here [Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel].

It is simply amazing that the assembled group of technical practitioners could not agree on what certain packaging terms mean but….they couldn’t. At first I chose to sit quietly in the audience amused at the miss speak…but then… my good friend Bob Patti, a panel member,  spotted me in the corner of the room and called me out …” Phil what do you think “…it was at that point , no longer able to hold back, that I unleashed my tirade […a long angry speech of scorn and criticism…]

Let me attempt to articulate my position on several of the topics that came up that night …

INTERPOSER – for some reason, be it ignorance, youth or a combination of both, some in the audience continue to believe that the term interposer was invented for 2.5D.

All 1^st level packages are interposers, The purpose of an interposer is to spread a connection to a wider pitch. Interposer comes from the Latin, interpōnere, meaning “to put up between.” A BGA substrate is an interposer ! This is clearly shown in the Infineon slide that they have been showing for nearly 20 years.

SYSTEM-in-PACKAGE – there was mass confusion on what this meant and what is included in this definition. Several experts felt that 2.5/3D were NOT included in the definition of SiP. I think some of these disagreements come from the fact that corporations do not divide things up in their business units based on definitions so all things SiP may not be in the same business unit and this influences their thinking.

In the 1990s multiple chip packages, MCMs as they became known, were sets of chips that were connected on high density Si, laminate or ceramic substrates by WB or C4. In the early 2000’s it became vogue to call these system-in-package as industry focus became delivering functions for portable devices in separate modules. Need more history on MCMs try the Multichip Module Technology Handbook [link] which Iwona Turlik and I edited in 1998.

Let’s look at another Infineon slide, below. Whether its side by side, stacked, through hole or embedded, these multiple chip solutions are all versions or categories of SiP.

2.5D, 2.1D and 5.5D: Please stop the madness!

3D packaging defines the various ways of stacking chips in the z direction whether it be WB them to a common substrate, package-on-package stacking, embedded chip stacking (in laminate or EMC ) or direct connection with TSV.

The term 2.5D is usually credited to ASE’s Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3DIC since the infrastructure and standards were not ready for 3DIC stacking yet.  Tong felt the silicon interposer would get us a major part of the way there, and could be ready sooner than 3DIC technology.  He used the term 2.5D, which immediately caught on with other practitioners. Tong was not trying to create a new nomenclature, he was making a joke that we were not ready for 3D but this silicon interposer with TSV would get us close. He actually got laughs when he called it 2.5D at the RTI ASIP conference fall of 2009.

We are now starting to hear the laminate community use the term 2.1D for high density laminate and some in the silicon interposer community using the term 5.5D  for a 3D memory stack on an interposer. To all this, all I can say is “STOP – Enough-is- enough…it’s no longer funny..”

At one point during Bryan Black’s AMD talk at the conference he said “3D” and the audience interrupted him to ask whether he meant 2.5D. His response was something like “Oh yeah…well they both mean the same thing to me..” meaning we are talking about stacking technology with TSV.  Bryan is correct!

LARGE AREA PROCESSING (LAP)

LAP is being held out as the solution to everything that is not economical these days. FOWLP not low enough cost to break into commodity applications ? …don’t worry we’ll use LAP and the price will come down. Glass interposers not looking like the price will be low enough for mobile products?…don’t worry we can manufacture on LAP lines and the price will come way down.

Certainly our microelectronics educations have taught us that larger usually means cheaper, i.e. chips from 300mm lines ARE cheaper than the same chips from 200mm lines. This is true as long as the equipment and technology is available to give you high yields, i.e. see the current 450mm situation.

My point to the audience was that PCB are made in large panels because they can be…higher density BGA substrates are made in much smaller strips because they have to be!

I actually have hands on experience at what we called LAP back in 1995-1997, as we had a major DARPA contract to try to manufacture MCM substrates  on a sq 400mm format. Check out my chapter “High Density, Large Area Processing (LAP) in the Multichip Module Technology Handbook [link]. By the way our program with MMS and others to manufacture high density MCM substrates made for a great magazine cover (see below)…too bad it didn’t yield!

Do I think that pursuing high density LAP is a worthy R and D goal ?…certainly, lets just not act like it will be easily accomplished.

Other problems with today’s nomenclature?? Let me know …

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE !

 

By Garrou

Let’s take a look at some of the key presentations from the SEMI Summit that took place in January in Grenoble.

Gartner – 3D Market Forecast

Stromberg of Gartner gave a market forecast of greater than 1.5M 300mm wafer equiv per month or 2B units / year of 2.5/3D (non MEMS non CIS) by 2018 but then listed several pages worth of technical issues that could affect the forecast.

Editorial Comment:

In emerging technologies like 2.5/3D  guaging market timing and size is an art, not a science but I’m not sure what numbers like this are worth if you preface them by saying they could be inmpacted by thermal issues, yield issues, design issues and  competitive treats by PoP and  WB devices. Of course all those things are true, but then what kind of confidence do we have in the nubmbers / timing ?  This is true for al lthe marketing houses not just Gartner.

GlobalFoundries

GF has been detailing their imminent commercialization of 2.5/3D IC for several years. Their current status report is shown below.

Their response to Interposer TSV formation, front side routing and backside reveal and RDL  issues are shown below. High IO counts require dense interposer frontside routing (i.e. over 1600 wires for a HBM port.

The GF supply chain for 2.5D productization is shown below:

TSMC

Miekei Leong , VP TSMC, gave the standard TSMC CoWoS pitch but did offer a definition of their supply chain model where OSATS are now integrated as part of the supply chain.

Another interesting roadmap showed TSMC demonstrating HBM (high bandwidth memory) on CoWoS by 4Q 2014.

IMEC – Cost Analysis

Eric Beyne of IMEC presented data on a cost breakdown of their 5 x 50µm TSV full flow 3DIC process (without stacking) showing the TSV middle fabrication process and the thin and backside eveal processing are about equivalent in cost.

They find that a lot of cost is invested in CMP processing which can be improved by reducing the Cu overburden after TSV fill.

This can be compared to the 10 x 100µm TSV costs presented by Ramaswami of Applied Materials shown below:

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

RTI- Architectures for Semiconductor Integration & Packaging (ASIP) is always held in Burlingame, CA at year’s end. It is focused on commercial 3DIC technology and applications and is always a good indicator for the status of the industry.

In the next few blogs we’ll take a look at some key papers from this years conference.

Tezzaron acquires Ziptronix facility outside RTP NC

As we have discussed previously Tezzaron has purchased the former Sematech fabs in Austin and is running the operation as a subsidiary Novati [ see IFTLE 146, “TSMC Apple…Novati” and IFTLE 166 “IEEE 3DIC part 1;….Novati” ]

Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing [link].

In addition Tezzarons Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly. [link]

Tezzaron, known for its fine featured TSV showed the following process status and an interesting X section of a W TSV connected at M5.

Suss and EVG

Suss and EVG examined their processes and equipment available for thin film handling of 2.5 & 3DIC wafers, namely temp bonding and debonding.

They are both working with a number of materials suppliers as shown in the Table below. All of them now supply room temp (RT) debonding solutions

 

Typical thickness requirements for temporary adhesives are dependent on the interface that is being bonded as shown below.

Both Suss and EVG have recently  introduced eximer laser assisted RT debonding which was first introduced by 3M years ago. [ref]

EVG is also touting a laser-initiated debonding process flow.

Brewer has introduced a new UV absorbing release layer which is stable up to 350 ˚C.

Amkor, STATS ChipPAC and ASE to package  Apple A8

DIGITIMES is reporting that Amkor  and STATS ChipPAC will each package  40% of the Apple A8 processor, with the remaining 20% by ASE.[link]

They report that Apple’s A8 chip will be a package-on-package (PoP) SoC solution comprising processors and mobile DRAM in a single package.

(TSMC, which is believed to have landed foundry orders for Apple’s next-generation A8 chip, has reportedly also secured wafer bumping orders for the processor as part of its turnkey solution.  TSMC reportedly will start ramping up production using 20nm process technology for Apple’s A8 chip in the second quarter of 2014.

The recent Semi Industry Strategy Symp (ISS) occurred in Half Moon Bay CA a few weeks ago. In the past this has been a treasure trove of information on how and why the IC industry is making the moves that it does. Let’s take a look at some of the key papers from this conference.

IBM

IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Volumetric scaling will be critical to future performance enablement

– Tightly coupled modules and components

– 3D stacking and interposer integration

Casey examined the current state of interposer substrates and showed the following comparison:

 

 

 

 

 

 

 

 

Linx

Linx consultants looked at “Chemicals and Materials in Semiconductor Devices.” IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores.

 

 

 

 

 

 

 

 

 

 

Linx lists 3DIC among the major 5 challenges for the IC industry in the future.

 

Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base.

IMEC

An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm.” She offered the following roadmaps for 3D applications and TSV dimensions.

And the following CoO Analysis for their  3D process flow.

IHS

IHS examined semiconductors in the electronics value chain.  An unexpected piece of data is that consumers are spending more on hardware (HW) than content i.e.:

IBS

Our friends at Int. Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. They expect Capex decreases in 2014 (small decline)  and 2015 (large decline).

While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ½ semi sales will come from 32nm and below.

They also conclude that low power and low cost will dominate the application space for 32nm or less devices.

They continue to predict that cost/gate will no longer be a cost driver.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…