By Dr. Phil Garrou, Contributing Editor

The IMAPS Device Packaging Conference was once again held in March in Arizona. Here is a look at some of the more interesting papers from the conference.

AMKOR – 2.5/3D Readiness

In Amkor’s presentation on 2.5/3D readiness, the following slide showing product qualifications was of special interest.

2.5D & 3D product qualification data is shown below:

GlobalFoundries TSV Readiness

GlobalFoundries TSV technology is qualified and ready for HVM ramp for all <28nm nodes Fab 8. Std TSV size is typically 5 x 55um.

Thermo-compression bonding is used for assembly.

• First, thin TSV die bonded chip to substrate (CoS) using non conductive paste (NCP)
• Top dies then bonded chip to chip (CoC) during 2nd bond on top of first stack
• TC-NCP process is used to minimize stress on ULK layers during cool down

Warpage characterization is critical during design and reliability phase of development along with production yield improvement.

• 3 different backside passivation layers were assessed in terms of impact of film stress on warpage
• Backside passivation film stress does not play a big role in overall package warpage
• Top Die Thickness impact on warpage
• Package level warpage in the order of 125um was measured at peak temperature for 100um thin top die
• With 260um thick top die package warpage was reduced to 80um at peak temperature
• Packages with 100um top die and thus increased stress / warpage clearly showed cracks appearing in the Cu pillar joints. Thus higher warpage clearly leads to degraded electrical performance of copper pillars in the corners of the package

CEA Leti

While most of us were focused on 3D stacking of memory chips, CEA Leti was studying the stacking of capacitor chips. Using the PICS capacitor technology of IPDIA, Leti demonstrated that a smaller thin film cap footprint could be achieved if silicon caps are stacked and connected in parallel.

Several attacking technologies are proposed including TSV and more traditional WB.

Various packaging solutions are presented including a molded version (shown below) but IFTLE strongly disagrees the inference that such packages can withstand near 400C since IFTLE has expressed many times that thermal stability needs t be determined from isothermal TGAs NOT ramp TGAs like the one show. Ramp TGAs tend to highly exaggerate the thermal stability of the samples in question, for instance epoxy mold compounds are NOT stable at anywhere near 400C.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The Taipei Times headline on April 18^th read “New packaging may spur TSMC growth” adding that despite its weak revenue growth guidance for this quarter, TSMC, might see stronger growth from next quarter thanks to its InFO (integrated fan out) packaging technology [link].

The Times reports that InFO could help TSMC beat rival Samsung and win more A10 application processor orders from Apple, because the technology offers “…lower costs, higher speed and thinner form factor when compared to conventional flip chip packaging”. TSMC is preparing a complete InFO portfolio aimed at different package sizes and applications. In a conference call with investors on last week, TSMC CEO C.C. Wei stated that they have almost completed equipment installation and expect to complete customer product qualification shortly. They plan to ship volume production shortly. Estimates are that the revenue contribution from InFO packaging could total US$300 million this year.

IFTLE has previously reported that TSMC had purchased a facility in Longtan, Taiwan (from Qualcomm for $85MM) and was turning it into a facility devoted to the manufacturing of integrated fan-out wafer-level packaging (InFO-WLP) technology. [see IFTLE 219 “TSMC INFO factory…” [link]

Apple is expected to unveil its new iPhone in the second half of this year. Daiwa Capital Markets analysts estimates that Apple’s order split for A9 processors (last generation) was 45% for TSMC and 55% for Samsung, but projects TSMC could take more than 50% of the A10 processor business, due in part to the superior packaging technology now being offered by TSMC. Other smartphone chip vendors are reportedly looking at adopting TSMC InFO packaging technology in the near future.

IFTLE has reported previously that TSMC lost the chance for making Apple A3 processors to Samsung because it lacked the capability to package and test the chips [link].

YSIC (Yuanta Securities Investment Consulting) claims the InFO technology is at least 20 percent cheaper than flip chip packaging. YSIC notes that “… it is becoming more difficult to solely rely on front-end tech node migration to drive better performance and cost” , a statement that should be very familiar to readers of IFTLE.

In 2014, IFTLE discussed TSMCs announced ambition of becoming a major player in full back-end packaging services with their plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 [ See IFTLE 190 “TSMC Focus on Packaging….”] [link] . Based on this roadmap, TSMC would become the 3rd leading packaging company in Taiwan by 2016, trailing only ASE and SPIL.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Wide band gap semiconductors are extremely attractive for power electronics applications. GaN is a binary III-V wide-band gap ( 3.4 eV) material. Since GaN transistors can operate at much higher temperatures and work at much higher voltages than gallium arsenide (GaAs) transistors, they make ideal power amplifiers at microwave frequencies.

GaN has shown to have applications in optoelectronic, high-power and high-frequency devices. Because GaN offers very high breakdown voltages, high electron mobility, and saturation velocity it is also an ideal candidate for high-power and high-temperature microwave applications like RF power amplifiers at microwave frequencies and high-voltage switching devices for power grids.

GaN devices target both military (ship-board, airborne and ground Radars and high performance space electronics) and commercial applications ( base station transmitters, C-band Satcom, Ku-K band VSAT and broadband satellites, LMDS and digital radio).

There are basically two manufacturing (growth) processes, based on either Silicon or Silicon-Carbide substrates. GaN-on-Si has a significant cost advantage that is driving down the cost curve.

Initially, it seemed GaN-based devices would be affordable only for military applications, such as the development of electronic warfare, radar, and high security communications systems. However, material maturity, improvement in yield, expansion to 4” wafers and lower-cost silicon growth process has reduced GaN-based device costs and therefore an economical option for commercial applications as well.

Growth of the GaN device market has required the development of novel packaging solutions. Since GaN HEMTs are thermally limited significantly below the electrical capability of the devices. The challenge of a GaN HEMT is its heat flux at the gate fingers, which cannot be effectively addressed by conventional packaging and thermal management systems.

The DARPA ICECool program is developing liquid cooling solution for such hot GaN devices. [see IFTLE 119, “ICECool putsThermal Issues Back in Focus”.]

Non liquid cooling solutions are also under development at facilities such as HRL (Hughes Research Labs). While thermal heat spreaders are usually limited by the TIM (thermal interface materials ) used to attach them, The HRL solutions electroplate the heat sink right on the back side of the GaN device or module. For instance see the process sequence below, developed by Herrault and co-workers at the HRL Labs in Malibu CA.

First, GaN dice are temporarily bonded face down onto a carrier wafer using a temporary adhesive layer. The silicon body wafer, which consists of through-wafer cavities, is also bonded face down onto the carrier wafer, as depicted in the figure (a). Next, a Ti/Au seed layer is sputtered over the wafer, and copper is electroplated and subsequently polished down to the surface of the silicon wafer as shown in (b). This step forms the integrated thermal heat spreader. Therefore, there is intimate contact between the high-thermal-conductivity heat spreader and the high-power-density GaN device, which is beneficial for high-performance thermal management. The silicon body wafer was used as a polishing barrier for the copper removal, enabling a flat and smooth backside for additional processing steps. The combination of use of a silicon body wafer, electroplating and chemical mechanical planarization (CMP) process eliminates the need for a bonding layer between the chip and the heat spreader, and therefore reduces the overall thermal resistance from junction to baseplate.

The body wafer with copper-embedded GaN dice is then released from the carrier wafer. Front-side electroplated gold connectors and bond pads are then fabricated using standard microfabrication technologies. The silicon cap with TSV allows connections to the outside of the module.

The technology is compatible with integration of multiple chips (GaN, CMOS, SiGe) from different semiconductor technologies and with different thicknesses since the chip thicknesses are absorbed by the plated copper which is subsequently CMP’ed.

Compared to conventionally mounted GaN power amplifiers (PA) using AuSn solder, an electroformed (called ITAP) X-band PA showed 1.4x improvement in CW Pout (4.4W at 8 GHz) while the ITAP Ku-band showed 1.3x improvement in CW Pout (4W at 12 GHz). Compared to silver epoxy mounted PAs the improvement was 2x and 1.5x, respectively.

The figure below plots Junction temperature vs. dissipated power density using gate resistance test structures. The electroplated heat sinks (ITAP 1 & 2) increase the power handling by 1.45x (for Tj of 150°C) or reduce Tj by 40°C (at 2W/mm dissipated power density).

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The Taipei Times is reporting that the Taiwan Fair Trade Commission has suspended its review of ASE’s bid to take over SPIL (link). ASE’s prior acquisition of a 25% stake in SPIL has raised anti-trust concerns and fears that the merger would undermine competition in the market.

The decision means a victory for SPIL who has fought the acquisition. SPIL, which has repeatedly urged the commission to terminate the review of the acquisition welcomed the FTC’s decision.

ASE released a statement saying it will continue with our plan to acquire 100 percent equity interest in SPIL through all legally permissible means and avenues.” ASE will be able to continue raising its ownership in SPIL through open market purchases including intra-day trading, block trades, and acquisition of SPIL’s Nasdaq-listed American depositary receipts. If ASE’s stake in SPIL exceeds the 33% threshold, ASE will need to apply to Taiwan’s Fair Trade Commission (FTC) to merge with SPIL.

Intel Admits Moore’s Law Coming to an End…Predict What Might be Next

The recent issue of MIT technology review noted that “Intel will slow the pace at which it rolls out new chip-making technology, and is searching for the appropriate successor to silicon transistors.” (link)

They note that Intel in their 2015 10K report last month disclosed that it is slowing the timing at which it moves to the next scaling node. Intel has already pushed back the debut of its first 10nm chips from the end of this year to sometime in 2017 noting that it can’t keep up the pace it used to.

We all know it is becoming more difficult to shrink features further in a cost-effective manner, but this doesn’t mean that future devices will stop improving. Intel says that in the future, it will make improvements to the way chips are designed. They add that for many important new applications such as wearable devices and medical implants, chips are already powerful enough and power consumption is more important.

William Holt, who leads the company’s technology and manufacturing group, speaking at the International Solid State Circuits Conference said that for chips to keep improving, Intel will soon have to start using fundamentally new technologies in about four years. While Intel has not yet announced silicon’s successor, most technologists feel that the two leading candidates are spintronics and tunneling transistors.

Neither of these technologies offer increases in computing power and neither are ready for volume manufacturing. Both would require major changes in how chips are designed and manufactured. While neither offer speed benefits over silicon transistors, the new technologies would, improve energy efficiency something important for many leading uses of computing today, such as cloud computing, mobile devices, and robotics. Future chips connect to household, commercial, and industrial objects and thus will need to be as energy efficient as possible.

Sine packaging experts need to be aware of what’s going on in the front end lets take a look at these technologies.

SPINTRONICS

Conventional electronic devices rely on the transport of electrical charge carriers – electrons – in a semiconductor such as silicon. Spintronics or “spin transport electronics”( also known as magnetoelectronics), depends on the intrinsic spin of electrons and the associated magnetic moment, in addition to its fundamental electronic charge, in solid-state devices. Devices follow the simple sequence:

1 – information is stored (written) into spins as a particular spin orientation (up or down),

2 – the spins, being attached to mobile electrons, carry the information along a wire, and

3- the information is read at a terminal.

Spin orientation of conduction electrons survives for a relatively long time which makes spintronic devices particularly attractive for memory storage and magnetic sensors applications, and, potentially for quantum computing [link].

Tunneling FET

The basic TFET structure is similar to a MOSFET except that the source and drain terminals of a TFET are doped of opposite type. A common TFET device structure consists of a P-I-N (junction, in which the electrostatic potential of the intrinsic region is controlled by a gate terminal. The device is operated by applying gate bias so that electron accumulation occurs in the intrinsic region. At sufficient gate bias, tunneling occurs when the conduction band of the intrinsic region aligns with the valence band of the P region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region and current can flow across the device. As the gate bias is reduced, the bands becomes misaligned and current can no longer flow.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…