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For all the latest in 3DIC and advanced packaging stay linked to IFTLE…………….
(Click on any of the images below to enlarge them)
For all the latest in 3DIC and advanced packaging stay linked to IFTLE…………….
Minimizing energy consumption is a performance goal of all of today’s devices including microprocessors. Dynamic voltage and frequency scaling (DVFS) is a technique for performing “on-the-fly” energy-use optimization. Implementation of DVFS requires voltage regulators that can provide independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs).
Inductors are fabricated on the silicon interposer in an elongated spiral with a Ni-Fe magnetic core encasing the copper windings on the long axis. “The Ni-Fe is deposited under a magnetic biasing field so that the hard axis of magnetization forms along the width of the core as shown in the figure. Inverse coupling between adjacent inductors, is utilized to avoid magnetic saturation of the core.” The inductor fabrication involves successive electroplating deposition of the bottom magnetic core, copper windings, and top magnetic core. The windings are electrically isolated from the bottom magnetic core with a layer of silicon nitride, and from the top core with ”hard baked photoresist”.
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There have been rumors out there that IBM would be applying with their 3D technology in their upcoming Power7 devices. Their presentation at ISSCC may be the first look that we are getting at their early designs for processors stacked with cache memory using TSV technology.
Standard design methodologies with some 3D extensions were used to design each stratum. TSV locations for power and clock were pre-defined to match a regular grid. Some sites were de-populated to accommodate the eDRAM blocks.
3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5 x 5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density
In general, commercial DRAM shows large process variation from chip to chip, which causes address access time variation (tAC). In order to reduce the tAC variation, most high speed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption.
Hynix in their paper entitled “A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for Through-Silicon Via (TSV) Interface explains that this can be an even larger problem for stacked memory die. “For TSV-based stacked dies, large tAC variation results in higher power consumption due to short circuit current from data conflicts among shared IOs”. Since the number of IO might be 512 or more for wide IO DRAM, the additional power consumption can be very high. While it is desirable in mobile DRAM to exclude the DLL because of the power cost , TSV stacked DRAM for high-speed operation partially adopts a DLL in the master die (driver circuitry) . The DLL-based data self-aligner (DBDA) described by Hynix reportedly reduces the data conflict time among stacked dies, consuming 283.2µW during read operation at 800Mb/s/pin. It dissipates 4.98µW in self-refresh mode with the help of leakage-current-reduction controller.
TI’s Mark Gerber, a key player in bringing up their Cu pillar technology at Amkor addressed 3D packaging technology for next generation devices. Mark broke out current FC interconnect technologies into the following 4 categories indicating that fine pitch gold stud bumping was confined mainly to Japan.
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Sung-Il Cho of Samsung’s test and package center looked at Samsung’s Packaging Roadmap. He offered the following categorization for their DRAM, Flash and system LSI chips…
…and the following roadmap for flash technology development for solid state drives. Consistent with their corporate policy of holding new technology information "close to the vest" their inputs on 3D packaging with TSV were either ITRS roadmap slides or Yole roadmaps that have been published on these IFTLE pages before.
Keiichirou Kata of Renesas Advanced Package Development Dept. addresses their packaging roadmaps. He sees the major developing areas as FC BGAs, WLP and what he calls 3D Jisso (3D IC integration). Their FC technology roadmap is driven by desire for tighter pitches.
28 nm node chips will see a move to 108 um pitch and copper pillar bumps by the end of 2012.
Their proposed fan out WLP is an RDL first technology which they contend eliminates the issues of chip movement due to mold compound shrinkage.
They are moving to wide IO DRAM standards for low power DDR3 and beyond.
Ryoji Matsushima from Toshiba’s Memory Packaging Engineering Dept. discussed equipment materials and processing issues for thin memory packages. High memory capacity, high memory access speed and thinner packages all point towards memory stacking with TSV.
Technical issues with thin packages are shown on the slide below.
In Memorium: Jackki Morris Joyner
This past week I was attending the IMAPS Device Packaging Conference in Ft McDowell AZ (coverage coming in a few weeks). Those of you who are long time readers of IFTLE know I am there every year and strongly support this IMAPS conference. In the end, what separates societies is people not content. Part of what makes IMAPS great to work with has been Jackki Morris, or as we knew her post marriage Jackie Morris Joyner. When she first told us of the impending marriage and that she was becoming Jackki Joyner we all teased her asking her to run around the buildng for us ( for our non US friends this is the name of a famous US Olympic runner) and she laughed along with us. Jackki was the kind of person who made your life better for having talked to her on the phone or corresponded by email. Everyone asks "how’s it going" but she meant it. She genuinely cared about people… you just could tell.
The last time I talked with Jackki she was working the IMAPS table with her husband Cliff Monday night. When she saw me she gave me a hug and she turned on her computer and showed me pictures I had sent her of my grandaughters a few years ago. She had pages and pages of pictures of all the friends she had made through IMAPS because she just was that way. We shared funny stories of past conferences and laughed before I let her get back to work.
The next morning she was noticeably missing and Exec Dir Michael O’Donoghue revealed to several of us that Jackki had become quite ill during the night. By the time she made the hospital her heart had stopped several times and she was in intensive care with Cliff by her side. This cast a pall over the rest of the meeting and she remained in intensive are as we all left the meeting to go home. By the time I arrived home Friday she had passed away. The world is truly worse off today because this caring, loving person is gone.
Our prayers are with Cliff and her family
Anybody here seen my old friend Jackki
Can you tell me where she’s gone
She cared and shared with a lot of people
But it seems the good they die young
I just turned around and she’s gone
Copper Protrusion
In the last several years PFTLE and IFTLE have brought copper protrusion to the forefront as an issue [see "Researchers Strive for Copper TSV Reliability" Semi Int, 12/03/2009] and reported on technical solutions as they appeared from IMEC [see IFTLE 6 "Cu-Cu and IMC Bonding Studies at 2010 ECTC…"]; TSMC [see IFTLE 34, "3DIC at the 2010 IEDM"] and others. IME has now reported on their study of 5 um x 50 um Cu TSV as they were annealed from 250 to 450C.
Cu expands vertically because it is constrained by the surrounding silicon substrate. Because it expands plastically it does not return to its original length when the sample is cooled down.
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The effects of anneal temp, anneal time, via diameter and via depth are shown below where "room temp" refers to the protrusion present after anneal and return to room temperature and high temp refers to protrusion after anneal while still at the elevated temperature. As with previous studies they found that CMP after anneal retards any further protrusion if the temperature is again elevated.
Bottom line is that protrusion is minimized by small diameter, low aspect ratio TSV.
Samsung System LSI Division has also looked at the Cu protrusion issue and report similar results i.e that Cu protrusion can be reduced by heat treatment before CMP and that Cu protrusion and delamination strongly depend on TSV dimensions.
When the via diameter was in zone A all the vias showed high Cu extrusion and via delamination, but TSV diameters from zone B showed no problems.
Micro-cracking caused by Lateral Extrusion
Conference Chair Koyanagi and co-workers at Tohoku Univ also examined TSV dimensions and the effect of high temp annealing. An array of Cu TSV with diameters ranging from 3 to 30 um at three different pitches were annealed from 200 to 400C. Both the lateral and vertical protrusion of the copper was monitored.
Again larger diameter TSV (at a constant depth) show higher extrusion, but also that lateral extrusion (extrusion in the x-y after Cu has protruded from the surface) increased with anneal temp. For example 5 um TSV on a 10 um pitch extrude laterally 2 um at 400C. This would put them within 1 um of touching! Stresses induced by the TSV also result in microcracking "…on the periphery of the TSV array and in between the TSV." Careful choice of TSV size and pitch is recommended.
Cu-Cu Direct Bonding
Copper-copper direct bonding continues to be a popular topic due to the promise of fine pitch, low resistance interconnect which are more mechanically reliable than IMC bonding (Cu-Sn-Cu) and should show less electromigration issues. Such processes are currently limited by the required bonding time / temperature which are usually reported as 30 min / 350-400C. The holy grail appears to be a thin die Cu-Cu thermo compression bonding process which requires low bonding temp and pressure.
IMEC and TSMC have studied the direct Cu-Cu bonding of 5 x 40 um TSV with (3) different configurations ; (1) no nail head exposed (Cu CMP’d flat with the oxide surface; (2) flat nail head (cu CMP’d flat and then oxide recessed and (3) natural nail head (stop grind short of the nail head, pull back oxide revealing "dome" shaped copper protrusion. The matching landing pad is a Cu surface CMP’d flat with the oxide surface. After bonding they observed that the "no nail head exposed" and the "flat nail head" sample s delaminated even when the bonding temp and or the pressure was increased. They assumed failure was due to the low % area that is actually used to bond (less than 1%). So, what is good for the design (less than 1% of the area occupied by TSV) is not good for the strength of bonding. The dome bonding was better due to its ability to deform. IFTLE interprets this as an ability of the domed structured to deform allowing shorter TSV to now touch their pads and bond. IFTLE also thinks this is a good reason to look at hybrid bonding schemes such as proposed by Ziptronix [see PFTLE 48, "Opening the Kimono, Ziptronix gives details on DBI Process"] and CEA Leti [see PFTLE 103, "Show me the Copper"]
Stacking of Ultrathin Die
Standard 3DIC thickness has focused around 50 um for the last few years. IMEC has now shared their results of ultrathin (25 um) die stacking.
After temporary bonding and grinding, oxide is pulled back for Cu TSV reveal. The revealed "nail heads" are passivated with 3 um BCB and reconfigured with Cu/BCB RDL. Cu/Sn bumps are then fabricated on the landing pads. The 25um thick die are diced while still bonded to the carrier. They note that "this is required to have enough mechanical support during stacking"
Both NUF and WUF were looked at for underfill solutions. NUF is unfilled polymer dispensed onto the landing die prior to bonding and WUF is filled underfill film laminated to the thinned wafer while still on the carrier.
Issues with NUF were: (1) underfill trapped between the bumps;(2) voids between top and bottom die and (3) induced topography due to underfill shrinkage on cure. Shrinkage of the underfill upon curing and the CTE difference between a microbump and the underfill cause a bending of the die over the ubump connection. For an unfilled underfill and a 25um thick die a 40% increase in the drain current was observed to occur.
After several failed tries, they decided to focus on WUF with 60% filler loading. WUF was vacuum laminated onto the die and gave much better topography and the use of a filled underfill resulted in reduced stress.
They also found that increase in the die thickness from 25 to 50 um resulted in a stress reduction of 3X. Final conclusions were that 50 um thickness die were currently much better option for scalable manufacturable process and that reduction in the TSV diameter from 5 to 3 um will reduce the required KOZ by 64%.
Wireless Product with Design Partitioning
ST Micro and CEA Leti described their program to partition the digital and analog functions of a HD video transmitter onto separate die and stack them using Cu TSV and ubumps.
TSV are 10 um with a 40 um pitch and wafers are 80 um thick. Cu pillar interconnect are 25 um dia and 30 um high. Reliability tests were done at package level using JEDEC level 3. No delamination and no electrical failures were obtained after 1000 cycles.
————–The next IEEE 3DIC Conference will be held in the fall of 2013 in San Francisco————–
Coming up in IFTLE :
-advanced packaging from InterNepcon Japan
-3D as the ISSCC
-detailed coverage on the IMAPS Device Packaging Conference and more
For all the latest in 3D IC and advanced packaging stay linked to IFTLE……………………….