By Dr. Phil Garrou, Contributing Editor

Conference Consolidation under IMAPS

Recently, consolidation has hit the conference circuit, much the same as it has hit the corporate world. The 2016 IMAPS Polymers Conference which we will discuss below focuses, as you might imagine, on the use of polymers in microelectronics. It has been a biennial conference sponsored 15X by DuPont and was held in Wilmington DE. It was acquired by IMAPS and for now continues to operate at the Wilmington location.

IMAPS has also acquired the RTI 3D ASIP Conference. As you may know, 3DASIP is the longest running 2.5 / 3DIC conference focused on commercialization and infrastructure. The IMAPS supported 2016 meeting will be held December 13-15th, at the Marriott San Francisco Airport Hotel in Burlingame, Ca. As in years past, all presentations will be invited.

Continuing in the technical direction that was started last year, 3D ASIP will grow its focus on not only 2.5 and 3D IC, but other competitive high density packaging technologies that are being developed. With the ending of the Ga Tech interposer conference they have asked Corning to join the polymer conference and provide a session on the status of this technology.

The US Technical Chair will be Alan Huffman from RTI, the European Chair will be Mark Scannell of Leti and the Asia Chair will be Mitsu Koyanagi of Tohoku Univ.

There will be two AM tutorials, plenary presentations to start off each day and (8) sessions structured and developed by 8 “topic leaders” who will develop their 3 or 4 paper sessions and serve as session chairs.

IMAPS 17^th Symp on Polymers for Microelectronics.

Continuing in the Winterhaven DE site that has held these meeting for many hears, the conference was spearheaded by a 6 person steering committee and a 6 person advisory board.

Yole Developpement

Amandine Pizzagalli of Yole gave a nice presentation on the use of polymers in advanced packaging platforms. The following generic packaging slide first breaks down technology options into leadframe packages vs substrate based and non substrate based packages etc. Another conclusion from this slide which John Hunt made in a later talk was that ALL packages are fan out except wafer level packages.

Their wafer count forecast shows that while fan out shows the strongest growth rate, FC based packaging is responsible for > 75% of all adv packaging wafer count through 2020.

Yole’s 2015 marketing study shows that PI accounts for ~ 63% of dielectric usage in advanced packaging.

ASE – Fan Out Packaging

In the fanout panel packaging session John Hunt of ASE made the point that while fan out today has taken the connotation of “eWLB” packaging, it truly has been around forever since all packaging except wafer level is fan out including all leadframe and substrate packaging. He showed the following chart for ASE fan out package offerings ad noted that ASE like many others were focusing on panel level processing to attempt to cut costs.

 

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

SMIC Ups Ownership in JCET

Following the lead of global foundry leader TSMC, SMIC, in two separate moves has put an additional $0.5B into JCET (Jiangsu Changjiang Electronics Technology), mainland China’s largest semiconductor packaging assembly and test business, uping their ownership position to $14.25% and making it the biggest shareholder in JCET. [link].

SMIC used a straight cash investment and it’s subsidiary SilTech Shanghai which agreed to sell to JCET its 19.61 per cent equity interest in semiconductor packaging and test services company Stats ChipPac in exchange for JCET shares. SilTech, JCET and the China IC Industry Investment Fund jointly acquired Stats ChipPac in 2014.

With TSMC and SMIC moving into packaging (as IFTLE has predicted for years) it will be interesting to watch for the response from GlobalFoundries and or UMC.

Continuing our look at the IMAPS Device packaging Workshop

ASE – SiP

Bill Chen’s plenary presentation on SiP contained a nice section on WLP (or WLCSP as it used to be called). IFTLE has recently pointed out that WLP should end up being a very important package for IoT which need very small forma factor and very low cost. [ see IFTLE 268 IMAPS 2015 Part 1: A Comeback for WLP in IoT]

I admit to being very partial to the WLP package since I spent many years in the 1990s working with FCT and Unitive as they created the package and made it an industry standard.

Chen points out that the WLCSP of the 1990s paved the way for may other WL packages as shown below.

Based on Yole data, Chen estimates that todays leading edge smart phones contain ~ 35% WLCSP.

As technology developed to apply WLP to larger and larger die more applications came into reach and more I/O ae available at the same pitch as shown below.

IPDIA

Bunel of IPDIA discussed their “Low profile flip-type or embedded Silicon Capacitors in high speed decoupling and broadband filtering”. Communication applications are requiring compact capacitors with large capacitance and low impedance.

IPDIA silicon capacitor technology is based on the structure shown below which can be built in thin film technology with very low profile.

It is compared to a std MCC (multilayer ceramic) cap below.

The silicon caps are thinner and have a smaller footprint than standard MLCC caps.

The main take away of this paper is that the insertion loss at frequencies above 15GHz is dependent on the environment and the mounting parameters. The comparison between the Silicon capacitor and the MLCC shows that on top of the performances required for the UWBB capacitors, the Silicon capacitors offer a combined solution of low profile, high capacitance and low ESR/ESL to meet the requirements in decoupling applications.

Amkor

Amkor discussed sputtered copper vs metal can shielding for cell phone components. They contend sputtering is a lower cost smaller footprint solution.

 

The process flow is shown below.

 

Excellent shielding effectiveness is achieved, mostly above 30 dB, up to12 GHz for far field and up to 6 GHz for near field, and low frequency from10 MHz-100 MHz. Amkor recommends 3 μm sputtering copper solution for best shielding performance and lowest cost.

Hope to see a lot of you in a few week at the ECTC conference in Las Vegas.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

IME Forum

In late March IME held an industry forum in Singapore to discuss “High Density WLFO WLP for next gen mobile 2.5D/5G Systems” Of special interest was their process flow for PoP package constructed from a FOWLP as shown below. This is a chips last FOWLP assembly with access to the top surface by TMV (through mold vias) and subsequent formation of stacked memory as the upper PoP level.

Continuing our look at the 2016 IMAPS Device Packaging Workshop

IMEC – Assembly and Packaging Challenges for 2.5/3D

IMEC addressed assembly and packaging challenges for 2.5/3D. One the main changes we will see moving from 50um to 10um micro bump pitch will be the move from solder ball reflow to thermo-compression bonding.

This will require the use of pre applied underfill to insure:

• Mechanical connection (adhesion)
• Protection of joints and chips during operation

Two types of pre-applied underfill are available:

• No-flow underfill (NUF) – dispensed on bottom die
• Wafer-level underfill (WLUF) – applied on top wafer

If the TCB is done to quickly, heavy voiding results. A comparison of NUF and WLUF (which IFTLE sometimes calls WUF) is given below.

The process flows for NUF and WUF are compared below.

Amkor moves SWIFT and SLIM into Mass Production

Anyone questioning whether Amkor would move their high density TSV-less packaging technologies SWIFT and SLIM into HVM should question no more following their announcement that they have teamed with Cadence and will be releasing PDK for these technologies.[link]

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

For those of you who haven’t seen the latest IC Insights list of 2015 foundry players, I have reprinted it below. TSMC is the leader with $26.4 billion in sales. TSMC sales were over 5x that of # 2 ranked GlobalFoundries (even with the addition of IBM’s chip business in the second half of 2015) and ~12x the sales of # 5 SMIC.  There are now only two IDM foundries in the ranking namely Samsung and Fujitsu. Without Apple, TSMC’s foundry sales would have declined by 2% last year and without the addition of IBM’s sales in the second half of last year, GlobalFoundries’ sales would also have declined by 2% in 2015. The top 13 players now account for 93%of all foundry sales. As everyone now understands, more consolidation is to come….get ready for it.

Continuing our look at presentations form the 2016 IMAPS Device Packaging Conference

In the IMAPS Global Business Council session, Bill McClean of IC Insights updated the attendees on recent IC trends including recent moves by Chinese entities to acquire a position in the global IC Industry. [ see IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card ]

In addition to the list below, he lists the following as rumored full or partial acquisition targets by Chinese entities: AMD, GlobalFoundries, MediaTek, Micron, Qualcomm, Renesas, SK Hynix, SPIL, TSMC and Toshiba.

 

JECT (STATSChipPAC)

The STATS presentation on SiP contained the following interesting slide depicting technologies vs applications overlaid on required L/S.

K&S

Strothman of K&S gave a presentations covering process options for low cost thermo-compression bonding (TCB). Stacked memory products are the highest volume products assembled today using TCB.

• Micron HMC assembled on laminate with C2S (chip to substrate)TC bonders
• Hynix HBM assembled on interposers using C2W (chip to wafer) bonders

Process options are shown below:

The cost of TCB becomes competitive with mass reflow bonding at high UPH.

 

Thus the question becomes how to achieve high UPH. Two key approaches can improve process UPH

• Reduce temperature excursions for the bond head
  • Enable higher die transfer temperature
    • TC-CUF flux dip requires lower bondhead temp
    • TC-NCF needs lower transfer temp to prevent film damage
  • Hot touch down for TC-CUF
• Remove sequential process steps
  • Flux dip process for each die adds time

KNS reports an optimized process through reduced temperature range and higher die transfer temp resulting in TC-NCF process at 2000 UPH and TC-CUF process at 2500 UPH significantly reducing overall costs.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…