By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the 2015 3D ASIP, conference we’ll look at the presentations from some of the memory suppliers and users.

Toshiba

Higashi form Toshiba discussed TSV technology for NAND flash. IFTLE did not take this to be a product announcement, but rather a technology status report.

We are all aware that flash faced major obstacles continuing normal scaling so it recently moved to monolithic stacking. NAND scaling will stop its planar 2D approach at 10 nm. All market players have developed 3D NAND technologies where the memory cells are now vertically aligned. There are many competitive monolithic transistor stacking technologies reported as shown below.

Higashi proposes that TSV flash will be required to achieve the high performance ( low latency and IOPS/W ) and low power required for performance SSD.

 

23Gb and 256Gb prototype chip stack is shown below.

At the 2015 Flash Memory Summit, they showed a prototype SSD using this TSV based NAND.

It was proposed that the first application may be data center servers.

Micron

During Tom Gregorich of Micron’s discussion on “Challenges in the Development and Deployment of Ultra High‐Performance 3Di DRAM Systems,” he noted that the ASIC to DRAM interface s what controls the bandwidth and power usage. The Micron HMC uses SERDES interface which is great for performance but in order to make it in consumer products they will need a new interface type to drop pricing.

AMD / Hynix

3D ASIP supporters Bryan Black of AMD and Minh Suh of Hynix updated the 3D ASIP audience on the status of Hynix HBM memory stacks and the status of the first graphics product to hit the market with TSV stacked HBM memory, the Radeon R9 Fury Series GPUs.

The interposer is made by UMC in the 300mm Fab 12 foundry (UMC) in Singapore. UMC is reported to have entered into volume production very recently (July 2015).

Hynix compared current HBM1 to the soon to be released HBM2 in the following slide.

 

The feel that the new generations of HBM will expand their use into more market segments.

 

Tezzaron

The Patti architecture and manufacturing process are quite different from the 3 main DRAM suppliers. In terms of architecture he separates not only the control functions but also has a separate layer for the I/O. This allows them to deliver “the right I/O for every need.”

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 3D ASIP conference, one of the themes of this years conference was the coming of age of 3D stacked memory which now comes in several flavors from several vendors. This week, we’ll look at the Yole review and next week finish off with a look at the presentations by Toshiba, Hynix, Micron, AMD and Tezzaron.

Yole

In the plenary presentation, Thibault Buisson of Yole spoke on the “Comparison of new Memory Architecture -3D TSV Memory Packaging trends!” Some of the recent product and technology announcements are shown below. After MEMS and CIS, stacked Memory has become the next segment to see adoption of TSV technology. Graphics has been the first application using 3D stacked memories.

All of the major memory suppliers ow have TSV based memory stacked products.

Yole estimates that the SK Hynix HBM stack price with an assumption of 50% gross margin will range from $12.68 to $18.01 per stack.

They further conjecture that the AMD Radeon pricing rages from $191 to $258 with the GPU dies represening 43% of the component cost; the (4) HBM stack representing 28% , the silicon interposer representing 14% and the package subsrate 12%

Toshiba has announced the world’s first NAND flash memory packages integrating (16) 128 Gb NAND memory devices connected together using TSV. The multi-layer chips feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50% less energy on write operations, read operations, and I/O data transfers than Toshiba’s current memory products. (see more below)

The stacked memory supply chain is also clarifying.

1. The HBM stack (memory dies, logic die) is made by Memory Manufacturer
2. The GPU die is manufactured by wafer foundry
3. The interposer is also manufactured by wafer foundry (could be a different one compare to GPU)
4. The PCB package substrate is made by a substrate manufacturer
5. The final assembly (HBM, GPU, interposer, interposer on PCB, passives assembly and BGA balls) is performed by an OSAT.

X-sect comparison of Hynix HBM to Samsung stacked DDR4 is shown below.

On the Passing of Moore’s Law

Every once in awhile you find an article and say “this is great, this is exactly as I would have written it”

I recently found such an article on the passing of Moore’s Law …or…as the author Peter Bright states it

“…Moore’s Law has passed away at the age of 51 after an extended illness” [link]

I hate to take up space just quoting him, but as I said I couldn’t have written it any better, so…

“In the 2000s, it [became] clear that … geometric scaling was at an end, but various technical measures were devised to keep up the pace of Moore’s law…. At 90nm, strained silicon was introduced; at 45nm, new materials to increase the capacitance of each transistor layered on the silicon were introduced. At 22nm, tri-gate transistors maintained the scaling.

Even with EUV, it’s unclear just how much further scaling is even possible; at 2nm, transistors would be just 10 atoms wide, and it’s unlikely that they’d operate reliably…as the transistors are packed ever tighter, dissipating the energy that they use becomes ever harder.

The new techniques, such as strained silicon and tri-gate transistors, took more than a decade to put in production. EUV has been talked about for longer still. There’s also a significant cost factor. Technology may provide ways to further increase the number of transistors packed into a chip, but the manufacturing facilities to build these chips may be prohibitively expensive.

Compounding all this is that all these extra transistors have become increasingly hard to use. In the 1980s and 1990s the value of the extra transistors was obvious: the Pentium was much faster than the 486, the Pentium II much faster than the Pentium. Those easy improvements stopped coming in the 2000s. Constrained by heat, clock speeds have largely stood still, and the performance of each individual processor core has increased only incrementally. What we see instead are multiple processor cores within a single chip. This increases the overall theoretical performance of a processor, but it can be difficult to actually exploit this improvement in software.

These difficulties mean that the Moore’s law-driven roadmap is now at an end. ITRS decided in 2014 that its next roadmap would no longer be beholden to Moore’s “law,” and… the next ITRS roadmap, published next month, will take an approach it describes as “More than Moore.”

IFTLE is in full agreement, as you know IFTLE thinks technologies like 2.5 and 3DIC have replaced Moore’s Law. May Moore’s Law rest-in-peace…

Those who continue to preach that “Moore’s Law is still alive and well” are akin to those who claim to have seen Elvis yesterday on the streets of Nashville!

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Samsung announces 4GB HBM2 DRAM

Samsung Electronics announced that it has begun mass producing the industry’s first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, and enterprise servers. [link]

The newly introduced 4GB HBM2 DRAM, uses Samsung’s 20nm process technology and is reportedly more than seven times faster than the current DRAM.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains > 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Samsung’s new DRAM package features 256 GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

Samsung also plans to produce an 8GB HBM2 DRAM package in the next 12 months. Offering designers a 95 percent space savings vs GDDR5 DRAM.

Samsung announced that production volume of HBM2 DRAM will increase over the remainder of the year.

The second-generation HBM (HBM2) technology is outlined by the JESD235A standard. It uses 128-bit DDR interface, 1024-bit I/O, 1.2 V I/O and core. Just like HBM1, HBM2 supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks). HBM Gen 2 expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 2 Gb/s per pin.

Continuing our look at the 2015 3D ASIP Conference…

Prismark

Brandon Prior of Prismark addressed the “Status of 2.5/3D and other high density packaging technologies”.

2.5D / Silicon Interposer is an effective fine-pitch solution to provide >10,000 die-to-die connection. Currently used for:

– ASIC/FPGA die partition

– GPU/CPU/ASIC + memory

– For L/S <2μm and vias <5μm, Si interposer is the only available approach

• Several notable production developments with 2.5 and 3D technology in 2015

– All major DRAM players with production capability of TSV memory stacks; but focus remains on “near memory” requiring extremely high bandwidth

– Si Interposer adoption by AMD for “gaming enthusiast” GPU

– Continued work with TSV for Image and other sensors for backside access

• Increased adoption of 2.5 and 3D TSV dependant on cost and alternatives

– Si Interposer most relevant to server/telecom CPU and ASIC products

– TSV for portable processors still under review, but LPDDR5 is more likely

• Companies such as Sony, Toshiba, Aptina, ST have been shipping image sensors with TSV for back side access since 2009/2010
• Sony is first to ship using die stacking “hybrid” approach in 2012/2013; economical only for 8 – 13MP designs

ADVANCED PACKAGE SUBSTRATE DESIGN RULES

• Substrate technologies continue to progress

– 10-12μm L/S in HVM for MPU

– 8μm L/S capabilities in process at Kyocera, Ibiden, Shinko and others

• Sub-5μm on organic is a challenge

– RDL technologies used in FO-WLP or Si Interposer are looking to displace build-up substrates

• Ibiden and Shinko working on “organic interposer”

– Internal qualification now down to 2μm L/S and vias 10-25μm

– Yield remains a challenge, so Si Interposer remains compelling alternative

FO-WLP MARKET STATUS

• Expectation is that Apple will proceed with TSMC InFO FO-WLP for A10 in 2016

– Tool orders and capacity seen in supply chain

– Speculation on second location/source being required

• OSATs see uptick in interest for products outside application processor

– OSATs: JCET/STATS, ASE, SPIL, Amkor, Nanium, PTI, DECA and Inotera

– Possible Customers: Marvell, Qualcomm, Mediatek, Dialog, Renesas, Infineon,

Freescale, Avago, Analog, Spreadtrum, Maxim, HiSilicon

• Most focus on smaller die/packages: 3×3 to 8x8mm

– “Large die FO-WLP remain too expensive and yield challenged”

– Expect 1 and 2 die packages with hundreds of I/O in 2016 from multiple applications and companies

– Most production of FO-WLP focused on 1-3 layer RDL at 5-15μm L/S.

– 300mm reconfigured wafers remains dominant approach for now

• Intel and Samsung remain skeptical of FO-WLP

– At this time, neither have plans to install fan out capacity

– Not seen as cost effective means to make a thinner package

 

Northrup Grumman / DARPA DAHI Program

After DARPA program Manager Dan Green gave an introductory presentation on the DARPA goals for DAHI (Diverse Accessible Heterogeneous Integration) [see IFTLE 206, “COSMOS and DAHI Herald the Era of 3D Heterogeneous Integration” ] Augusto Gutierrez-Aitken detailed DAHI activity in NGAS.

DAHI seeks to create circuits from various CMOS nodes with SiGe, GaN and/or InP.

They have developed a basic foundry infrastructure allowing external design teams to generate multiple technology heterogeneously integrated circuits

• Developed a process to integrate multiple compound semiconductor technologies to CMOS wafers
• Demonstrated three-technology integration between IBM 65nm CMOS, NGAS TF4 InP HBT, and NGAS GaN20 HEMT
• Demonstrated integration of third-party technology

A typical NGAS DAHI flow is shown below.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Beginning coverage on the 2015 3D ASIP (Architectures for Semiconductor Interconnect and packaging) conference sponsored by RI Int which is the final major high density packaging conference of the year.

This years technical Chairs were Prof Mitsumsa Koyanagi from Tohoku Univ. and Rama Alipati from GlobalFoundries.

Professor Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the Conferences first recipients of the “3DIC Pioneer Award”. After more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, 3D ASIP management were convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first to recognize what 3DIC could do, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Sony

Hirayama of Sony detailed their work on 3DIC based CMOS image sensors.

AS shown below, the color pixels require fewer metal interconnect layers and high voltage, lower temperatures during processing and longer anneal times whereas the logic portions of the circuit are quite the opposite needing many more layers of interconnect and low voltage, higher processing temps and shorter anneal times. It therefore makes sense to fabricate these layers separately and stack them.

This separation of circuits and functions is shown below.

Sony introduced this technology in 2012 and by 2015 had more than 2/3 of their shipped CIS using this method of fabrication.

In the future, Sony sees introduction of processors and memory to this stack.

SPIL Acquisition

Digitimes estimates that more than $893MM worth of SPIL orders are moving to other OSAT companies due to the potential acquisition by ASE [link].

As we have discussed previously [see IFTLE 252 ‘ASE Makes Bid for Siliconware Shares…” ], ASE has previously acquired a 25% stake in SPIL through an unsolicited tender offer, and has launched another tender offer to buy more shares of SPIL which will bring its total ownership interest in the company to almost 50%. ASE has also disclosed its goal is to acquire the rest of SPIL shares, i.e a complete takeover as IFTLE initially projected. .

SPIL now reports that fabless “..chip vendors such as Qualcomm, Broadcom and MediaTek all try to diversify their suppliers to reduce supply risks”. Thus the other IC assembly and test services companies will benefit from ASE’s potential takeover of SPIL. SPIL points to Amkor, China-based Jiangsu Changjiang Electronics Technology (JCET) and Taiwan’s Powertech Technology (PTI) as the beneficiaries.

Consolidation of Notebook computer vendors.

Digitimes also reports that Japan-based PC vendors Sony, Toshiba and Fujitsu are reportedly finalizing talks to merge their notebook businesses into one company [link]. Post merger Sony, Fujitsu and Toshiba would account for 30% of Japan’s notebook market, compared to 29% held by the NEC/Lenovo joint venture.

For all the latest in 3DIC and other high advanced packaging stay linked to IFTLE…