Continuing our look at the 2014 IMAPS Conference held in San Diego…

K&S

Colosimo of K&S examined high productivity Thermo-compression FC bonding. In traditional FC assembly, the chips are tacked down to the substrate and then solder joints are melted and mass reflowed in an oven. Mass reflow (MR) becomes more difficult as the pitch of the solder bumps becomes finer due to control of solder flow and warpage of the package when the die and substrate are heated and cooled together. These issues are exacerbated for thin die and die stacks. Thermo compression (TC) was developed to locally heat the solder without subjecting the entire substrate to the heating and cooling cycle.  This requires the bond head heat past the MP of the solder and then cool down to a low enough temp to pick up the next die from the wafer mounted to tape. Current tools today can do this in 7 to 15 seconds (a few hundred units/hr) which is substantially slower than todays standard FC process.

The newly developed K&S TC  tool reportedly can process 1000-2000 chips/hr.

Shinko

Shinko detailed their studies on 3D stacking an SoC die and a memory die in a SiP package.  The fig below shows X-sectional image of the 3D Sip. The structure has a bottom die (6mm sq) with TSVs, stacked on an organic substrate and a top die (9mm sq) stacked on the back side TSV of the bottom die. The bottom die has 10um TSV on 40um pitch.

 

MEOL (mid end of line) processing flow is shown below. The bottom wafer with copper pillar bumps on its front side and blind TSV is attached to a carrier and thinned to expose the TSV and passivated. The carrier is debonded and the die are sawn for assembly.

 

The figure below shows the die stacking and packaging flow. The bottom die with copper pillar bumps is assembled onto the BGA substrate. Next the microbumps on the top die are bonded to the TSV pads of the bottom die. The finished assembly is encapsulated and solder balls are attached to he BGA package.

BLR (board level reliability) comprising Temp cycling ad drop testing is shown in the following table. Weibull plot of temp cycling shows first failure at 2,344 cycles and 0.1% failure at 1194 cycles.

 

Samsung EM

Samsung Electromechanics examined the fabrication of Fine featured organic interposers. The next gen packaging such as wide IO memory – logic packaging (JEDEC requires min bump pitch of 40um) requires connection on less than 50um pitch. The Samsung EM process flow using photoimageable build up layers reportedly is capable of less than 5/5 L/S with micro-vias on 50um pitch. The layers can be connected with Vias with min 10um dia.

 

Univ. Texas

Paul Ho’s group at U Texas has examined the impact of copper grain structure and material properties on via extrusion in 3D interconnects.

The copper vias they examined were 5.5 x 55um in 780um thick Si. In sample A the copper grain size was uniform. In sample B the copper grains were a mixture of large and small grains. The average elastic modulus for A TSV were 117 MPa and for B 93 MPa. TSV extrusion was found to be 117nm for A and 147nm for B. The smaller more uniform grains were found to exhibit higher yield strength and therefore less via extrusion. Stronger Cu/Si interfaces are also shown to achieve less via extrusion.

GaTech Mechanical Eng

Charles Ume of GaTech reported on his studies detailing the effect of bump pitch, package size, Mold compound and substrate thickness on PBGA warpage.

FEA studies reveal that solder bump pitch, package size and mold compound thickness affect he maximum PBGA thickness significantly, but substrate thickness does not.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2014 IMAPS Conference held in San Diego…

Corning

Shorey of Corning Glass gave an update on glass panel fabrication. He noted that “there are challenges in applying standard plating processes to glass,” but Autotech has recently reported significant progress in the ability to metallize glass vias using new adhesion promoters. They show complete fill with little overburden in 80um holes in 300um glass.

They also showed 370 x 470 x 0.3mm glass panels. A Rudolph Jetstep S3500 was used to create “~3um L/S…with additional work we fully expect to be able to resolve < 3um L/S”.  Smallest vias shown were 35um in 100um glass.

 

Rudolph Technologies

In an aligned presentation, Ruhmer of Rudolph discussed high resolution patterning to enable panel based advanced packaging.

When examining litho steps for panel processing Rudolph points to the following key items: minimum resolution, overlay accuracy, sidewall angle and CD control, depth of focus (DoF), exposure field size and warped panel handling capability.

– optical characteristics of suitable litho systems should offer N/A of 0.1 to 0.15 in order to meet L/S resolution requirements for high density interposers (1-2um)

– depending on the complexity of the interposer 5 or more mask layers per side can be required. In general the overlay accuracy should be ~ 1/3 the resolution limit of the system, so for a resolution of 1.5um the overlay accuracy should be 0.5um. Reconstituted substrates for FO-WLP is more complex due to die shift.

– accurate focus control across the wafer is required for tight CD control and consistent sidewall angle in photo dielectrics

– depth of focus for back end processing requires 10um or greater range, not typically available in front end steppers.

– exposure field size should at least cover one die to avoid stiching.

– in initial panel based FO-WLP testing warpage of approx 10mm was observed for a Gen 2 glass panel. Equipment with  warped handling features like switchable and compliant gaskets on chucks and handlers ae needed for litho and other processing steps.

Corning / Unimicron / Qualcomm

Corning, Unimicron and Qualcomm reported on their low cost interposer development program.

They sought to show feasibility of interposer manufacturing on their 200um thick 508 x 508mm glass panel format. Daisy chains are connected with 100um TGV (through glass vias) and 8/8 L/S.

The process flow using ABF dielectric is shown below.

 

Early handling led to glass breakage. The ABF lamination (Ajinomoto) gave the thin glass panel mechanical support more handlable.  Then vias were created through the ABF.

Warpage of the glass panels were compared to laminate (BT) panels of the same size with 200um core thickness. The glass panels showed 3X lass warpage.

DNP

DNP reported on a comparison of fabrication processes and electrical performance of silicon and glass interposers. I should note that these appear to be DNP processes, not necessarily standard processes. For instance they comment that silicon is fabricated on 200mm lines but glass can be fabricated on large panel lines. The facts actually are that Si is fabricated commercially on 300mm lines and large panel glass interposers are in R&D stage.

Their silicon and glass processes ae compared below.

 

In the silicon process, the holes are formed by ICP-RIE. The wafer is then thermally oxidized and coated with PECVD SiN. The holes are seed sputtered then plated with Cu, CMP’ed and both sides covered with Cu/PI RDL. TSV are on 200um pitch.

In the glass process, 50um TSV on 200um pitch are formed in 0.3mm glass by focused electrical discharge (Recall AGC is a proponent of this method). After Ti/Cu seed the vias a electroplated with copper and the surfaces CMP’ed. Copper / PI RDL are added to both sides.

Glass interposers showed better high freq. performance than silicon as was expected.

 

Shinko

Mori of Shinko described their development of Glass Interposers with fine pitch ubumps and their warpage results. They examined glasses with CTE’s of 3.2 and 9.5 ppm and corresponding moduli of 73 and 90 GPa. Their design rules are shown below.

 

Three laminates were examined with properties shown in the table below:

 

Warpage of the die on interposer on substrate showed that warpage of the assembled stack is lowered with lower CTE laminate substrate but is not affected by the CTE of the glass Interposer. Modeling verified these results.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

3D ASIP

It’s that time of year again to be thinking about registering for the RTI sponsored 3D ASIP (Architectures for Semiconductor Integration & Pkging) which will be held at the Burlingame Hyatt on Dec 10-12 [link].

RTI ASIP has been focused on 3DIC and 2.5D for 11 years now. As we are now finally seeing  commercial commitment from the memory suppliers and the graphics module manufacturers hopefully we are observing 2.5/3DIC  finally taking off. Unlike other, more academic conferences, RTI ASIP has always been focused on the commercial and business aspects of bringing 3DIC to the market place.

This years program includes two special pre-conference symposia . A  ½ day symposia 2.5/3D IC design tools and flows led by Herb Reiter will include speakers from Cadence, Mentor, Apache design, GF, Rambus and Qualcomm. There will also be a half day tutorial on the current state of the art in 2.5/3D processing led by yours truly with “drill and fill” covered by Dean Malta of RTI; Temp bond and via reveal presented by Severine Cheramy of Leti and assembly presented by Laura Mirkarimi of Invensas.    As a special bonus, those attending the processing tutorial will receive a free copy of “The Handbook of 3D Integration Volume 3: 3D Process Technology” edited by Garrou, Koyanagi and Ramm.

The regular conference includes presentations by Micron, Xilinx, Nvidia, GF, Synopsys, Nanium, Unimicron ad many more . Of special interest should be the updates on their DARPA ICECool  3D cooling programs by Bakkir of GaTech and Gaynes of IBM Watson and the IoT (Internet of things) presentations by Beica of Yole and Schulz of the silicon integration initiative.

Hope to see you there.

Amkor – Extending Mass Reflow to Finer Pitch Copper Pillar Bumping

Another key paper from the recent 2014 IMAPS Conference in San Diego was by Fernando Roa of  Amkor concerned with extending the current processing envelope for Copper pillar bumping using mass reflow (MR).

Thermo compression (TC) is typically applied for copper pillar bumping. In general, it is a slower more expensive assembly process since each die has to be positioned and mated before moving on to the next die. A bonding head is typically used to hold the die flat and in alignment with the substrate while heat is applied to complete the connection. In general MR throughput is 2X that of MR.

In contrast, MR bonding places the die and then reflows them all at once.  Std FC attach and capillary underfill is shown below vs thermo-compression (TC) bonding.  TC typically underfills with non conductive paste (NCP) or film since capillary underfills are more difficult to use with copper pillar bumps because of their fine pitch.

 

Amkor typically uses the MR process flow for copper pillar bump (CPB) from 200 to 100um pitches with minimum changes to the standard process flow.

For fine bump pitch (b), since the bumps are much closer together there is less room to create solder mask defined pads as show below. Since the bump diameter is close to the typical width of the trace they are allowed to form connection directly on the trace.

 

While typical MR assembly relies on solder self alignment during reflow, MR of solder to trace is more difficult since self alignment to solder catch pads is not possible. In MR of fine pitch bumps the solder wraps around the trace in contrast to TC joints that typically show solder squeezing out of the joints because of the compression.

Very precise selection and control of die thickness, substrate construction and substrate finish is necessary to reduce or eliminate solder shorts and non wets. Roa indicates that Amkor efforts are underway to extend MR to finer pitch bumping activities.

By Dr. Phil Garrou, Contributing Editor

Rumors on the SCP Acquisition

We have discussed the Acquisition of STATSChipPAC (SCP) in recent blogs [see IFTLE 195,  “STATS in play….” and IFTLE 198, “….STATSChipPAC suitors named…”.] In late August, Bloomberg News reported that Jiangsu Changjiang Electronics (JCET) and Tianshui Huatian Technology were working on offers for SCP [link].

IFTLE continues to hear rumors from multiple credible sources that the deal with JCET is imminent and that final price is being negotiated. While denials are being floated by JCET, we all recall that similar denials were also rampant in the recent IBM / GF deal till the last minute.

IFTLE is also hearing that during these negotiations SCP, like IBM, is loosing key personnel throughout the organization. But, whereas IBM personnel movement was to ultimate acquirer GF, not so for SCP and JCET. Rumors from SCP indicate that JCET will not be retaining any key Singapore management in an effort to lower their cost position. As JCET waits to lower the ultimate acquisition price, IFTLE believes they are also lowering the overall value of SCP. A company is its people!  There are also unsubstantiated rumors of customers leaving SCP because of this chaos.

While it may be 2015 before the deal is consummated, IFTLE can see SCP falling from the #4 OSAT position and is probably already behind PTI.

Will SLIT replace TSV?

At the recent IMAPS meeting in San Diego Xilinx and SPIL presented the paper “Cost effective, high performance 28nm FPGA with new disruptive Silicon-less Interconnect Technology (SLIT).

In the traditional Xilinx silicon based FPGA module the FPGA die with microbup interconnect are connected to the 4 layers of 65nm interconenct on the silicon inerposer which then has TSV and c4 bumps to connect power/grd and other incoming sgnals.

In the new SLIT technology the same FPGA slices are mated to 65nm intrconenct on silicon but no TSV are required since ther is selective Si removal and backside contact formation along with required inline wafer warpage control. The structure is EXPECTED to give lower cost while delivering better electrical performance. The structures are compared below.

TSV “drilling and filling” are eliminated as are thin wafer handling, backside reveaand many inspect and metrology steps.

 

(a) traditional Xilinx FPGA with silicon Interposer; (b) FPGA without interposer

 

(C) SLIT in X-section

The 65nm interconnect are created on std bulk silicon The bottom most dielectric layer is selected to have high selectivity during subsequent backside etch. The top of the metallization interconnect layer is capped in 45um pitch pads and microbumps.

The FPGA die are  thinned diced and stacked onto the interconnect wafer. After reflow the ubump gap is underfilled and overmolded and the mold cmpd is ground down to expose the die top surface.

Subsequent wafer thinning is done to the dielectric etch stop layer.  Contact holes re etched in the dielectric and pads and balls are created/placed.

The main processing issue is wafer warpage, especially after the full silicon removal. Stresses are balanced with a reinforcement layer and other stress controls during the processing.

This is certainly a very interesting proposed structure and IFTLE will be keeping an eye on SLIT processing.

More from IMAPS in subsequent blogs

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…