By Dr. Phil Garrou, Contributing Editor

Now, at first glance you may be saying, “Why is IFTLE concerned with the Toshiba’s memory business? This is an advanced packaging blog!” But I hope most of you have learned IFTLE lesson #1 which is whatever effects chips, directly affects chip packaging. So with that in mind, the recent report by Reuters that Apple is looking into joining the Foxconn bid is very interesting. [link]

The sale of the Toshiba memory business is reportedly being driven by “…multi billion dollar writedowns at Toshiba’s US nuclear unit, Westinghouse” which has recently declared bankruptcy. The collapse of Westinghouse, once the key to Toshiba’s plans to diversify away from consumer electronics, has been hastened by nuclear power project delays in Georgia and South Carolina. Reports from Toshiba are that losses for the year may total > One trillion Yen [link]

To prevent total corporate bankruptcy, Toshiba put up its memory business for sale. Toshiba reportedly narrowed down its list of offers to bids from Broadcom, SK Hynix, Western Digital and Foxconn. According to the Reuters report, Apple was not part of the initial Foxconn bid. .

According to Reuters, Apple is considering taking a 20% stake (several billion dollars) in the Foxconn bid, Foxconn would take 30% and Toshiba would keep a partial holding so the business would remain under US and Japanese control. Reportedly “…Foxconn has been considered a national security risk (to Japan) due to its ties with China”.

This would fit with Apples stated goal of insuring a stable supply of key components. Apple has traditionally used Toshiba’s flash memory in its iPhones and iPads, especially after competitive issues with Samsung developed. Ownership of Toshiba’s NAND flash business would increase Foxconn’s control of the parts it procures for Apple to assemble their phones. Apple, in return, ensures that it gets the best NAND flash for its products, forcing its competitors to stand in line.

But….According to reports in the Financial Times, even if Foxconn successfully partners with Apple, Japanese government officials could still block the sale because they have reservations about al bidders with factories in China. “The Japanese government, Toshiba and its partner Western Digital will likely do everything in their power to prevent any buyer that could potentially allow technology leakage to China and South Korea,” … “Partnering with Apple will not eliminate their concerns regarding Foxconn.” [link]

There are also reports that a consortium consisting of SK Hynix and several Japanese financial institutions reportedly has offered more than $9B for a majority stake in Toshiba memory chip business [link, link] This would make Hynix a major player in both DRAM and NAND and make them more of a threat to rival Samsung. It would also put even more of the worlds memory supply on the Korean peninsula.

UNITY

Any of you looking for Yann Guillou at SEMI Europe will have your emails bounce back like mine did recently. Yann is now at Unity SC. Unity was formed last summer by combining Fogale Nanotech’s SEMICON division with Altatech [link]. Unity SC remains a subsidiary of Fogale Nanotech with headquarters in Grenoble FR. Their goal is to provide process control solutions for the semiconductor industry, with a focus on the advanced packaging and MEMS markets.

They claim to have the only complete solution for 3D TSV and FOWLP.

So, if you’re doing advanced packaging and/or MEMS and looking for measurement of thickness, CD, surface profiling, TTV, bow, warp, roughness, overlay or defect inspection take a look at their offerings.

Continuing our look at fan-out presentations at the recent IMAPS Device Packaging Conference…

JCET (STATS ChipPAC)

As we detailed in IFTLE 331, Yole Developpement reports that JCET leads all FOWLP vendors edging out TSMC with a 37% market share. [link]

At the recent IMAPS Device Packaging Conference JCET discussed advanced 3D eWLBB-SiP technology.

He following slide is a nice summary of target applications for SiP packages.

JCET claims their ability to create ultrafine L/S ground rules, down to 2/2 in a 3 RDL layer format, enables improved routability and tighter component placement. In addition since eWLB eliminates the use of substrate, it reduces the overall package thickness by up to 50% (down to 0.2mm in 2017).

Through additional technologies like thick Cu RDL, embedded inductors and IPD integration JCET provides options to meet RF performance requirements of L, Q factor etc.

For all the latest in advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

As one might expect, there were quite a number of fan-out packaging presentations at the recent IMAPS Device Packaging Conference and the next few IFTLE will examine some of those presentations.

K&S

Tom Strothmann of K&S discussed “Speed and Accuracy Optimization for Fan Out Die Placement”. Die placement accuracy in conjunction with die shift from the reconstitution process must accommodate the design rules for RDL via size, passivation opening size and pad pitch for the intended devices.

– die placement speed is directly related to cost and the highest UPH is preferred. Typically 10K UPH at 3-5um accuracy. Multi head placement has potential to place 12K UPH with accuracy of 7-10um.

– Accuracy is directly related to yield and the subsequent cost for advanced products

– > 98% yield is required for each RDL layer since compounding yield loss from multiple RDL layers rapidly erodes margins ($$). Thus a lower RDL count is better.

Panel Processing (or as we called it in the late 1990s “Large Area Processing”)

– still remains > 2 years out

– many versions still in development, panel size has not been standardized, equipment suppliers still have moving target

– panel line cost estimated at $100MM

– high speed placement required for lower costs

– panel warpage is still a problem

– die shift occurs as mold cmpd cures

– plating uniformity difficult on large rectangular panels

“High Density fan out will remain on round format for the foreseeable future”

InFO Process Flow

Of great interest was Strothmann’s discussion of the InFO process flow. IFTLE has reprduced the slides below:

Yole Developpement

Jerome Azemar of Yole discussed fan out packaging market trends. Of interest was the following chart showing various applications vs general requirements for I/O and package size ranging from the small, low IO Codec for WiFi to large, high I/O FPGA’s.

Fan out technical challenges are described in the slide below including warpage, die topography, failure to planarize chips with mold compound resulting in RDL distortion, die shift during mold cmpd cure and solder joint issues for large packages.

 

Yole reports 2016 fan out packaging revenues at $492MM with SCP / JCET holding 37% market share. TSMC is close behind with 35% share based on their one client Apple.

 

For all the latest in advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2017 IMAPS Device Packaging Conference (DPC) held annually in AZ.

Prismark

Brandon Prior of Prismark examined “the Changing Landscape in the Back End.” The Prismark punchline is that even though the industry is maturing and entering a period of consolidation and slower growth, “…packaging technology remains critical to delivery of semiconductor and sensor functionality”

Below are some of the system trends that they report:

– 0.4mm pitch components have been mainstream now for > 10 years due to package test below 0.4mm     SMT processes, equipment and materials are not ready for ).3mm

– 0.8mm thick packages are in flagship smartphones (WLCSP,QFN, PoP, FCCSP) Users are asking for 0.6mm; EMI shielding in the package is becoming common.

– SiP use is growing not only in Rf solutions due to smaller footprint and lower total cost potential

– WLCSP has now been commercial for nearly two decades. Both OSATS and foundries have significant capacity. Mobile phones and tablets most significant users. Concerns about cost, reliability and assembly remain.

– FOWLP receiving significant interest. Products are developing for solutions based on: single die, PoP and Multidie with passives as shown below.

While panel based FOWLP remains of great interest at companies like: STATS/JCET, ASE, DECA, PTI, SEMCO and Unimicron, imaging equipment players (Rudolph, ORC and Ushio) reportedly have not shipped any tools. DECA an SEMCO continue to lead in promoting panel based technology.

A very interesting slide is shown below. It indicates that Prismark sees 80% of value add growth coming from wafer based packaging. [for someone like IFTLE who was promoting WLCSP back in the late 1990s, while at Dow Chemical, when the popular response was that wafer based packaging was absurd, this is great vindication!]

Amkor

Ron Huemoeller of Amkor examined “Heterogeneous Integration: Packaging for the Future”. Huemoeller indicated that creating value at the packaging level is dependent on (a) smaller form factor, (b) enhanced performance, (c) modularization and (d) high reliability.

Amkor indicates that the high end packaging market can be categorized by application as follows:

Also of interest is the depiction of key technology drivers by Industry segment:

DOW Chemical

Speaking of my former employer (been gone since 2004), Eric Huenger discussed “Advanced Materials and Interconnect Technologies for Next Gen Smart Devices”. Although you may have seen it before, I still enjoy seeing the slide shown below which depicts the materials necessary to develop todays high end packaging. It’s good to see Dow with such a broad portfolio. That’s exactly what some of us were pushing for > 15 years ago.

From a historical perspective those that drove electronics in Dow Chemical in the early years (1985-2005) consisted of the following folks:

 

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

SEMI Honors European  3D Integration Leaders

The European SEMI Award was established in 1989 to recognize individuals and teams who have made a significant contribution to the European semiconductor and related industries. At the SEMI ISS meeting (Industry Strategy Symposium) in Munich, SEMI announced the recipients of the European SEMI Award for 2017. Winners were nominated and selected by peers within the international semiconductor community in recognition of outstanding contributions in the field of 3D Integration.

Rolf Aschenbrenner, deputy director of the Fraunhofer IZM; Eric Beyne, fellow and program director of 3D System Integration at IMEC; and Gilles Poupon, CEA fellow on Advanced Packaging and 3D Integration at CEA-Leti were this year’s award winners.

 

Trolls

A recent EEE Times article took a look the increase in activity that they have seen from “patent licensing companies”[link], aka trolls.

JC Eloy of Yole Developpement offered that chip vendors have become more vulnerable in recent years because M&A in the semiconductor market, has put many patents is up for sale.

For those of you around the world that don’t understand what this is about, I thought I’d add some background to the EE Times discussion. As the Yole figure below shows these are companies that neither make nor markets products. They derive income by licensing patents to / litigating against companies suspected of infringing said patent(s).

From the work that IFTLE has done for legal firms as an expert witness, I have learned that the legal term for such firms is “non-practicing entity” or simply NPE. The slang term used in the industry for such entities is “patent trolls” which is not meant in any way to be complimentary. I’m not talking the Dreamworks cartoon for kids here, I’m talking old school trolls (…the Norse nouns troll and tröll …mean fiend, demon or werewolf – Wikapedia).

Now trolling in the English language especially modern day slang has many meanings (none of them positive) like internet trolls, but for our discussion here Patent Troll is a term applied to a person or company who attempts to enforce patent rights, against accused infringers, far beyond the patent’s contribution to the prior art, often through borderline illegal, legal tactics”. I hope this definition is polite enough for any trolls out there reading this.

Their standard MO (modus operandi) is to buy up patents with some lifetime left on them at depressed prices. Then, their hoard of lawyers are unleashed on companies that are thought to, or hoped to be, or in most cases just hoped to be fearful of the costs of fending off the accusations of being in violation of said patents. Some of them may have R&D operations which help them determine where to focus and others are simply offices full of lawyers and their helpers.

The MO (modus operandi) of the patent troll is to throw a wide net filing lawsuits against a large group of similar companies and then focusing on what is considered to be the weakest one. Getting them to “give up” and pay what might be an initially low fee, to avoid court costs, is key to their ability to intimidate the rest. Once the license precedent is set, the fact that a similar company has licensed the said patent(s), is a strong factor in court cases. After the first company is “hooked” the price for the rest normally goes up substantially.

Yole has identified the most active NPEs in the figure below. Wi-LAN, based in Ottawa, reportedly acquired 2000+ U.S. patents in 2015, mainly from Infineon/Qimonda and Freescale. In 2016, Wi-LAN initiated 17 lawsuits.

 

In the EE Times article, Mike McLean of TechInisghts’ offered the following suggestion for dealing with NPE’s, “To deal with NPE’s, operators need to either take patents off the market before [NPEs] get them in their hands, or need to be able to effectively challenge patent validity.“ Helping deliver the latter has provided a steady income stream for IFTLE over the last decade.

More on Intel EMIB

At the recent Intel “Technology and Manufacturing day” in SF, Intel Sr. Fellow Mark Bohr again pushed for their EMIB technology [see IFTLE 324 “Intel EMIB Implementation in the Stratix MX”] as the best solution for heterogeneous integration. “Heterogeneous Integration …… This is where you can not only combine two similar die in a package, but in some cases two very dis- similar die….Heterogeneous Integration will be a bigger part of our future…”

In the expanded view and cross section shown below we see the tighter pitch peripheral IO connection to the silicon EMIB bridge. Bohr contends that EMIB solution is cheaper because it does not contain TSV, through silicon vias.

Bohr notes that this is not just a packaging technology since the chips must be custom designed to be used with the EMIB bridge technology. To IFTLE this is a very important limiting factor that I have not seen discussed previously.

 

For all the latest in Advanced Packaging, stay linked to IFTLE…