By Dr. Phil Garrou, Contributing Editor

Finishing our look at IMAPS 2015…

ULVAC – TSV etching

ULVAC has developed an etch tool capable of both Bosch etching and their “direct etch” process. Direct etch uses a mix of SF₆ and O₂ and can result in either a sloped or straight sidewall as shown below. They claim that the direct etch results in significantly shorted PVD time and that the taper vias can result in 80% less electro dep time when filling the vias.

Tanaka Kikinzoku – Gold sealing technology

Tanaka Kikinzoku shared their results on hermetic low temp sealing for MEMS and WLP. They developed a wafer level hermetic sealing process using a rim structure covered with sub micron gold particle paste by stencil printing as shown below. The maximum leak rate was found to be 10^-14 Pa·m³/s (He)

 

Asahi Kasei Electronic Materials

Asahi Kasssei (AKEM) shared their studies on the thermal cycle testing of organic passivations for WLSCP…well really they didn’t share them and I have a few comments about that. Through the years I have complained about reports that fail to fully identify exactly what they are examining. Many of us know them as A,B,C,D papers ….you know “A was much better than B and somewhat better than C and D.” This complaint is not pointed only AKEM, but rather at the many companies and institutes who publish such papers.

Granted such papers can lead us in the right direction if they are commenting that certain properties lead to better results, but they can never be reproduced since no one else knows what it was that was examined.

AKEM introduced their studies by indicating that previous studies had found that PBO failed thermal cycling tests (TCT) earlier than PIs and they wished to know why. The problem is that there are many different types of PIs and PBOs. The examples you choose to compare will totally control the results that you get. The only hints we get is that their PI is a low cure version (“imidization of our specific PI is finished at 200C”) Would it have hurt to give us an experimental or commercial designation ? since AKEM has not chosen to share the structure of this material with us. Even worse is the identification of the PBO. The comment is made that “..the cure temp of the typical photo PBO is over 300 °C …” It is not clear that this is the kind of example that they used and certainly not clear why they used a high temp cure PBO to compare to a low temp cure PI. Those of us in the field know that there are many low temp cure PBOs to choose from.

As an example their examination of strain change vs time (fig 11) they state that “strain is effected by the polymer difference. Equivalent strain in the case of PBO is larger than PI because the modulus of PBO is lower than PI.” Would it not be better to test two known PIs and two known PBOs of differing modulus to make this case? Since I do not know the identity of the two materials that they chose to compare, I cannot draw a clean conclusion about any of their results. I think you see the point.

ORMET – Transient Liquid Phase Sintering (TLPS)

Ormet has been around our industry since the late 1990’s optimizing their TLPS products. ORMET has recently been acquired by Merk. They view their materials as solder replacements for either hierarchical soldering (consecutive joints are soldered at sequentially lower temps) applications where solder remelt is a problem such as MEMS lid attach, SIP and PoP.   Also for high operating temp market segments such as power electronics. Basically the TLPS pastes consist of a high mp metal (copper), a low melting point alloy ( SnBi) and a flus-polymer phase. As the temp is raised the alloy begins to melt and reacts with the high mp metal to form high mp alloys or intermetallics until there is no longer a molten phase at that temp. Pastes are formulate specific to the application.

They have worked with Kemet to develop a line of pastes for MLCC attach (multi layer capacitors) for high temp applications. Such materials have passed high temp storage (175 C for 2000 hrs); thermal cycling (-40 to +175 for 2000 cycles) and temp humidity bias (50V, 85C/85%RH 2000 hrs) without any failures. Brittle Cu/Sn intermetallic phases are found to initiate some cracks but appear to terminate on the Cu particles.

For all he latest on 3DIC and other advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.

Unimicron

Unimicron discussed their continued development of < 5/5 L/S for polymeric interposer applications.

While silicon can meet fine line (< 5/5 L/S) requirements easily by wafer level processing, silicon processing cost is a barrier to many applications.

There are two types of processes available to meet fine line requirements on organic substrates, traditional semi-additive processing (SAP) or laser embedded technology. They are shown in xsect below. Unimicron reports that current status for SAP is 8/8.

UV YAG lasers allow for maskless ablation processes by ablating trenches and blind vias simultaneously, but the throughput becomes slow as the features get larger. Throughput of eximer lasers is independent of pattern features since they are defined by the mask. The aspect ratio (h/w) for eximer laser was 1.2 for 3/3 in build-up film with fine filler particles and for 5/5. In general, the finer the filler particle size, the deeper the trench. Since they found that eximer laser ablation was much slower than lithography, the next developments will be with photo build up dielectric to replace the laser ablation. IFTLE should note that this is how it was done during the MCM era in the mid 1990’s, like the IBM SLC technology.

Princo – System on film

In yet another chips last packaging solution, Princo described their system on film technology. Following the figure below they 200mm glass wafer that is first surface treated with a PI and then a silane release coating then another PI layer. Steps 4 to 7 are a lift of copper metallization sequence (6/4um L/S ; 11um thick). Next comes a dielectric layer ad then laser formed vias. These steps are repeated for further layers (up to 8 so far). In step 14, the structure is released from the carrier. This RDL film wafer is then flipped over and the pads are opened through the PI layer and ENIG coated. Die are flip chip mounted, underfilled, overmolded and balls attached and balls placed.

They describe two modules. Module #1 consists of a µprocessor, LPDDR SDRAM / NAND flash combo memory and power management IC on a 6 layer 20 x 17mm module. The second module consists of a µprocessor and a bluetooth 4 dual mode chip packaged in a 4 layer 9.5 x 7.3mm thin film package.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.

YOLE

Advanced packaging has increased in complexity over the years, transitioning from single to multi die packaging there are several platforms now available as summarized by Beica of Yole in the following figure. When choosing a package solution, typically the most mature and established will be considered first.

When looking at flip chip ~ 37% of the cost is attributed to the substrate. The substrate also increases the thickness of the package.

Fan out packaging offers increased I/O but also a thinner package since the substrate is not required. Initially limited to eWLB licensees from Infineon (Nanium and STATSChipPAC) the market is expected to explode in the next few years as ASE, SPIL, Amkor TSMC and DECA bring fan out capacity online.

Yole’s Ivankovic compared expectations for glass/silicon interposers vs polymeric substrates. Glass interposer technology is still immature. Polymeric sub 10um L/S substrates are promising but need cost reduction and further L/S reductions. The sweet spot for silicon interposers appears to be up to ~ 3/3.

IFTLE feels that silicon interposers with coarser L/S can surely be manufactured but will not compete on a cost basis. A substrate technology gap exists between 10 and 1um. This will be where the battle for business will be fought.

ASE FOCLP

Chen of ASE escribed their new Fan out Chip Last Package (FOCLP) which they see as a low cost alternative to eWLB FOWLP solutions. Copper pillar bumped die are mass reflowed onto a low cot coreless substrate, followed by overmolding, which also serves to underfill the die. The Cu pillars allow die connection at 50um or below, negating requirement for RDL n the die. The Cu pillars are bonded to one side of the copper trace (down to 15um L/S) and solder balls are directly bonded to the other side. This makes the “substrate” be effectively as thick as the copper in the traces and allows the final package to be as thin as 400um. Implementation with multiple die, inclusion of passives and 3D structures can all be implemented.

STATSChipPAC – High Density eWLB

Currently eWLB devise are used in baseband processors, RF transceivers, power management ICs, NAND memory controllers, on 2 node and ramping on 20nm. In a number of cases STATS reports a 20-40% reduction in package size and a 50% volume reduction due to its slim form factor.

STATS presented their work on with Qualcomm defining eWLB technology with high density ( 2/2 L/S ) and multilayer RDL. Their test structure contained 3 layers of RDL with 2/2, 5/5 and 10/10um L/S.

These structures were built and passed std JEDEC reliability testing.

Nanium – Advances in eWLB

NAnium described new developments in eWLB technology. Kroehnert indicates that the first eWLB based products have been qualified for wafer level SiP and WLPoP with embedded multi die, discrete passives, already packaged components sensors and optical elements.

As thin 300mm reconstituted wafers are not stable enough to be handled in traditional equipment, temporary bonding of recon wafers was developed. They found significant impact from bot the temp bond adhesive and the carrier composition.

The majority of work being done is to enable higher density integration:

– finer L/S

– multilayer RDL routing

– multi die placement with smaller inter chip distances

For all the latest in 3DIC ab=n other advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

IMAPS 2015 also known as the 48^th International Symp on Microelectronics was held this past Oct in Orlando, FL. Umi Ray of Qualcomm was General Chair and Erika Folk of Northrup Grumman was Tech Chair. There were 30 sessions, > 150 presentations and > 135 exhibit booths. Certainly, in terms of microelectronic packaging, this is the largest annual exhibition in the USA. In the next few weeks we will take a look at some of the presentations that caught the eye of IFTLE…

First, let’s first take a step back to one of the best boxing movies of all time, ROCKY. In 1976, Sly Stallone (who by the way spent his early years growing up on my block in Hell’s Kitchen, NYC) wrote and starred in this rags to riches American Dream story of Rocky Balboa, an uneducated but kind-hearted boxer in the slums of Philadelphia who gets a shot at the world heavyweight champion Apollo Creed, and looses the fight. The film earned three Oscars, including Best Picture. In 2006, the film was selected for preservation by the Library of Congress as being “culturally, historically, or aesthetically significant.”

Anyone who saw the film at the time will never forget the single line that ended the movie. As the ring announcer is proclaiming Creed the winner, Rocky, with both eyes swollen shut, is shouting out “Adrian!, Adrian!“ calling for his girlfriend (Talia Shire) . It brought grown men and women to tears. [link]

Anyway after many sequels, none of which came anywhere near the quality of the original, fast forward to 2015 and the movie “Creed” where Adonis Creed, Apollo’s son asks Rocky to become his trainer after no one else will work with him. In a strange twist of fate Creeds son also ends up fighting against the champion and looses but “…though he lost the fight, Creed won the night”. For his performance, Stallone has been nominated for the Golden Globe Award for Best Supporting Actor in a Motion Picture, his first nomination since the original Rocky, 40 years ago. Certainly a comeback for Rocky!

So you ask yourselves where is IFTLE going with this? Be patient.

I want to start our look at IMAPS 2015 with the presentation by the new Yole Developpement packaging team on the technology and market trends for WLP. You may wonder why I focus on this technology which was Leading Edge literally 20 years ago. Certainly it is near and dear to my heart since many of my most exciting days in technology were shared with the WLP pioneering groups at Flip Chip Technologies (FCT) and Microelectronics Center of NC / Unitive as this initial wafer level technology was being conceived and developed with my team developing BCB. These two small startup companies certainly were underdogs, and they were using my new dielectric, also an underdog, but within 2 years we were in nearly every cell phone made in the world.

Since it’s inception by Rajen Chanchani at the Boston IMAPS conference in 1994 to the commercialization of the UltraCSP by Pete Elenius of FCT in 1998, what was at first one of many chip sized package solutions evolved into wafer level chip scale packaging and then more simply into wafer level packaging or WLP.

[for a complete history of bumping and WLP see “On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging,” A. Huffman, P. Garrou, (link)]

By the early 2000’s it became obvious that WLP had unmatched advantages in both form factor and cost and the technology was quickly licensed by all the key OSATS and OEMs worldwide and adopted in nearly all mobile phone products. 20 years ago this was the leading edge and those working in the area and finding success felt like this [link]:

“Trying hard now…It’s so hard now…Trying hard now”

“Feeling strong now…won’t be long now…getting strong now”

“gonna fly now….flying high now…gonna fly…fly… fly ! “

Yole points out that although WLP has been seemingly out of the spotlight with the advent of higher density packaging solutions such as copper pillar bump, 2.5 & 3DIC and fan out and embedded packaging, WLP remains a highly important and constant presence. The mobile market continues to be the main driver for WLP with over 90% of all fan in packages being found in handsets and tablets.

Since the WLP eliminates the need for WB, substrates, FC bumps and in most cases mold compound, it still results in the shortest interconnects, lowest parasitics, and best electrical performance in terms of speed and frequency. Bump pitch of 0.35mm are currently in high volume production with 0.3 and 0.25mm under consideration. Most fan-in die are below 7 x 7mm and below 200 I/O. In general warpage and board level reliability for larger dies remains a concern. If your die is relatively small and your I/O demands relatively low, this is the best packaging solution.

Fan-in WPL units hit 35B in 2014 with a 9% CAGR. BT + WiFi + FM combos, CMOS image sensors and Rf transceivers account for ~ 50% of all WLP applications.

Yole has identified more than 70 high volume fabless and IDM companies implementing their designs in fan-in WLP along with over 20 fan-in manufacturing companies.

What the Future Holds for WLP

In the future IoT (Internet of Things) will eventually succeed mobile phones as the microelectronic driver…the big dog. However, there have been many unjustified presentations over the last few years detailing, without any support data, how IoT will drive leading edge, high end technologies like 3DIC. IFTLE does not agree with that conclusion but rather contends that IoT will be low I/O and will demand two things – small form factor and low, low cost. As such IoT will generate a huge potential market for fan-in WLP.

Back in the mid 1990’s, WL-CSP was an underdog who proved itself and became an integral part of cell phone manufacturing and, now after being somewhat overshadowed by newer leading edge technologies for a while, is about to make a comeback due to the inherent strengths of this technology. Anyone care to bet against it?

For all the latest in 3DIC and other advanced packaging technologies, stay linked to IFTLE…