By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the 2018 SMI ISS meeting, let’s take a look what John Hunt, ASE, had to say about the “Transformative Power of Fan-Out.”

Without question so called “fan-out packaging” has become the new packaging buzz word having replaced 3D-IC a few years ago. Focus on this technology has quickly (vs 3DIC) produced significant technical advances and led to broad commercialization. Although IFTLE has covered this technology in detail since its inception by Infineon, it is always good to review it one more time, which is what John Hunt did for the mostly front end folks assembled at Half Moon Bay.

Hunt’s slide shown below is an extension of the well worn slide showing why wafer level packaging developed with a low cost structure, i.e. the packaging was done on the wafer before dicing. Hunt contends, correctly, that the same is true for the WL FO WLP, though I would add that this also shows why the early eWLB structures from Infineon couldn’t get down low enough in cost for major market penetrations, i.e. the extra steps involved with creating the reconstituted wafer.

Fan Out Enables Multi Die Packages

• Advanced technology nodes increase wafer cost
• Fan out allows partitioning into different nodes
  • See DARPA CHIPS concepts in IFTLE 367 “DARPA CHIPS Headlines 14th 3D-ASIP Conf “
• Fan out allows partitioning of functionality
  • Digital, Analog, Components, MEMS, and IPDs

Fan out can be done either chips first or chips last as shown below. The newer chips first, face up (followed by planarization) and chips last options have resulted in much higher density interconnect which has allowed competition with some of the silicon 2.5D applications.

The high density fan out chip on substrate (FOCoS) is capable of 2/2.5um L/S and 4 metal layers as shown below:

 

Significantly thinner PoP can now be fabricated I much thinner formats:

In addition, they are still looking at moving FOWLP technology to large panel format in an attempt to continue to lower costs even further.

For all the latest in Advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the presentations given at the Semi ISS (Industry Strategy Symp) conference in January at Half Moon Bay.

VLSI Research

Lati of VLSI Research discussed “Market Opportunities in the Coming Technology Disruptions”

Six companies are now responsible for > 70% of Capex spending. Memory Capex hit $45B in 2017, more than 50% of total spending.

– Samsung accounted for more than half of DRAM spending in 2017. Other suppliers will have to respond with increased spending in 2018 to prevent share losses.

Semiconductor assembly equipment is expected to account for $5.2B in sales in 2018 with assembly equipment trends shown below.

 

Versum Materials

Novo of Versum Materials discussed “The Semiconductor Industry from a Materials Suppliers Perspective.” He listed the following forces acting on Materials suppliers:

Consolidation means fewer and much larger customers…

• Customer Centric vs. Market Centric model
• Higher pressure
• Access is critical for more limited POR opportunities
• Risk/Rewards are greater
• Too many suppliers for shrinking customer base

Shift to Asia requires footprint changes in terms of:

• Supply
• Distribution
• Innovation

Giga sized fabs mean:

• Greater Customer Expectations
• Implications of Winning/Losing
• Increased Ramp Complexity, Volume & Variability

They list the following as Criteria for Success in the 2020s:

IHS Markit

Jelenick of HIS Markit discussed Global Semiconductor Market Trends. Their breakout of the consumer electronics market by IC categories follows:

Electrification, automated driving and connectivity are expected to drive the growth in the automotive sector.

 

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The 14^th 3D ASIP Conference (3-D Architectures for Semiconductor Integration and Packaging) has officially ended. It was decided that the longest running focused 3DIC conference was no longer needed by the community since the technology is now fully commercialized in 3D memory stacks and numerous high end applications. For sure, there will be further advances in 3D, 2.5D and ancillary technologies, but it was felt that they could best be handled at your standard advanced packaging conferences. As they say “It’s best to go out when your still on top.”

3-D Architectures for Semiconductor Integration and Packaging, or 3D ASIP as it became known, started in 2004 sponsored by RTI International as a means of showcasing its wafer to wafer bonding technology being developed by spin out Ziptronix. Through the first 12 years it was organized under RTI’s Matt MeCray, who, although not a technologist in the area, developed the vision of having a conference on 2.5/3D technology focused on commercialization and business issues and focused on corporate and Institute “invitation only” presentations. For 14 years, hundreds of 3D practitioners assembled in Burlingame CA ( except for a 1 years hiatus in AZ) in early December to discuss the latest breakthroughs in the area. I joined the team as a program chair in 2008 working with Matt to define the programs content /speakers. After working with Matt for 7 years he moved on to do other things in RTI after the 2014 meeting. In 2016 RTI transferred the meeting to IMAPS where it has resided the past two years being chaired by Mark Scannell – Leti, Mitsu Koyanagi-Tohoku Univ. and myself. Below you will find some photos of those involved with the conference through the years and those who have served as program chairs.

A personal thank you to all presenters, who were a who’s who of the 2.5/3D world, and attendees. For me it was an enjoyable decade. I hope it was informative and enjoyable for all of you as well.

For all the latest on advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 14^th annual 3DASIP Conference.

K&S

Tom Strothmann of K&S discussed the requirements for HBM Memory Stacking. High Bandwidth Memory (HBM 1,2) are currently assembled using C2W compression bonding. Production is mostly done by memory suppliers as opposed to OSATS. HBM 3 is projected for 2019.

There are two prominent stacked die process flows:

• TC-CUF (Thermocompression with Capillary Underfill)
  • Die by die stacked using TCB
  • Die stack tacked followed by mass reflow
• TC-NCF (Thermocompression with Non-Conductive Film)
  • Stacked die by die using TCB
  • Die stack tacked followed by Collective Bond
  • Die stack tacked followed by Gang Bond

Cost reduction has focused on units/hr for the TCB process:

• Bondhead temperature ramp speed
• Target and die material handling systems
• Number of bondheads and accuracy requirements

Tacking has the potential to move machine UPH from 1700 to 3500 for a 4 die stacked process using NCF if a separate gang process is used.

 

TSV Die Stress and Warpage

• Silicon thinned to 50 microns during the via reveal process then has backside dielectrics and UBM applied
• Imbalanced stress resulting from the dielectrics, metals and pillars on the front of the wafer as compared to the back of the wafer causes warpage in the thinned silicon wafer
• Stress remains after dicing, resulting in die bowing that can be as much as 40um in a 9x9mm die

TCB with CUF Process

• TC-CUF processes have been used for stacked die production in HVM. Flux dip before placement followed by capillary underfill is a mature process.
• Typically lower throughput because the flux dip must be done below 100ºC to avoid premature activation of the flux. UPH >1000 is still possible during bonding with a dual head machine.

• TC-CUF die stacks have a narrow process window due to thin die warpage. Single die can be held flat during the bonding process , the next die in the stack does not. Heat is conducted through the thin silicon and Cu pillars into the die below, causng solder remelt and relaxation to original warped shape resulting in BLT variation. Since the top die is still held flat, this can create inconsistent bondline thickness throughout the stack.

TCB with NCF (non conductive film)

• NCF has the benefit of locking the BLT during the bonding process to enable a “flat die” process and more consistent bond lines
• TCB process can be optimized independent of die stack position
• Potential to remelt a lower die and change BLT is removed, enabling better process capability
• But…high forces may be required for bonding some layers based on die size and pillar count

As shown below the thickness of the NCF must be exact or the interface will suffer from particle entrapment or voiding.

Strothmann also offered the following opinions on alternative bonding approaches:

• Cu-Cu bonding is an area of active development work but is less likely to be applied to memory stacking in the near future
• Direct (hybrid) bonding of chip to wafer is unlikely for memory stacking

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

First introduced in June 2016, the Samsung HBM2 consists of eight 8Gb HBM2 dies and a buffer die at the bottom of the stack, vertically interconnected by TSVs and µbumps. With each die containing over 5,000 TSVs, a single Samsung 8GB HBM2 package has over 40,000 TSVs. Including spares TSVs ensures high performance, by enabling data paths to be switched to different TSVs when a delay in data transmission occurs. The HBM2 is also designed to prevent overheating beyond certain temperature to guarantee high reliability. The HBM2 reports a 256GB/s data transmission bandwidth, offering more than an 8X increase over a 32GB/s GDDR5 DRAM chip. With capacity double that of 4GB HBM2, the 8GB solution contributes greatly to improving system performance and energy efficiency, offering ideal upgrades to data-intensive, high-end computing (HPC) applications that deal with machine learning and graphics processing .

Last week Samsung announced that it has started mass production of its 2nd-generation 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) with the fastest data transmission speed on the market today.[link] Dubbed “Aquabolt”, it is claimed to be the industry’s first HBM2 to deliver a 2.4 gigabits-per-second (Gbps) data transfer speed per pin, at 1.2V for the supercomputing and the graphics card market.

This performance is reportedly 50% greater than the 1st-generation 8GB HBM2 package with its 1.6Gbps pin speed at 1.2V and 2.0Gbps at 1.35V.

A single Samsung 8GB HBM2 package will offer a 307 GBps data bandwidth, achieving 9.6 times faster data transmission than an 8 gigabit (Gb) GDDR5 chip, which provides a 32GBps data bandwidth. Using four of the new HBM2 packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth.

In addition, Samsung increased the number of thermal bumps between the HBM2 dies, enabling better thermal control in each package. The new HBM2 also includes an additional protective layer at the bottom, which increases the package’s overall physical strength.

 

Continuing our look at the presentations at the 14 3D ASIP Conference.

Micross – Ultra Fine Pitch Interconnect

Matt Lueck of Micross gave a presentation on their Ultra fine pith interconnect technologies that are being used in their Northrup Grumman (NGC) DARPA CHIPS program discussed in IFTLE 367 [link].

Fine pitch (< 80 um), Cu pillar thermo-compression bonding (TCB) has been widely adopted for advanced packaging of stacked memory and many other applications. Major foundries and assembly houses are offering Cu pillar down to 30 – 50µm pitch with 20 – 30µm pitch in development. Availability of fine pitch Cu pillar bumping from foundries and OSATs are limited to high volume customers and off-shore processing.

Micross has been developing fine pitch technologies over the years under their previous ownership ( Microelectronic Consortium of NC (MCNC) and Research Triangle Institute (RTI). They re positioning themselves as a source for prototype and small volume production of such ultra high pitch interconnect.

They have used 10µm pitch Cu/Sn – Cu bonding in multiple programs since 2007 such as large area array detector applications. They report that such interconnect have shown proven reliability, even for heterogeneous integration with CTE mismatch issues.

• For next generation area array imaging applications, sub-10 µm pitch electrical interconnects are desired between detector chip and ROIC
• A process for the fabrication and bonding of 5 µm pitch Cu-Cu interconnects was demonstrated
• I-V curves indicate ohmic behavior of interconnect chains
• Leakage current measurements indicate > 100 GΩ isolation between adjacent channels of interconnects
• Demonstrated high yield on 1280 x 1024 array sample

Working with NGC they are developing 4 – 10µm pitch gold-gold bonding technology. The evaporated gold bumps show RMS roughness of 3.7-3.9nm.

BESI- Thin Die Pick and Place

Stefan Behler of Besi discussed “How to peel Ultra this dies from Wafer tape”

Behler describes 4 key properties as shown below:

(1) Wafer foil peel force depends on the foil type and the peel speed as shown in table below.

(2) edge peel force depends on the dicing method

(3) Bending stress depends on the Ejector type with thinned die resulting in more bending stress.

 

(4) die strength appears (measured by 3 point bending test) is almost independent of thickness but is dependent on :

• surface (active structure)
• backside (grinding, polishing…)
• edges (dicing)

For all the latest in Advanced Packaging, stay linked to IFTLE…