By Dr. Phil Garrou, Contributing Editor

Sony had some interesting things to say about their semiconductor and imaging technology businesses at their recent investor relations day May 22^nd in Tokyo. As the industry moves forward to 5G, they seek to provide both hardware solutions and content services. Probably most startling to those in attendance appeared to be their announcement of a major focus on their mobile smartphone business.

Shigeki Ishizuka, Exec VP of Imaging products and mobile communications business discussed their theme of “light to display” as shown below. Imaging products and solutions is currently a 660B Yen business for Sony.

Their key applications for real time broadcasting include not only sporting events and concerts but also business to business communications, the education market which they call “active learning solutions” and medical room imaging solutions.

The medical business is described below and consists of both surgical imaging and life sciences.

Their newly developed 3D surgical microscope allows doctors to operate without looking into the eye lenses of the microscope and the image can be shared real time with the whole operating team.

In the mobile communications segment Sony smartphone (Xperia) unit sales have decreasing since 2014 (see below). They will now focus on 5G phone solutions to revive their business position in that segment.

They will be seeking to advance smartphone competitiveness vs the industry leaders by bringing all their internal technology and their external partnerships to bear. They expressed a need to especially improve the design.

Post presentations, most of the questions focused on this announcement of increased focus on the mobile segment. When questioned about whether 5G mobile was an area that they HAD to be in, Sony answered that the technology hurdle for 5G is “quite high” including antenna technology “…. multi antenna array for beam focusing and switching has never happened before….high technology solutions are needed…its not like you can purchase an LSI chip and write some software and develop a solution…we will have to acquire these solutions and mature them” IFTLE assumes this answer was meant to mean that this is not likely to be a commodity product and would require the technical expertise that only companies of Sony’s stature could deliver.

When asked whether it was logical to focus on smartphones where Sony now has less than 1% market share they answered that “…with respect to smartphones the share is low-right- that’s a pity…we don’t have much product offering and product capability is very low….” The rest of the answer did not clearly explain how they intended to turn this around other than they awould be focusing all their internal technical expertise on solving this problem.

It will be interesting to see if Sony can really become competitive with the likes of Samsung and Apple in the future 5G arena.

For all the latest in advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

At the recent IMAPS Device Packaging Conference outside Phoenix Hamid Eslampour, CMOS BU Product Management, of GlobalFoundries (GF) discussed Advanced Packaging in the Foundry Space.

Eslampour indicated that todays networking, machine learning, and other high-end computing applications have created the need for architectures that allow for processing of massive amount of data located in nearby memory through communication with the CPU/ GPU with low latency, parallel processing, and high data rate.

To enable these solutions, advanced Si nodes with High-Speed-SERDES (HSS), enhanced HBM-PHY, and highly integrated package technologies are required. The packaging solutions they see providing the level of integration required include MCM, 2.5D, and 3D.

The challenge for foundries such as GF is to enable these solutions through co-design with the customer within a business model that provides the package design, technology integration, and OSAT manufacturing processes required.

High bandwidth and high performance computing technologies for silicon and packaging are shown below. Such high performance devices will require < 40um pitch copper pillar bumping and fine line interconnect (< 10/10 L/S).

14nm designs are in customer development with 7nm and beyond designs in pathfinding.

Current GF interposer capabilities are shown below and include 10um TSV on 40um pitch, up to 3 metal layers of 0.8um L/S interconnect:

GF has the following supply chain in place:

Higher bandwidth trends drive higher number of HBM stacks, larger silicon interposers and larger power dissipation issues.

For all the latest on Advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

China is by far the largest consumer of semiconductors reportedly accounting for 45 percent of the worldwide demand for chips, used both in China and for exports. More than 90 percent of its consumption relies on imported ICs.

At the end of 2016 IC Insights reported that China was responsible for ~ 11% of the worlds wafer capacity.

China has been working to reduce its dependence on technology imports, including computer chips for several years. In March, it was reported that state-backed China Integrated Circuit Industry Investment Fund Co. is in talks with government agencies to raise at least $24B to build up China’s domestic semiconductor industry. Recently, the Wall Street Journal reported that China is poised to announce a new fund of ~ $47B for development of its semiconductor industry and close the technology gap with the U.S. and other rivals.[link]

While the existence of such a fund has been rumored for months, the size of the fund has been hard to pin down. A few weeks ago, Reuters reported that the fund would be $19B, while Bloomberg reported $31.5B two months ago. The exact number appears to be under consideration among the Chinese leadership, and tied to the increasingly tense trade negotiations with the United States. If $47B is indeed the correct number, it would be identical in size to the $47 billion fund that was financed by Tsinghua University, to spur the development of an indigenous semiconductor industry back in 2015.

While China is playing catchup in many semiconductor areas, it has also been placing its bets on new areas like 5G wireless and AI (artificial intelligence) chips. [link].

China releases its first cloud AI chip

Beijing artificial intelligence (AI) chip maker Cambricon Technologies Corp Ltd has just announced two new products, a cloud-based smart chip Cambricon MLU100 and a new version of its AI processor, Cambricon 1M, in Shanghai on May 3^rd.

The cloud chip MLU100, developed by China’s Cambricon Technology, is China’s first cloud artificial intelligence (AI) chip developed to have big data processing ability, for image and voice searching [link].

Cambricon 1M is the company’s third generation AI chip (gen 1 was in 2015) for “edge devices.” An edge device is a device which provides an entry point into enterprise or service provider networks such as routers, routing switches, integrated access devices (IADs), multiplexers, and WAN (wide area network) access devices. Using TSMC 7nm technology, the AI chip can be used in smartphones, smart speakers, cameras, and smart driving.

Cambricon MLU100 supports cloud-based machine learning, including vision, audio and natural language processing. It can process under complex scenarios, such as “…with huge amounts of data, multi-tasks, multi-modality and low latency.” This processor reportedly can provide 166 TFLOPS in high-performance mode with energy consumption of no more than 110 watts at peak. The MLU100 is built with TSMC 16nm technology.

Lenovo has announced that their ThinkSystem SR650 server is based on the MLU100. Products built around MLU100 were also announced by Sugon and iFlytek who also announced collaboration with Cambricon [link]

For all the latest on Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

TSMC Introduces WoW Technology

At the TSMC Technology Symposium in Santa Clara, the company discussed their new Wafer-on-Wafer (WOW) silicon wafer stacking technology for the 7 and 5nm nodes. The “new” technology connects chips on two silicon wafers reportedly using 10um TSV. Those of us who have been following 3DIC for over a decade recognize this as W2W 3DIC. Even the name isn’t new, since Fujitsu introduced their version of WoW technology in 2010 which we discussed way back in in IFTLE 181.

TSMC first teased us with this potential technology back in 2014 at the IEEE IEDM.

The TSMC technology stacks and interconnects die while still part of the full silicon wafers vs their previous 2.5D technology CoWoS that uses silicon interposers. The advantage is obviously that this tech connects all die on two wafers in one process step. In terms of performance, direct 3D stacking has always been known as the highest performance lowest latency solution.
As we have known for a decade at least, there are several issues with W2W technology: (1) yield – bad die on wafer 1 will be connected to good die on wafer 2 resulting in a bad stack. This precludes this technology from being a viable solution for silicon that doesn’t already offer high wafer yields. Ideally, TSMC reports that chip yields should be 90% or higher to use TSMC’s Wafer-on-Wafer technology. (2) quite obviously this technology is most relevant for low-power silicon, where heat is less of an issue and (3) Also importantly, readers of IFTLE know that this solution works best for chips that are identical like memory stacking, but not for ships of different sizes and different I/O configurations which would require redistribution (RDL) before alignment and stacking is possible, thus increasing cost.

So far, TSMC has reportedly achieved “2-layer stacks, in which two silicon layers that are mirror images of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.”

Since TSMC currently manufactures graphics cards for both AMD and Nvidia and there are some predicting that we will see stacked GPUs from the WoW technology. “There won’t be latency problems between the connected GPUs as the wafer has the ability to let the GPUs communicate quickly, meaning we could see dual-GPU graphics cards based on current GPUs like the Polaris and Pascal GPUs from AMD and NVIDIA, respectively.” [link]

Certainly they wouldn’t be hyping the technology if there weren’t real customers urging them to move forward with it. It will be interesting to see if they give a more complete description of WoW at the IEEE ECTC in a few weeks. If so be sure that IFTLE will get you the details.

What about designing these complicated structures ??

Cadence Teams with TSMC for full WoW Design Flow

Cadence has announced that its full suite of Cadence digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology. [link]

Cadence announced a new WoW reference flow to complement their other TSMC integration solutions ( InFO and CoWoS). They described the following design flows, tools and methodologies that will enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process as follows:

• Innovus™ Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
• Quantus™ Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
• Voltus™ IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
• Tempus™ Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
• Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
• Virtuoso^® Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
• OrbitIO™ interconnect designer: Provides interface connectivity,  device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
• Sigrity™ PowerSI^® 3D-EM Extraction Option: Offers electrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
• Sigrity PowerDC™ technology: Thermal analysis solution with interposer and die analysis capabilities that allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
• Sigrity XcitePI™ Extraction:  Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
• Sigrity SystemSI™ technology: Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation

For all the latest on Advanced Packaging, stay linked to IFTLE…