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Monthly Archives: June 2013

IFTLE 152 2013 IMAPS Device Packaging Conference part 2

Continuing with our coverage of the March IMAPS DPC.

TI

In his keynote presentation on semiconductor packaging trends Devan Iyer of TI showed  a great chart on package shrinkage through the years. We have moved from the 1.75mm SOIC to the picostar 2G at 0.075mm which they claim to be the thinnest package available for portable products and can be buried into PCB layers . 

 

 Iyer  also listed the following packaging challenges for materials and assembly.

 
APSTL
Dev  Gupta of APSTL  examined  “Stacked package with improved bandwidth and power efficiency” . His conclusions are  based on the assumption that 2.5/3D technology is still immature and high cost and not ready for adoption in consumer products like smart phones. He is a proponent of what he calls “super PoP” packages.
He points to the recent presentations by JEDEC which indicated that TSV based wide IO would be an option for 2015 but would find strong competition in LPDDR4. { For further discussion of this issue see IFTLE 134,  “SEMI 3D European Summit – Is the Wide IO Driver Dead ?” ]
 
Gupta claims that the issues for Pop arise from increased power loss due to parasitics in the package and that this can be cured by inserting “signal conditioning chips “ (442)
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Nanium
Nanium announced that they were installing  30mm WL fan in technology (Spheron PBO technology from Flip Chip Int) to compliment their WL fan out technology already in place.
Corning
Corning discussed their 3D carrier glass substrates used in the wafer thinning process. 
They supply glass carriers for the 3M temp bond / debond process. Their fusion glass process results in surfaces with RMS 0.3nm; Ra 0.2 nm and Z range 4.2nm which is better than lapped and polished glass.
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200 & 300 mm wafers cut out of a sheet. 450 will not be a problem and panels are ready when the industry becomes ready to use them.
They are using alumino-silicate glass (SGW3) to match CTE od Si from 0 – 300 C.  This CTE match keeps warpage very low. Corning pointed out that measuring TTV on these wafers is difficult and that reports in the literature of 1 um TTV are sometimes as far off as 5 um.
Recycling glass wafers depends on all process perameters, but in general they envision  15 recycles as doable.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE………….
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IFTLE 151 2013 IMAPS Device Packaging Conf part 1 – Amkor

I’ll be interspersing reports from DPC with ECTC and ICEP reports so pay attention as to where the material over the summer is coming from. In addition I will be covering ConFab and Semicon West so there will be a lot of information coming your way.

The IMAPS DPC , Proceedings and the Literature Search Problem

We are finally getting around to taking a look at the March IMAPS  Device Pkging Conference. Actually it is officially listed as a workshop, which to IFTLE is inappropriate since it runs 3 parallel sessions for 2 ½ days and has a very large exhibit tied to it. It seems the driving force to not change is that SOME don’t want to write up their papers for a proceedings which would be required if it were officially a conference. These are probably the same authors who don’t ever hand in, or take 2+ months to turn in , their slides. When I was general chair I tried twice to require a proceedings and was voted down twice, so don’t blame me !

In the end its all about literature searching. We all have become so accustomed to using Google scholar that if it doesn’t show up there we just ignore it. If I don’t have a copy of a specific proceedings and its papers don’t show up in Google Scholar basically the material does not exist. Sure I can go to each societies web page, and become a member and then search their archives but how many of us do ? Right now that means we all reference quite a bit of literature from IEEE explore because Google indexes it and our companies / institutions pay to access it.

Other societies need to make sure their material is archival and searchable otherwise after a few years it is really lost. I know IMAPS specifically is working on this problem and I hope all the other societies are too.

IMAPS DPC – AMKOR

Lets start our DPC look with presentations from Amkor. Being close by in AZ, Amkor always brings a strong contingent to the DPC.

Amkor discussed their thermo compression non conductive paste process for formation of copper pillar bumps. Copper pillar bumping achieves better electrical performance as well as smaller packages with lower standoff heights. It is also expected to lower costs by reducing substrate layer counts. The bump process flow is shown below:

 
The assembly process for thermocompression bonding with non conductive paste (TCNCP) is shown below. Key to the assembly process is control of the peak heating temp and the heating time.
 
 
 


Amkor also discussed mold shrinkage and die stress effects on FC molded BGAs.
 
FCBGA can be molded using either mold compound or molded underfill. Schematic of molding is sown below. Increased shrinkage increases both  tensile and shear stresses.
Stresses are concentrated in the mold/ die interface in the mid section of the die.  The rubber insert used to protect the die surface creates a grove in the top of the molded surface. This grove controls the stress on the overall package and this package warpage.
 

Kelly of Amkor  discussed “Assembly challenges for 2.5D”. Their latest roadmap now shows memory + logic modules pushed back to the 2014 – 2015 timeframe.

 
Their TSV manufacturing experience base is based on :

 
High performance products now look like they are coming in 2014 – 2015 with smart phone % tablets coming in 2015+ as prices come down
Amkor has been engaged with > 10 top tier customers with > 20K parts built. There has been a  large package  focus (> 40mm) . While the slides showed interposers from 3 different “foundries” upon questioning they admitted that TSMC is delivering and the other two (Global and UMC) are close.
Process technology
– Their copper pillar bump process is on 40-45um for most customers roadmaps.
– for die joining  mass reflow is preferred but warpage must be well under control. TC bonding is an option for higher die warpage.  TCNCP can be used for small die and CUF for larger die.
– backside passivation must be mechanically stable, good adhesion to underfill and provide warpage control. In the Q&A session they indicated that they preferred inorganic backside dielectric “â??¦sometimes with a final organic cap” indicating that the “â??¦backside oxide must be incredibly mechanically robust. “
– Interposer top side to bottom side die interfaces must be flat in order to assemble.
– Need to know top side stress on incoming wafers in order to properly assemble.
– memory stacks are pretested
Comparison of 3 assembly flows is given below

 
For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


IFTLE 150 ICEP Osaka part 1

The Int Symp on Electronic Packaging was held in Osaka the week of April 10th with keynote

speakers, Dr. Subramanian S. Iyer of IBM, Dr. Takeshi Uenoyama of Panasonic, and Dr. Urmi Ray of Qualcomm. General Chair was Shintao  Yamamichi of Renesas and Technical program Chair was Hitoshi Sakamoto was NEC.

 There were 180 papers and over 20 posters. Major topics were: Advanced Packaging, Substrate & Interposer, 2.5D and 3DIC Packaging, Design/Modeling/Reliability, Thermal Management, Materials and Process, Printed Electronics, N-MEMS, Optoelectronics, Power Devices, and Biomimetics. In addition, the Japan ASET consortium, Taiwan and Korea held special sessions. IFTLE will cover key presentations over the next few weeks.  

 
ASET SPECIAL SESSION

 Lets first take a look at the ASET special session. The ASET “Dream Chip” program has recently ended in Japan.


Sueoka and co-workers described their proposal for “High Precision Bonding for Fine Pitch Interconnection”. Bonding fine pitch interconnect requires consideration of the factors which degrade the alignment accuracy such as:

– thermal expansion of the machinery

– surface topologies of the chip an substrate

 The were able to bond 10um pitch bumps (see figure) using a flip chip bonder equipped with infrared alignment optics they found that they could observe alignment marks and adjust the chip position during the bonding process, even when the solder was molten. Most importantly they could eliminate the miss-alignment caused by joining non flat chips an due to thermal expansion of the tool head.

This dynamic alignment bonding scheme consists of 4 steps:

(1) pre-align for the approach of the chip to the substrate

(2) small gap align with IR light
(3) correct alignment for offsets caused by impact of the chip touching the substrate
(4) final align during the bonding while the solder is molten.

 



  Renesas and IBM Japan described “3D Package Assembly Development with the use of Dicing Tape Having NCF Layer”.

 Dicing and stacking are important technologies n 3DIC assembly. Bumps on the wafer backside make it difficult for general dicing tape to achieve both high quality dicing and pickup. For tight pitch, small bump bonding it is also difficult to inject underfill into the narrow gap between the dies.  

General dicing tape cannot burry the bumps and thus fully fix the die. This causes chipping and cracking of the die during dicing. If you increase the tapes thickness to fully burry the bumps, die pickup becomes difficult. Process flow is shown below.

 
ASET studied a new ICF tape from Nitto Denko. The tape has a NCF layer (non conductive film) on the dicing tape.  Since this NCF layer ends up staying in the gap as underfill, they call this Inner chip film or ICF (just what we need more acronyms !)  Hot lamination of the tape to the wafer will burry the backside bump. Wafer and NCF layer are diced together. The die pick up becomes easy since the required separation is between the ICF and the dicing tape adhesive.
 
 
The new process using ICF tape is shown below.
 
 

 

Hozawa and ASET co-workers at ASET described their “3D Integration Technology using Hybrid Wafer Bonding and its Electrical Characteristics”. In this study ASET examined 3D integration with vias last. Vias last was examined because it needs no modification of the front end process. The test structure and target specs are shown below.
 
 
 The process flow consists of: TSV formation; bump/contact ad formation; substrate thinning and stacking.
They examined W2W bonding and thinning after bonding as process flows.
 
Hybrid bonding was chosen where Cu-Cu and polymer – polymer bonding (they used PBO)  occur at the same interface. Hybrid bonding provides both strong metal bonding and reliable polymer underfilling simultaneously.

 
 
In the full process sequence a silicon interposer wafer and the first device wafer are bonded F2F with hybrid bonding. After backside thinning the first device wafer, TSV formation and backside bumping the second device wafer  is bonded to the stack B2F. Lastly the silicon interposer is thinned, TSV formed and bumps attached.
To achieve good CU-Cu bonding in the hybrid bonding “hydrogen radical” treatment of the Cu surface was necessary. When they tried plasma treatment it damages the PBO surface. A cross section of the interface is shown below.
 
 

Serial resistance of a 3 layer connection (2 TSV, 1 Cu-Cu bond, 1 Cu-TSV bond) is under
0.5Ω.
 For all the latest on 3DIC and advanced packaging stay linked to  IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦..
 
 
 
 
 
 

 


IFTLE 149 2013 ECTC part 1

The undisputed Jewel of IC packaging conferences, the  ECTC (Electronic Component Technology Conference) took place this past week in Las Vegas with 1300+ attendees, 95 exhibitors and IFTLE in attendance.

Over 600 submitted abstracts resulted in ~300 presentations (verbal and poster) and the highest rejection rate in the industry.  Key to this years conference success were Program Chair Beth Keser from Qualcomm, General Chair Wolfgang Sauter from IBM,  and Assistant Program Chair Alan Huffman from RTI Int.

 
Beth Keser, Wolfgang Sauter and Alan Huffman from the ECTC Program Committee
John Lau Wins IEEE CPMT Field Award
Awards are an important part of this yearly conference and the pre-imminent packaging award is IEEE CPMT’s (Component, Packaging and Manufacturing Technology Society) “Field Award”  Past years winners include Rao Tummala (packaging), Yutaka Tsukada (underfilling),  Paul Totta (bumping); Herb Reichl (packaging); George Harman (wire bonding), Dimitri Grabbe (connectors) and CP Wong (polymers).
 
This years winner Is Dr. John Lau, currently a Fellow at ITRI. Best known for his extensive work in solder joint reliability, anyone who has a few packaging books on their bookshelf probably has one of Johns. One of my personal favorites is his chip on Board volume published in the 1990’s. If I am remembering correctly, John once told me that his daughter Judy designed the cover.
 
 
 
 
 
Bill Chen (ASE), CP Wong ( GaTech ), John Lau ,wife Theresa and daughter Judy Celebrate his award
Other major award winners included:
Outstanding Contribution Award – Rolf Aschenbrenner, Fraunhoffer IZM Berlin
Outstanding  Sustained Technical Contributions Award – Dongkai Shangguan, National Center for Advanced  Packaging – China
 
Exceptional Technical Achievement Award –  Yong Liu, Fairchild
Electronic Manufacturing Technology Award – Louie Huang, ASE
This years event was also loaded with  panel sessions including  Broadcom’s Sam Karikalan chairing “The role of Wafer Foundries in the Next Gen Packaging”; CPMT President Ricky Lee of Hong Kong Univ of Science and Techniology, chairing “LEDs for Solid State Lighting” ( Lester Lightbulb was seen in tears after he was informed that he was not selected to speak on this panel ); Amkor’s Lou Nichols chairing “Packaging Challenges  Across the Wireless Supply Chain” and   Fujitsu’s Yocouchi-san chairing “Low Loss Dielectrics for High Frequency and High Bandwidth”
Without question the leading theme at this years conference was once again 3DIC. I counted at least 12 sessions and numerous posters that dealt with the various components of 2.5 and 3D technology. 
3DIC Status
There were no major commercial announcements or major technology advances in 3DIC.  Presentations tended to show  slow steady movement forward for both 3D and advanced packaging in general. Over the next few weeks we will discuss this further and will take a look at some of the more interesting presentations at this years ECTC.
IFTLE also thanks Cornelia Tsang of IBM for guarding his seat during the ECTC gala celebration ! (inside joke)
For all the latest on Advanced Packaging and 3DIC stay linked to IFTLEâ??¦â??¦â??¦â??¦