By Dr. Phil Garrou, Contributing Editor

Fab Construction Declining, New Construction be mainly in China.

Over the last few years, IFTLE has detailed the slowdown in scaling which is leading to the construction of fewer and fewer latest node fabs. We have also noted that this maturity of our industry has led to the consolidation trend that has been so prevalent the past few years.

Peter Clarke of EE Times Europe recently reported the latest SEMI data on new fab construction [link]. They predict 19 wafer fab starts in 2016 and 2017 and predict that China, will be responsible for more than half of them. This is a low total number by historical standards consistent with our trend of slowdown.

(12) of the fabs are 300mm, (4) are 200mm, and the (3) LED fabs are 150mm, 100mm, and 50mm respectively. Activity in the 3D NAND, 10nm logic, and foundry segments is expected to push equipment spending up 1.5% globally vs 2015. Fab equipment spending declined by 2 percent in 2015. SEMI lists a probability 60% or higher for these predictions but admits that some may be delayed.

The heavy participation by China is also consistent with IFLE noting that China would be the Wild card when it comes to future IC production (see “IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card” [link]).

SEMI estimates far more manufacturers are looking at fab upgrades or facility conversions as shown in the table below. IFTLE agrees that this is likely the way of the future.

Continuing our look at the 2016 ECTC

Wafer Level Integrated Fan Out Packaging (InFO) – TSMC

IFTLE has stated over and over that the front end practitioners are paying more and more attention to packaging because they understand that it is the future way of customizing a circuit and could have more value in the long run than further scaling. (At least till the CMOS replacement is found sometime in the future). This was never made clearer than by the rumors that TSMC had been selected as Apple’s exclusive manufacturer for this year’s A10 chip expected to power the iPhone 7 and new iPad models. “The new chip is expected to use a 16nm process combined with a new InFO packaging, which allows chips to be stacked on top of each other and mounted directly to a circuit board, instead of onto a substrate first, reducing both the thickness and the weight of devices. Apple is rumored to be TSMC’s first customer to use InFo.”[link]

In fact it is likely that this was also a main motivation for Samsung EM’s recent announcement that they would be entering the FO-WLP business by the end of the year.( see IFTLE 291 : “Samsung EM enters FO-WLP Packaging Mkt…” [link] ).

Session 1 paper 1 at the 2016 ECTC was a TSMC paper on InFO by Doug Yu and his team at TSMC. Up until a few years ago, Doug had been the key technology Mgr developing the latest front end copper low K interconnect for each succeeding scaling generation at TSMC. He now runs 2.5D and wafer level packaging like InFO…does that tell you anything ? I think it does.

Since they first indicated that InFO was on their radar , ~ 2012, TSMC has focused on presenting comparative data showing the better performance that InFO would deliver vs other options. This latest paper continues in that venue comparing the form factor and performance advantages of InFO PoP over std FC-PoP. What’s been missing from the InFO presentations has been any detail on the process flow. (see IFTLE 261: “….The info on InFO…” [link].

In IFTLE 261, we reported on a rumored InFO process flow which consists of (1)copper pillar plating on the die,(2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging comes from the more planar starting surfaces and better control of the photo processes.

A prevalent rumor going around ECTC is that ASE will become the second source of InFO technology for the industry. Does this make sense ? Well ASE is known to be a preferred partner for TSMC packaging and ASE has won its own Apple contracts for supplying SiP for the Apple watch (see IFTLE 238: “ASE & the Apple watch…” [link]). So yes I’d say this is plausible.

In addition ASE and DECA have just announced that ASE has licensed the DECA FO technology and will be putting in a line to manufacture it. [link]

Is it logical that ASE is about to scale up two different fan out packages at the same time ?…..probably not.

It is more logical if the TSMC process and the DECA process are similar enough that this really constitutes only ONE line for both products.

The DECA process flow (as published in the 2013 IWLPC) is shown below.

Enough said…

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Samsung Electro-Mechanics launches IC packaging business

Reports are that Samsung EM (Electro-Mechanics), part of the Samsung Group, is entering the integrated circuit packaging business [link]

Samsung Electronics system LSI and Samsung Electro-Mechanics will join forces to staff the project and launch the business. They will transform current LCD assembly lines in Cheonnan KR into IC packaging lines. It is unclear whether they have developed full panel processing capability which many packaging OSATS have been trying to accomplish, or they will work in smaller formats.

Certainly their goal is to supply both Samsung and win the business of smartphone makers, like U.S.-based Apple. Apple recently gave a large order to Samsung’s competitor TSMC who will be using their InFO based FO-WLP packaging technology in Apples next smartphone.

Samsung EM has announced that they will be packaging power management ICs with Fan-out Wafer Level Package (FO-WLP) in their new factories.

IFTLE speculates that Samsung EM, a major provider of high density substrates also saw that FO-WLP was going to, or already has, begun to eat into their high density substrate business since FO-WLP can do the same job at a lower cost.

Plans are for the packaging factories to be operational in the first half of 2017.

Continuing our look at the 2016 ECTC

X-Celeprint & RTI Int Propose FO-WLP Free of Mold Compound for sub mm ICs

Closing out the morning for the “Advances in Fan Out Packaging” session at the 2016 ECTC, Matt Lueck of RTI Int discussed the results of their joint program with X-Celeprint.

A common aspect to all fan-out packaging is the requirement to physically assemble devices into dispersed arrays, often called reconfigured wafers, which provides the real estate needed to fan-out. Devices made in sub-mm chip sizes can impose cost and performance challenges to FO-WLP using serial pick-and place assembly technologies. RTI and X-Celeprint joined forces to develop a fan out package for sub mm IC using the X-Celeprint massively parallel assembly technology called micro transfer-printing, which is well-suited for handling very thin and fragile devices.

In their micro transfer-printing technology a polymer layer is first applied to the substrate before the assembly process, and the devices are assembled in a face-up configuration. Following the formation of the reconfigured substrates, conventional redistribution layer (RDL) and solder ball processing was performed. Two different photoimageable spin on dielectrics, HD4100 PI and Intervia 8023 epoxy,

were used as the RDL dielectrics. The fan-out package contains no molding compound and is made using standard wafer-level packaging tools.

There are potential benefits from fan-out packaging strategies that do not require molding compound. The process described here does not suffer from the “die drift” that occurs during compression molded fan-out packaging which often requires special adaptive alignment techniques. It also does not suffer from the wafer and package warpage that can occur in molding compound based fan-out packages.

Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.

In the figure below shows (A) the chiplet source wafer after partial removal of chiplets with the elastomer stamp; (B) a completed fan out package before solder ball placement; (C) close-up of the interconnect to the chi pads; (D) Final FO-WLP

 

Initial yields are reported to be 97%.

Two PCB test vehicles populated with 60 die each were built for thermal cycle testing. The board level thermal cycle testing was run under -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

More on the ASE / SPIL “holding company”

In IFTLE 289, I described the formation of a holding company to reach a peaceful merger of ASE and SPIL. After a week at the recent ECTC, I have concluded that maybe the merger will not be so peaceful after all. Rumors abound that SPIL is still not a happy camper.

While both sides are awaiting legal Oks, reportedly from Taiwan, China and the US, I hear that the holding company board will be composed of 14 members. 9 will be from ASE, 2 from SPIL and 3 from the outside. Hummm…….still sounds like an acquisition to me. Wonder who will be running the show in this operation? If anyone feels that is not correct, feel free to comment.

No Resisting Consolidation

My blogs on consolidation in the Microelectronics industry started way back in the predecessor to IFTLE, perspectives from the leading edge or PFTLE, which ran for > 3 years in Semiconductor International. When I saw AMAT making acquisitions of back end of line equipment companies it became clear that consolidation was underway.

In IFTLE 195 (June of 2014), I explained the 4 stages of a Business cycle as discussed thoroughly in the Harvard Business Review. These stages have held true throughout history for planes, trains and automobiles and every other industry that has ever existed on this planet. Microelectronics is no exception, it is not beyond the control of the basic laws of economics.

The best examples of this in our industry has been DRAM and hard disk drives. They have run their course and arrived at stage 4 of the business cycle where the top 3 companies claim 70-90% of the market. It was inevitable and it happened.

Our growth rate for many segments of the industry are now following the GDP (i.e we are a mature industry in stage 4 of the business cycle) as shown in the IC Insights slide presented at the recent IMAPS Device Packaging Conference. IC growth is now 96% in correlation with GDP.

 

The 4 stages of the business cycle notes that growth for stage 4 companies must come from spinning off new businesses or buying into aligned fields. In our case that may be the front end buying up the back end and/or foundries buying up the “lucrative segments” of the packaging industry. This will also hold true for materials and equipment suppliers, conferences and everything else in our microelectronics infrastructure.

Supplier consolidation was evident at the ECTC exhibits this past week. Going past the Dow Chemical, Dow Corning and HD Micro booths it struck me that next year there may be only be one booth and probably fewer attendees from the newly merged company (assuming the legal hurdles are met). While Dow Corning (the JV between Dow and Corning Glass) was included in this merger of equals, it is currently unclear what happens to HD Micro (the Hitachi Dupont PI JV) . While Dupont and Hitachi were never really competitors in the rest of their electronics business, Hitachi and Dow are (mainly through the R&H operation now part of Dow). So will Hitachi or Dow/Dupont buy out the HD JV ?? or will it just stay as it is?? No one seems to have that answer.

ECTC 2016 the 66^th ECTC

Alan Huffman of RTI Int. presided as the General Chair of the 66^th ECTC Conference in Las Vegas week before last. The ECTC Conference is the flagship conference of the Components, Packaging and Manufacturing Technologies (CPMT) society of IEEE. That name is a mouthful that none but the members really understand. Many favor a simpler name like the “Electronics Packaging Society”, which, at a high level, really fully describes what it is. This Conference is the undisputed leader in all things packaging. While most other conferences struggle to get the number of presentations necessary to put on their shows, ECTC routinely turns away > 50% of submissions. If you want to know what’s going on everywhere in the world, in electronic packaging, this is the place to be.

It was started the year after I was born and had been jointly owned by IEEE CPMT and the EIA (Electronic Industry Association) till Bill Chen and I, under our CPMT Presidencies bought out the EIA. That’s was a deal that we both are very proud of. It is certainly our legacy to the organization.

Anyway, this years 36 sessions, courses and exhibits covered the entire Microelectronic packaging infrastructure. I will be sharing what I consider key presentations with you for the next few weeks.

2016 CPMT Field Award – Michael Pecht UMD

The highest award honoring technical achievement in electronic packaging is the IEEE Components, Packaging and Manufacturing Technology Society Award – an IEEE Technical Field Award, sponsored by the CPMT Society and administered by the IEEE Awards Board. Past winners include Rao Tummala, CP Wong, John Lau, Herb Reichl, Avi Bar-Cohen, George Harman, Demitri Grabbe and Paul Totta. If you don’t know who any of these leaders are, you need to do more reading in the area. This year’s winner is Michael Pecht from Univ. of Maryland where he runs the Center for Advanced Life Cycle Engineering and has been a leader in physics-of-failure based electronic reliability. IFTLE salutes Professor Pecht who truly belongs in this elite group.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

ASE & SPIL find a non hostile Solution

When the ASE acquisition of SPIL stock began last year, I labeled it as a hostile takeover despite ASE’s pronouncements that it was not. Certainly we have seen SPIL resisting this acquisition. Last week, it was announced that they have found a non hostile solution where they will be joined through a new holding company. Under the holding company, SPIL and ASE conduct their own business/operations Independently as now. [link]

The deal creates a holding company that will list in Taiwan and the United States, with current securities of ASE and SPIL being delisted. Each will retain its management and staff. All working conditions, benefits etc remain unchanged. Both companies have one month to approve the deal, subject to the regulatory approval, most critical is the anti-trust examination from Taiwan, China, and USA governmental agencies.

Continuing our look at the IMAPS Polymers Conf.

Merck – Photoresists for Fine Line RDL

Toukhy of the old AZ group (now Merc performance materials) looked at photoresist development for fine RDL Applications.

They see future requirements for fine line RDL as:

– continued demand for thick uniform resist films

– higher resolution, aspect ration and vertical profiles

– improved focus latitude and process window

– chemical resistance to plating solutions

– longer allowed post exposure delays

– eliminate or reduce post exposure bake sensitivity

Conventional resist platforms are usually either chemically amplified or DNQ based. Positives and negatives are shown below:

 

Their product lineup includes:

 

Toray – Wafer Level NCF

Tomikawa of Toray looked at new non conductive films for their collective bonding process. Toray NCF has been used in HVM since 2010 on application processors and graphics ICs. The standard process flow is shown below:

A close up of flip chip bonding solution is shown below:

 

Assembly could be speeded up considerably as the chips could be pick and placed and then gng bonded with a single heat treatment as shown below.

Toray has developed a NCF for gang bonding that shows not voids and passes TCT (temp cycling testing).

Dow – BCB laminate film

With the upcoming merger of Dow Chemical, DuPont and Dow Corning (pending Govt approval) I wonder what will be the disposition of HD Micro, which provides a majority of the PI and PBO market? Will PI, PBO and BCB all be coming from the same company in the future? Just one of the questions that consolidation brings to our industry.

O’Connor of Dow Electronic Materials addressed the use of photo BCB film for Advanced packaging.

The old R&H group has developed both solvent (14-P005) and aqueous (16P-008) developable BCB dry film with enhanced flexibility, elongation and fracture toughness.

Processing and properties are shown below:

 

 

Chip level reliability testing is underway.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…