By Dr. Phil Garrou, Contributing Editor

The Latest on IBM and GF

Craig Wolf of the  Poughkeepsie Journal reports confirmation from Global Foundries that 150 to 200 IBM’ers will move from IBM’s East Fishkill chip plant to GlobalFoundries’ plant in upstate Saratoga County. GF has confirmed a contract with IBM in which “technical workers” based at the East Fishkill will work for eight months at GF’s Fab8 chip plant. IBM refused comment on the deal.

While one cannot conclude that his confirms the imminent sale of the IBM Semiconductor division to GF (which IFTLE has predicted for several years) , it certainly indicates that things are slow in the IBM plant.

Continuing our look at the recent 2.5/3DIC Forum at SEMI Singapore.

Nanium

Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology and that eWLB offers an alternative with sufficient capability for many applications in high volume at reasonable cost.

PoP structures such as those shown below are being readied for portable applications where less than 1mm thickness is required.

Nanium is working with AT&S to develop technology for reconstitution in laminate vs traditional eWLB which forms a wafer out of molding compound.

Fujitsu

Fujitsu presented on “Highly reliable chip to chip Cu wiring technologies for 3D/2.5D interconnection.” Their premise is that as interconnect gets finer and finer traces will need full barrier layer protection similar to what is done on chip with dual damascene, especially when the interposer is a high density PCB. This is shown by HAST failures as shown below.

Their proposed failure mechanism is:

– Halide ions and organic acid accumulate around the anode Cu

– Anode Cu dissolves and Cu ions are formed

– Cu ions diffuse and drift into insulating materials

– Cu dendrite growth on cathode surface triggers dielectric breakdown

A barrier layer is needed to prevent Cu corrosion. SiN failure is due to cracking due to the CTE mismatch.

EVG

Thorsten Matthias reviewed EVG solutions for interposer manufacturing.

Of special interest was his review of the work of GaTech and Zeon looking at the insulation of interposer TSVs with polymers instead of oxide. Oxide liner is usually less than 1μm thickness and the cost scales with thickness whereas polymer liners can be much thicker and the cost is independent of thickness. The GaTech simulations show the polymer liners will give superior electrical performance. FEA shows the polymer liners should show a Reduction of thermal induced mechanical stress.

EVG proposes spray coating as the technique to get the TSV insulated with polymer as shown below. EVG wafers were processed on an EVG NanoSpray coater with JSR Micro WPR 5100 positive resist and BCB for polymer insulation.

IFTLE notes that cross sections were shown for 40um dia TSV but not for the more common 10 x 100um TSV.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou

At the recent 2.5/3DIC Forum at SEMI Singapore Dr. Surya Bhattacharya, Director of Industry Development (TSV) at, A*STAR Institute of Microelectronics chaired the day long session looking at the state of TSV technology. Let’s take a look at some of these presentations.

SPTS

SPTS updated attendees on their endpoint controlled “via reveal” etch process. As we know, via reveal involves the following process sequence:

The SPTS Rapier module has their “ReVia^TM” in-situ end-point detection technology which they claim increases throughput and yield.

STATSChipPAC (SCP)

The SCP presentation looked at “2.5/3D Integration: Moores Law and Beyond.” One message here is that 2.5/3D is not a cure all. As we have seen SCP present in the past, they conclude (and IFTLE concurs) that the right packaging solution must be chosen based on the requirements of the unique opportunity. We have seen the figure below before, but it is worth showing it again.

For instance, comparing 2.5D to an eWLB solution:

SCP reiterated that they see their position in the infrastructure as mid end and back end of line.

Their work with UMC which was initiated in 2012 has taken structures such as wide IO memory on Aps processors through reliability with positive results.

SCP has demonstrated MEOL (mid end of line) and BEOL process capability for 2.5/3D TSV with hand-off between foundry and OSATs.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Phil Garrou

IFTLE has said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization. SEMI has been working on this now for 3+ years . Lets take a look at their recent update from their SEMICON Singapore presentation.

Semi 3DIC standard Activities

Semi updated their 3DIC standards activities in late 2010 with the following structure:

So far, they have published the following standards:

SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology

– Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.

– The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).

SEMI 3D2-1113, Specification for Glass Carrier Wafers for 3DS-IC

– This Specification describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;

– Methods of measurements suitable for determining the characteristics in the specifications indicated.

SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames

–Address the methods for shipping thin wafers on tape frames.

SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

– Control of bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and flatness metrology, is essential to successful implementation of a wafer bonding process.

– This std provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.

SEMI 3D5-0314, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through- Silicon Vias (TSVs) in 3DS-IC Structures

– This std assists in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.

SEMI 3D6-0913, New Standard: Guide for CMP and Micro-bump Processes for Frontside Through Silicon Via (TSV) Integration

– This std provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump.

SEMI 3D7-0913, New Standard: Guide for Alignment Mark for 3DS-IC Process

– Photo alignment mark configuration is the key to ensure consistent and precise alignment of layers, chips and wafers.

– This std provides an alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking.

NA Task Force Overview

Bonded Wafer Stacks -– Create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process.

Inspection & Metrology –  Develop standards for metrology and inspection methods to be used for measuring TSV properties, bonded wafer stacks, and dies used in the 3DIC manufacturing process.

Thin Wafer Handling – Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DIC high-volume manufacturing (HVM).

Taiwan 3DS IC Testing Task Force

• Design for Test (DfT) such as test structures and placement

• Test methodologies such as contact method and test procedures

• Test fixtures such as probe card and probe interfaces

Taiwan 3DIC Middle End Process Task Force

• Develop criteria for micro-bump dimensions, planarization and related. Dimensions can be determined into wafer-to-wafer level (WWL), die-to-wafer level (DWL), and die-to-die level (DDL).

• Develop criteria for TSV CMP process and related. (Via size, via surface roughness, post CMP Cu step height, and post CMP Cu bump planarization uniformity)

• Develop standard for photo alignment mark and overlay mark. Alignment marks for patterning TSVs and stacking devices/wafers would be standardized for recognition.

• Suggest wafer or die thickness variation and warpage before and after MEOL and identify thickness variation, void size, overall void percentage of temporary bonding glue layer, warpage control after temporary bonding and corresponding measure method.

• Develop TSV quality criteria such as thickness uniformity, TSV depth variation, void, pattern density, TSV metal extrusion.

Japan Thin Chip Handling Task Force

The Thin Chip Handling TF aims to develop standards for carriers such as chip trays for reliable handling and shipping of thin chips and dies used in high-volume 3DIC manufacturing.

• Test Method for Measurement of Chip (Die) Strength by Mean of Cantilever Bending was submitted

For more information, please visit the SEMI 3DS-IC Google Site: https://sites.google.com/a/semi.org/3dsic/

More from SEMI Singapore in next weeks IFTLE.

For all the latest in 3DIC and Advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou

For several years now through PFTLE (in Semiconductor Int) and IFTLE  (in Solid State Technology) I have been mimicking Kareem Abdul Jabbar’s role as the street preacher in Stephen King’s “The Stand.” For those of you who have not seen the movie (or read the novel) he marches through Times Square ringing a big cow bell and wearing a sign reading “The End is Near.”  He is predicting the end of the world as we know it due to a plague released by a secret Government lab. No one believes him, but soon, as they all begin die, we become aware that he was correct.

I have not been predicting the end of the world, but rather the end of electronics as we know it, i.e relying on CMOS scaling. Similar to my economic prediction that the stock market will “soon” fall, sooner or later I will be right.   Therefore, it was with great anticipation that I perused the 2013 ITRS roadmap that was released a few weeks ago. Would they try to ignore what is happening or would they face the issue head on like the poet of my generation Bob Dylan who in 1964 released “The times they are a-changin”. I am happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

The 2013 ITRS Roadmap

The ITRS for those of you not familiar with the group  is jointly sponsored by the US, Taiwan, European and Korean SIA and the Japanese JEITA (Japan Electronics and Information Tech Industry Assoc)  so they are certainly “mainstream.” Hundreds of technologists from around the world staff the dozens of committees that every few years update where the semiconductor industry is going.

A quick look at the Exec Summary gives us a good understanding of the theme for this update “The ever changing environment.” They contend that the Semiconductor Industry, born in the 70s, had two main goals: (1) providing cost effective memory devices with pin-out and functionality standardization and (2) application specific integrated circuits (ASICS) that required specific functionalities to realize novel products.

Classical Scaling

In the 80s system specifications were in the hands of the system integrators. Through scaling, semiconductor technologies were introduced every three years by memory devices and were subsequently adopted by makers of logic devices. In the 90s continued scaling allowed logic and memory IC manufacturers introduced new technologies every two years and substantial part of the control of system performance and profits moved into the hands of IC manufacturers. This period of ~25 years can be called the Era of “Classical Scaling.”

Equivalent Scaling

In the late 1990’s we began to see technologies such as strained silicon, high- κ /metal-gate and multigate transistors be used to further improve device performance. This second Era known as the Era of  “Equivalent Scaling” That can be seen in the figure below [ this is not in the ITRS roadmap, IFTLE added it to strengthen the point]

3D Power Scaling

Because 2D scaling will eventually reach fundamental limits, both logic and memory are now exploring the use of the vertical dimension (3D). Increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors. The combination of 3D device architecture and low power device will usher the (Third) Era of Scaling, “3D Power Scaling.”

System integration has shifted from a computational, PC centric approach to a mobile communication approach.

The heterogeneous integration of multiple technologies in a limited space (e.g., GPS, phone, tablet, mobile phones, etc.) is now the main goal of any design from a performance driven and reduced power driven approach. In the past performance was the only goal; today power consumption drives IC design.

The foundation of heterogeneous integration relies on “More Moore” (scaling) devices with “More than Moore” elements that add new non CMOS functionalities that do not typically scale or behave according to “Moore’s Law.”

Unfortunately the sections of the report that are of the most interest to IFTLE namely back-of-the-line “Interconnect” and “Assembly & Packaging”  are evidently not completed (or cleared for publication) yet. So discussion of those sections will have to wait. We have been given a glimpse of the packaging and assembly challenges in the table shown below.

The full report (all that has been released thus far) can be found here [link]

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…