By Dr. Phil Garrou, Contributing Editor

This week, I am interrupting our look at the 2017 3D-ASIP conference to take a look at consolidation in the equipment industry and the recent issue of IMAPS Advancing Microelectronics magazine.

Equipment Consolidation

IFTLE has explained many times that a sure sign of industry segment maturity is when the 3 top players have a combined > 80% market share. The best examples of this currently are hard disk drives and DRAM memory.

The latest data on the equipment industry market shares points to this segment being very close [link] . Had the TEL/ AMAT merger gone through, the industry truly would have reached the definition of maturity. I would be looking for attempts at other combinations in this segment to be coming soon.

Chip Package Interaction

Urmi Ray, VP of Technology for STATS ChipPAC (JCET) has edited a special edition on the chip-package interaction, which is definitely worth a read [Advancing Microelectronics, Nov/Dec 2017, V44, No 6.][Link]

As most of you know, CPI is the interaction between the semiconductor package stresses and the semiconductor device. Package stresses are caused by thermal, mechanical and chemical mechanisms. CPI contributes to various failure modes during package assembly and field life. The emergence of both fan in and fan out wafer level packaging, while delivering unparalleled form factor and cost improvements by eliminating the package substrate, has resulted in loss of a buffer layer between the chip and PCB resulting in additional stresses being transmitted to the die surface during SMT assembly.

Qualcomm

Zhao and co-workers at Qualcomm discussed the “Electrical Chip- Board Interaction (e-CBI) of Wafer Level Packaging Technology”.

The industry is clearly moving packaging technology toward WLP and Fan-Out WLP to reduce packaging cost and form factor. One of the key dif­ferences between Flip Chip CSP (FCCSP) and WLP/FOWLP is the absence of a package substrate in the latter packaging options. For e-CPI in FCCSP, the package substrate isolates the chip from the PCB. Without the package substrate, the silicon die in WLP/FOWLP directly inter­acts with the PCB board. The mediation of the board stresses by the packaging substrate is now gone and one must evaluate the risk of direct PCB stress on the chip, i.e. electrical chip-board interaction (e-CBI). For WLP and FOWLP, e-CBI can be signifi­cant.

For example, they point to the fact that visual in­spection of FOWLP reveals dimple patterns on the backside of the parts after board level underfill which correlate with the pat­terns of BGA depopulation. In the absence of the mechanical support from BGA solder balls in the depopulated areas, the board level underfill shrinkage pulls the thin silicon die to­wards PCB. FEA models have verified this phe­nomenon and reproduced similar “dimples”. Since the silicon die bends toward PCB in the BGA depopulated regions, this infers that tensile stress is being created on active silicon surface.

 

AMD

Ivor Barber and co-workers discussed “14nm Chip Package Interaction Technology Development.”

With the implementation of extreme low K (ELK) porous dielectric materials (k < 2.5) into the back end of line (BEOL) to reduce the in­terconnect capacitance and cross-talk noise and enhance circuit performance, the lower mechanical strength of the ELK, along with increased die size, difference in effective coefficient of thermal expansion (CTE) between die and substrate, and the use of higher stiffness lead free solder increasingly contribute towards ELK layer cracking. Chip package interaction (CPI) be­came one of the critical reliability issues that needed to be addressed to avoid electrical or mechanical failure in products.

In order to evaluate CPI risk and reliability concerns from a technology point of view, they developed a CPI test vehicle (TV) which must include the same BEOL stacks, same ELK ma­terial, same BEOL process, same bump technology, same substrate technology, same assembly process for the pro­duction of the same Si node. In their 14nm CPI development, a 14nm TV with die size of 21×21 mm2 with 140um bump pitch of SnAg bump has been selected. 40×40 mm2 substrate has been used in our CPI technolo­gy qualification. JEDEC standard tests (Precon, UBHAST, TCJ, MSL, and HTS) were used as criteria for the CPI tech­nology qualification.

ELK delamination / cracks called “white bumps” are encountered as rigid lead free bumps would transfer more stress to weak ELK layers causing ELK crack underneath the bump. Unlike bare silicon dies, thermal deformation of pack­aged dies can be directly coupled to Cu/low-k or ELK interconnects, inducing very high local stresses to drive fracture and delamination. ILD delamination is caused due to dicing defects like micro-cracks and poor adhesion or mechanical strength of low-k/ELK dielectric materials under the thermal load of the processes like flip-chip as­sembly process or thermal cycling tests.

In order to improve the CPI margin, studies have examined passivation thickness, polyimide thickness, under bump metallization, CTE of substrate, and FBEOL. Simulation and DOE have shown that by using thicker Aluminum terminal metal and two layers of passivation, the CPI risk reduced significantly. So foundries have now implemented this dual pas­sivation layer with Al terminal metal to enhance CPI reli­ability.

Simulation has shown that ELK stress are reduced with reduced bump pitch.

The fracture toughness of low-k/ELK dielectrics vs SiO2, is substantially reduced and is significantly lower than that of Si. It is thus much easier to induce defects like micro-cracks during dicing. Those tiny cracks can develop and propagate into the active die area and cause failure un­der thermal-mechanical stress. One approach to prevent cracking at the die edge or die corner is to apply patterned metal structures called crack stop around the perimeter, especially reinforced at the die corners. They found that double wall crack stop was necessary for products with large die size to provide protection for the dicing defects.

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Consolidation in CIS Market

Remembering our IFTLE rule [ see IFTLE 241, “Simply Obeying the Laws of Economics”] that maturing markets have 3 players with > 85% of market share, we note that Gartner Assoc. has reported that the top 5 vendors accounted for 88.9% of global CIS revenue in 2016 and the top 3 companies have 78.9% of the market, up from 77.1% in 2015 so we are getting close… [link]

 

Teledyne / DALSA

Invensas (Experi) has announced technology transfer of its Direct Bond Interconnect (DBI) to Teledyne DALSA. This capability enables Teledyne DALSA to deliver next-generation image sensors to customers in the automotive, IoT and consumer electronics markets. Invensas and Teledyne DALSA announced the signing of a development license in February 2017. All of the major image sensor players appear to be adopting this image sensor stacking technology.

Chip Stacking for Image Sensors

Ray Fontaine at TechInsights has this to say about image sensor technology in 2017 “Chip stacking (image sensor + image signal processor) for image sensors remains an enabling technology for improved camera performance, and this year we documented Sony’s first-generation TSV-based three die stack (now adding a DRAM) in mass production. For two-die stacks, we still primarily see TSV-based chip-to-chip interconnect, although Sony has been using direct bond interconnects (Cu-Cu hybrid bonding, or DBI) since early 2016. We recently saw OmniVision and foundry partner TSMC join the hybrid bonding club and claim the new world record, based on TechInsights’ findings, of 1.8 µm diameter, 3.7 µm pitch DBI pads.” [link]

IMAPS 3D ASIP

The 14^th annual 3D ASIP conference, in early December, deviated somewhat from its traditional focus on 3DIC content to cover ancillary and complimentary technologies. Below we see incoming IMAPS President Ron Huemoeller presenting plaques to Gen Chair Garrou and Tech Chairs Scannell and Koyanagi.

 

DARPA CHIPS

DARPA has a long history if chip integration as is depicted in the slide below showing DARPA programs and their acronyms.

 

IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].

In his plenary presentation, DARPA program Mgr. Dan Green pointed out that the CHIPS goal is to develop design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of DoD and commercial designs and technology. Particular emphasis is being placed on trying to develop a technology infrastructure that can be adopted by both the aerospace infrastructure and the commercial infrastructure.

The CHIPS grants are led, as shown below, by Boeing, Intel, Lockheed Martin, Northrup Grumman and the Univ of Michigan.

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

IZM Fraunhoffer TU Berlin and Osram

Tanja Braun of IZM Fraunhoffer discussed “Fan-out and Panel level technology for Advanced LED Packaging.”

The ongoing miniaturization in LED chip size and thickness down to 200 μm and below requires adapted chip handling and assembly. Innovative solutions are needed to electrically connect top and bottom contacts of the LED guaranteeing at the same time a sufficient overall thermal concept. Polymer based package solutions need to consider the aging/yellowing of the polymers on constant exposure to intense light. High volume and low cost solutions are required.

A blue LED with an area of 1×1 mm² and a thickness of 120 μm was chosen for package development. The LED has one contact pad on the topside and needs an additional electrical connection to the backside. The overall concept for the SMD compatible single LED package is shown below.

Package size was designed to 1.6×1.6 mm² allowing the integration of a through mold via (TMV) with 100 μm diameter routing the contact from the topside to the SMD compatible pads on the package backside. Package mold thickness is 300 μm resulting in a mold layer of 180 μm on the backside of the LED. The backside of the LED is connected by a blind via with a diameter of 250 μm. The process flow is shown below:

Compression molding is used for reconfigured wafer encapsulation. Recent developments now allow panel molding for sizes up to 600×600 mm². Compression molding evaluation within this study has been performed on 200 mm with a wafer level machine from TOWA and with a large area panel mold machine from APIC Yamada using a tooling with a cavity size of 457 x 305 mm². For the LED package development a liquid black epoxy molding compound (EMC) has been selected with a filler particle top cut of 25μm. Material with small maximum filler particle size has been chosen to allow laser through mold and blind via drilling with precise geometries and smooth via walls.

Die shifting is one of the key challenges during “Mold first” FOWLP. Due to the different thermo-mechanical properties of carrier, thermo-release tape and epoxy molding compound dies move such that the die position is shifted with respect to placement position after cooling down from compression molding. This effect is also influenced by the chemical shrinkage of the molding compound. Die shifting can be overcome by using a fast AOI (automated optical inspection) in combination with maskless processing for die connection and rewiring. This would give the opportunity to tolerate larger die misplacement by adapting the layout to the real die position.

Vias to the top side ad backside are shown below.

IMEC

Cavaco of IMEC discussed heir results on “Hybrd Copper Dielectric Direct Bonding of 200mm CMOS Wafers with 5 Meta Layers…” where IMEC reports wafer level electrical data and reliability testing results for 200-mm wafer to wafer hybrid copper to dielectric aligned bonding on short loop wafers which consist of five backend of line (BEOL) metal levels using silicon carbon nitride (SiCN) as dielectric. The fabricated 200-mm wafer pairs are representative of a real CMOS device structure as they are processed with five metal levels per test wafer in a 130-nm copper BEOL CMOS technology.

In the wafer to wafer hybrid bonding process, two substrates are connected simultaneously by a copper to copper metal bonding and by an inter layer dielectric (ILD) oxide bonding. Some of the main issues inherent to the hybrid bonding process are: the profile of the copper pads after copper chemical-mechanical-planarization (CMP); the oxide erosion; the used surface treatment before bonding; the wafer to wafer bonding alignment accuracy; the contact integrity; the contact reliability; and manufacturing yield issues.

The full bonding sequence essentially comprises a wet clean module, a plasma module for surface activation and a bonding aligner module. A bonding accuracy below 1μm can be achieved by using dedicated alignment keys on both sides of the wafers. Bonding misalignment on the X direction was of the order of 0.7μm. Afterwards, the wafers were brought into proximity and dielectric bonding took place. Subsequently, copper to copper bonds are formed during a post-bonding anneal step.

SiCN was chosen as the dielectric layer(a) because SiCN is known to have a higher bonding strength when compared to SiOx, or SiN and (b) because SiCN can act as a barrier against metal diffusion into the dielectric, which can take place when using SiOx in a hybrid bonding process that comprises copper line patterns.

To confine the copper bonding pad dishing/protrusion to values below 10 nm, a strict process control of the CMP step is required on all wafers.

In this study, both HTS and TC reliability testing were performed at wafer level. More specifically, TC testing consisted of up to 1000 temperature cycles, of one hour each, from -40 °C to +125 °C. HTS testing consisted of storing the wafers, in a nitrogen environment, up to 1000 hours at +125 °C. Zero-yield loss observed at the end of both TC or HTS reliability testing.

Xperi (Ziptronix)

Gao and co-workers from Xperi discussed their studies on the “Development of Hybrid Bond Interconenct Tech for D2W and D2D Applications”

We have discussed previously the acquisition by Xperi (Tessera) of Ziptronix and their DBI bonding process [see IFTLE 253, “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix; Tezzaron 8 layer 3DIC “ (link)]

This DBI (hybrid bonding) technology has been licensed and widely adopted by players in the CMOS imaging sensor industry such as Sony and Omnivision [see IFTLE 325, “ Omnivision takes Ziptronix License…” (link)]

To the best of my knowledge al of the CMOS image sensor work is being done on 200mm wafers , i.e W2W. Rumor has it that the process is much more difficult when trying to do D2W or D2D bonding. Attempting to resolve this issue and expand the use of the process in their applications, Xperi has undertaken a study of the D2W process looking to compare it to the more standard TCB (thermos compression bonding).

Obviously aiming at the stacked memory business, their test structures consisted of a host wafer designed to mimic the logic controller in a HBM stack. The fig below shows an illustration of four dies stacked on top of a host wafer. Daisy chain coverage includes hybrid bonding between the following interfaces: host die to die 1 bottom: die 1 top to die 2 bottom; die 2 top to die 3 bottom; and die 3 top to die 4 bottom. Currently, the stackable die does not have through-silicon vias (TSV). Consequently, electrical testing is limited to the die 1 bottom to host die interface. For next phase of development, TSV will be included to enable electrical testing of all interfaces.

It is desirable to maintain the RMS roughness of silicon oxide on the bonding surface below 0.5nm to facilitate high bond energy between the silicon oxide components of the hybrid bond. A similarly low surface roughness of copper is also desirable (although less critical) to further increase bond energy. In addition, it is desirable to have the Cu surface slightly recessed from the oxide surfaces.

The table below compares the total process time and throughput of a bonder for TCB and hybrid bonding. The hybrid bonding process requires very low contact force. It is essentially a P&P only process. It requires no temperature profile, no pressure control and no dispensing of additional material. On the Toray bonder, they demonstrated that 10s and 1s bonding dwell time shows the same bonding results. On the Datacon bonder, we have demonstrated bonding dwell time of 0.1s. With addition of 0.5s material handling time to each machine, the calculated throughput is 2400 unit per hour (UPH) on the Toray bonder and 6000 UPH on the Datacon bonder.

Compared to TCB, the hybrid bonding requires additional processes for die cleaning, activation and anneal. However, all these processes are carried out in batch and does not limit the throughput of the bonder.

 

Bonds with poor electrical contact appear to be the result of particulate contamination . Such contamination is considerable reduced in a class 100 clean room environment. Optical images of the die stack is shown below.

For all the latest in Advanced Packaging Stay, linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Merry Christmas and Happy New Year to One and All

Intel Altera release Stratix 10 FPGA with HBM2 memory and EMIB connections

Before we continue our coverage of the 2017 IWLPC, I need to make sure everyone has seen the announcement from Intel (Altera) on the availability of the Intel Stratix 10 MX FPGA, their FPGA (field programmable gate array) with integrated HBM2 (High Bandwidth Memory). [link]

The Intel Stratix 10 MX FPGAs, utilizing Intel’s 14 nm FinFET process, reportedly offer up to 10X the memory bandwidth as compared to standard DDR 2400 DIMM standalone memory solutions. In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can reportedly compress and accelerate larger data movements compared with stand-alone FPGAs.

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 Gb per second through the integrated HBM2. The Intel Stratix 10 MX FPGA family utilizes Intel’s EMIB technology (Embedded Multi-Die Interconnect Bridge) for high density connections. IFTLE thinks this is the first commercial implementation of EMIB technology in the industry.

IWLPC part 2

KNS

Brubaker and Strothman of KNS discussed the “Application of Infrared Inspection to Thermo-compression bonding and die placement”.

In die placement processes, accurate die placements are required to ensure the formation of functional and reliable electrical interconnections. Verification of accurate die placement can be a challenge for standard flip chip products where there are no patterned features on the backside of die. Cross-sectioning or X-ray inspection can be done, but cross-section inspection requires that samples be epoxy under-filled, ground, polished, and inspected using a microscope. X-ray inspections typically require offline processing with dedicated equipment.

In situ measurement within the die placement equipment itself would be preferable. Typically, die placement machines are equipped with a camera which is utilized for target alignment operating within the visible spectrum. The addition of infrared inspection capability to die placement equipment resolves the limitations presented for in situ visible inspection. Because silicon is transparent to infrared light, an infrared inspection system is able to see through the blank backside of die to detect internal metal patterns. Silicon wafers and die which have been back thinned using a fine grind or polishing process are excellent candidates for infrared inspection. Wafers which were back thinned using coarser mechanical grinding (2000 grit and 1200 grit) yielded lower quality infrared images. The impact of this limitation is believed to be minimal, since most high-end die which require high accuracy placement are evolving to thinner packages which already require fine surface finish to prevent die cracking and wafer warping.

In addition to surface finish, die designs must include features which can be used to generate images with sufficient quality to measure die offsets. In many cases, no special considerations are required in terms of die design. If the absolute best possible placement capability is desired, it is noted that dies which include features optimized for infrared inspection will maximize measurement capability.

Corning

Bellman and co-workers from Corning Glass discussed “Temporary Bonding for High Temp Processing of Thin Glass”.

Their “Advanced Lift-off Technology (ALOT)”, is a temporary wafer bonding method for thin glass which reportedly permits subsequent processing over 400C. Fluorocarbon plasmas modify the surface of the glass permitting subsequent controllable van der Waals bonding between a thin glass plates at room temperature. This modification can withstand the vacuum, thermal, wet processing steps of BEOL processing. However, the bond energy between the pair remains low-enough after the thermal processing steps that renders the pair fully detachable.

The ALOT process involves treating a clean hydroxylated glass carrier surface in low-pressure plasma containing CHF3 (or C4F8) and CF4 gases. The CHF3 gas acts as a polymerizing agent and deposits organic fluorocarbon species on the glass carrier while CF4 acts as an etchant and tends to etch away both glass and the organic polymer deposited by CHF3.

In the figure below they plot the bond energy as function of annealing temperature for glass to glass carrier without ALOT treatment (marked as “glass on glass”) and for thin glass bonded to ALOT treated glass carrier corresponding to three initial surface energies (40 mJ/m2, 55 mJ/m2, 72 mJ/m2). The bond energy of untreated glass to glass pair increases exponentially after 200 °C rendering the pair permanently bonded due to covalent bonding. On the other hand, the bond energy of thin glass and ALOT-treated glass carrier pair remains fairly constant at a moderate value up to 400 °C irrespective of the initial surface energy of the glass carrier. This renders the thin glass- glass carrier pair de-bondable after ay post processing which experiences a maximum temperature excursion of ~350-400.

SPTS

Barker and co-workers at SPTS discussed “RC Management for Next Gen PVD UBM/RDL Metallization Schemes”.

Organic materials such as PI or PBO dielectric passivation, epoxy mold compound (EMC), or adhesives for bonded wafers with 2.5D and 3D TSV) have the potential to contaminate under bump metal (UBM) or redistribution layers (RDL) producing a potentially undesirable increase in electrical contact resistance (Rc). With the reduction of UBM/RDL via dimensions in line with device shrinks, contamination effects become more critical.

When placed under vacuum and heated, organics will outgas moisture significantly more than traditional ‘front-end’ dielectrics such as SiN and SiO2. When those same organics are sputter-etched during the subsequent UBM/RDL pre-clean step to remove native oxide from exposed metal contacts, they release volatile carbon by-products from their surfaces. Both moisture and carbon by-product contaminants can react with the cleaned exposed metal pad contacts, forming a layer that increases the contact resistance of overall metallization interconnect scheme produced. The problem is particularly acute with advanced node devices with small contact area dimensions where the contaminant has a proportionally larger impact.

New package schemes such as FOWLP can include wafers that feature singulated die embedded in epoxy mold compound (EMC), and have organic dielectrics surrounding the RDL. These materials present challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. Whereas conventional circuits built on silicon can withstand heat up > 400C and can be degassed rapidly without impacting system throughput, the presence of any EMC, organic dielectrics, or bonding adhesives introduces a lower heat tolerance which can be as low as 120C. Temperatures exceeding these lower thresholds can cause decomposition of the organic based materials, in EMC case; it can lead to excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time.

Multi-wafer degas (MWD) technology has emerged as a solution to this problem, enabling many wafers to be degassed at 120C in parallel before being individually transferred to subsequent process steps, without breaking vacuum. Each wafer can spend up to 30 minutes inside the MWD, but because they are processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times.

If a wafer with organics present isn’t degassed sufficiently prior to pre-clean it can produce high levels of outgassing that affect plasma stability during etch, and film quality (Rc) during subsequent sputter deposition. As the surface of the wafer is etched during the pre-clean step, native oxide is removed from the exposed metal contact, but the ion bombardment damages the surface of the organic passivation, releasing volatile carbon species, which, re-contaminates the metal contacts.

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