By Dr. Phil Garrou, Contributing Editor

Before we take our first look at IMAPS 2016, let’s first look at some recent merger announcements and rumors which continue unabated.

ASE / Siliconware

Despite the recent approval by Taiwan’s Fair Trade Commission the proposed merger between ASE and SPIL continues to be reviewed by anti-trust authorities in China and the US. It is reported that it is unlikely to gain approval from the two major markets until the end of 2017. [link] ASE and SPIL agreed to merge through the formation of a parent holding company. The holding company would own ASE and SPIL.

The merger would create the world’s largest IC assembly & test company and widen the market gap with rival rivals such as Amkor China-based Jiangsu Changjiang Electronics Technology (JCET).

Earlier in 2016 Digitimes reported rumors that Amkor is being targeted for acquisitionby China’s Nantong Fujitsu Microelectronics (NFME). NFME previously acquired an 85% share of AMD’s backend operations in Penang, Malaysia and Suzhou, China for $371 MM.

Qualcomm / NXP

As we discussed in IFTLE 306 [“Qualcomm acquisition of NXP ?…”] , Qualcomm agreed to acquire NXP Semiconductors for $38.5 billion. This will give Qualcomm a presence in the chips for smart cars market.

Siemens / Mentor Graphics

Siemens and Mentor Graphics announced that they have entered into a merger agreement under which Siemens will acquire Mentor for $4.5B. Siemens is acquiring Mentor as part of its Vision 2020 concept. Mentor is expected to complement Siemens offering sin mechanics and software with design, test and simulation of electrical and electronic systems. Mentor is generally viewed as a global leader in IC design, test and manufacturing; electronic systems design and analysis and automotive electronics. The deal will boost Siemens software revenue by about a third.

Samsung Electric to acquire Harman International

Samsung Electric has announced it will acquire Harman Int for $8B. Harman is best known for making car audio systems such as Harman/Kardon and JBL. Samsung’s interest is in Harmans “connected car” business which supplies navigation services, onboard entertainment systems and connectivity to the rest of the world.

Rumors from Asia

IFTLE hears that silicon interposers are still in short supply. Word is that Inotera has backed out of the business before they ever entered it. Recall ASE announced Inotera would be their supplier [see IFTLE 187 “…..ASE / Inotera 3DIC JV”]. So who will supply ASE now? Have they decided not to be a player in this market sector ?

If we look at who is really supplying, i.e. actually selling, silicon interposers (vs the lists put together by marketing companies that are pages long and include everyone who wants their names included) we are left with TSMC (per their CoWoS technology) and UMC who is supplying AMD. As Porkey Pig used to say in the cartoons I used to watch as a child “That’s All Folks!”

Is there any wonder why 2.5D is struggling to take off with only these two suppliers in the infrastructure?

Congratulations to “Doug” Chen Hua Yu – TSMC

Rumor from Taiwan is that TSMC’s Douglas Yu was promoted to VP based on the success of InFO. Note that Doug was also responsible in a large part for the commercialization and success of CoWoS. As IFTLE has stated before, Doug, who earlier in his career was responsible for on chip interconnect scaling, was moved to packaging and has been a real driving force there.

Rumors persist that TSMC will license their InFO technology to 1-2 OSATs when their current fab is near sold out. IFTLE hears that Amkor is pursuing this licensing aggressively.

IMAPS 2016

The IMAPS 49^th Int. Symp. on Microelectronics was held in Pasadena CA in October. For the next few weeks we’ll be looking at some of the key presentations from that conference.

Amkor

Amkors Huemoeller certainly gave toe most relevant keynote “Creating Semiconductor Value through Advanced Packaging”. Nothing could be more in line with the theme of IFTLE for the past 6 years than the focus in the semiconductor industry shifting from the front end to packaging.

Huemoeller points to the fact that tier two OSATS simply do not have the scale or liquidity to invest what is needed to stay on the leading edge. He indicates that an investment of > $500MM / yr is required to just sustain current business.

**Remember the IFTLE credio “The leading edge is where you make the money” **

– investment in leading edge technologies creates scale and drives down costs.

He puts fort the following industry segments as driving packaging technology.

And lists the following as the “Big 5” packaging platforms:

– WLCSP is now showing > 30% penetration in high end smartphones.

We all know about the sensors in smartphones , but probably not the extent of sensors coming in automobiles:

SiP are basically today’s generation of what we used to call Multichip Modules in the 1990s. Amkor sees them requiring state of the art technology and driving heterogeneous integration with and without sensors.

 

Huemoeller sees the next gen of MCMs (or SiPs) being wafer based, since they will provide the best performance (power, electrical and thermal) and the thinnest form factor.

The following chart show how they see fan out packaging evolve into advanced SiP.

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 Semicon Taiwan. This week we finish our overview of Semicon Taiwan 216 with an examination of presentations by TSMC who as we all know is making a major push into the high end packaging market.

TSMC – Packaging Solutions

Doug Yu discussed TSMC packaging solutions which are summarized below:

The history of TSMCs CoWoS interposer commercialization is shown below. CoWoS “key merits” include:

Sub-mm interconnect

• DD Cu, 1000+ lines/mm
• Small via, easy routing
• Very low defect density

Super large size

• 1200 mm2 in production. Going 1500 mm2
• Highest level of multi-die integration

Multichip InFO vs multichip FC CSP are compared below:

TSMC – Interposers Past, Present and Future

Shang Hou of TSMC discussed interposers past, present and future.

Hou compared the TSMC CoWoS TSV based interposer technology to TSMC InFO fan out packaging in the slide below. The first gen CoWoS started in 2012 with 28nm logic chips. The industry’s first 16nm network processor was built with CoWoS® in (2014). CoWoS delivers faster time-to-market by eliminating the node-dependent CPI seen in conventional packages.

2nd Gen CoWoS

The industry’s first 20nm FPGA product was built on CoWoS in 2015

• xtra large interposer ~1200 mm2
• Composed by two-masks stitching of sub-micron RDL
• Package with record-large chip size
• Passed stringent component reliability tests

Volume is by far the No.1 factor in the cost equation

• It has not yet find a niche in mobile applications
• There is firm demand in the extremely high-end market (Cloud)

Interposer high intrinsic cost is unavoidable compared with flip chip. The key is whether it has sufficient value to justify the cost?

For all the latest on Advanced Packaging stay linked to IFTLE…

 

 

By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 SEMICON Taiwan. This week let’s look at some presentations that focused on TSV based packaging.

SPIL – TSV in IC Packaging

Mike MA of SPIL reviewed the status of TSV in IC Packaging. His summary of current TSV usage is shown below:

1. TSV in CIS – Sony
2. TSV in MEMS/Sensor
3. 3D IC with TSV – only in High Band Width (HBM) DRAM

-Hynix, Samsung start HBM-1 LVM in 2015

-HBM-2 in 2016

– Advantage proven, cost still high

4. 2.5D IC with TSV Si Interposer

– 2010 Xilinx debuted 1^st product group (FPGA)

– 2015: AMD rolled out 2^nd product group (GPU+HBM)

– 2016 nVidia GP100 with HBM-2

– Renewed interest for high end networking, VR/AR

SPIL currently doing 40um pitch on their ubumps as shown below.

SPIL is a proponent of the so called “chip on wafer last” process flow as shown below:

 

Other interesting comments by Ma include:

“The glass interposer has come and gone due to a lack of ecosystem”

“Fine line organic interposers keep delaying delivery of 5um L/S with still unknown costs. PCB insustry needs to invest in sub 5um L/S”

“Fan out packaging is capable of 2um L/S x 2 layers, but larger package size (> 15 x 15mm sq) will be challenging”

Amkor – Large Die Assembly with TSV Packaging

JY Khim discussed large die assembly technology in TSV packages. He notes the following points about their multi-die platforms:

CoS Process Flow

• No molding                 • Interim test available
• Mold sensitive components OK   • Shared infrastructure with FCBGA

Initial interposer warpage affects the PCB + interposer warpage. For the successful top die attach warpage minimization of interpose is important. Tuning the Inorganic C4-side passivation layer can reduce interposer warpage.

 

He compares the CoS to the CoW process below:

In the CoW Process, there are no warpage risks in top die attach on interposer regardless of die size.

Khim showed the following table containing Amkor 2.5D CoW experience.

EVG – Chip Stacking in High Volume

For those looking for a good comparison of Samsung vs Hynix stacked memory cross sections, Wimplinger of EVG offered us the following figure and table comparing the two.

For all the latest in Advanced Packaging, stay linked to IFTLE…