By Dr. Phil Garrou, Contributing Editor

Consolidation

One may say that IFTLE has been obsessed with consolidation for the last few years. The reasons for this become obvious when one looks at the increase in recent activity. There are typically ~25 or so acquisitions a year. In 2015, there will 2X that number and the deals, in general are ~10X larger than in the past.

IC Insights has recently pulled together the major M&A activity over the last year.

In addition, several large M&A agreements announced last year have closed in 2015 including:

• RF Micro Devices and TriQuint Semiconductor officially completed their Qorvo merger
• Qualcomm completed its acquisition of CSR in August 2015
• Cypress completed its acquisition and merger with Spansion in March 015
• Infineon completed its acquisition of International Rectifier in January 2015
• IBM completed the sale of its Microelectronics business to GlobalFoundries in July 2015

IC Insights notes that the unprecedented M&A activity is indicative of IC suppliers experiencing slower sales in their existing market segments and the need to broaden their businesses to stay in favor with investors. IFTLE favors the explanation that we have published previously, i.e. many of the segments of our industry are entering late stage 3 and stage 4 where consolidation is the norm. (See IFTLE 241, “Simply Obeying the Laws of Economics”.)

ASE Buys 25 percent of SPIL Stock

Following up on our story about ASE attempting to purchase 25 percent of SPIL (see IFTLE 252, “ASE makes bid for SPIL shares…”), ASE announced on September 22 it has purchased 25 percent shares of SPIL shares, achieving its acquisition goal.

SPIL reiterated that a SPIL-ASE tie-up would not create much synergy, since 85 percent of its customers overlap with ASE’s. “… the acquisition will cause order losses as customers will allocate some orders to a third supplier rather than put all their eggs in one basket,” SPIL stated.

ASE noted that now being a major shareholder of SPIL, the company will be exploring avenues of cooperation with SPIL but otherwise, “ ASE will not intervene in SPIL’s operations and therefore, cannot affect the rights and interests of SPILs current employees.” [Link]

Embedded and Wafer Level Package Technology Forum at Semicon Taiwan

Continuing our look at Semicon Taiwan 2015, let’s begin our look at the Embedded and Wafer Level Package Technology Forum led by Mr. Albert Lan (left), Senior Director, SPIL. The theme of the forum was System Integration & Package Solutions for Portable/Wearable/IoT Devices. Mediatek discussed “Packaging Breakthroughs in Wearable Devices”. Unimicron gave a great review of “Innovative Substrate Technology …”;  J Devices discussed their panel level processing efforts and Fraunhoffer IZM discussed results of their fan out panel level processing.

 

Mediatek

Overall Mediatek sees IoT wearables as requiring:

• miniaturization which can be achieved with embedding;
• being substrate less for low cost which is achieved by fan out packaging; and
• being manufactured on a panel process to minimize cost.

Mediatek discussed Aster (MT2502A) a monolithic low-power CMOS chip integrating power management unit, analog baseband and radio circuitry. Based on an ARM RISC processor, it provides a platform for class 12 MODEM and leading-edge multimedia applications.

It also features a Bluetooth transceiver and an FM receiver supporting both audio broadcast de-modulation and RDS/RBDS data decoding. The MT2502A device is offered in a 5.4mm×6.2mm, 143-ball, 0.4mm pitch, TFBGA package. MT2502A provides always-on mode to optimize the low power performance for wearable device. [Link]

Another interesting development is their antenna on package (AoP) technology which they claim offers smaller form factor, better performance and faster time to market, although one must be careful about a properly designed keep-out-zone and proper design to minimize EM interference.

We’ll finish up with Semicon Taiwan 2015 next week.

For all the latest in 3DIC and other advanced packaging stay linked to IFTLE.

By Dr. Phil Garrou, Contributing Editor

System Integration by 3D SiP

The forum chairman was CP Hung, who is currently the VP of Corporate R&D for ASE Group, responsible for next generation products development. The System Integration by 3D SiP forum invited global experts to discuss the development of 3DIC and 2.5DIC packaging and alternative solutions. Presentations were made by Cisco, AMD, SK Hynix, ASE, Altera, Amkor, Teledyne and Cadence.

 

AMD

Bryan Black detailed the commercialization of the AMD “Fiji” GPU which has been in development for 8.5 years. It “required the collaboration of 20+ companies and government research organizations”. The four that were key included Amkor, ASE, SK Hynix and UMC.

Some of the obstacles that they ran up against are listed below:

SK Hynix is in production with HBM memory in support of “Fiji”. HBM benefits include:

• 4096-bit memory interface with four stacks creating 512GB/s of bandwidth
• 60% higher memory bandwidth6 for 60% less power7 than GDDR5
• 4X bandwidth per watt improvement from Radeon (TM) R9 290X

SK Hynix

Hongshin Jun of SK Hynix detailed their high bandwidth memory development. Each application has different memory requirements, but most common are high bandwidth (HBM) and low power consumption.

Mass production of their HBMPower consumption and bandwidth are compared for DDR and HBM below:

HBM 2 will show the following properties:

The stacked memory features 25um bumps on 55um pitch.

Amkor

Min Yoo of Amkor presented their SLIM and SWIFT package architectures. Basically, these are interconnected first technologies with no TSV. SLIM uses back-end foundry technology for <2um L/S, whereas SWIFT uses 2-10um OSAT RDL technology.

GaTech Global Interposer Workshop coming in November

The fifth annual GaTech Interposer workshop is coming Nov 4-6. With 2.5 and 3D being buzzwords, many conferences have interposer presentations. But the GaTech conference does the best job of bringing together practitioners from silicon, laminate and glass segments of this leading edge technology. This year’s conference is led by Rao Tummala (the Godfather of packaging) and Matt Nowak of Qualcomm, and Subu Iyer, who recently retired from IBM to teach at UCLA.

Highlight presentations include:

• Bob Sankman (Intel) – EMIB packaging
• Dave McCann (Global Foundries) – ASIC and RF with 2.5D technology
• Doug Yu (TSMC) – InFO
• Suresh Ramalingam (Xilinx) – SLIT (a TSV-less interconnect technology)
• Ron Huemoeller(Amkor) – Advance fan out: SWIFT and SLIM
• Bryan Black (AMD) – The road to AMD’s Fuji dGPU Chip
• DC Hu (Unimicron) – Glass manufacturing readiness
• Tomoyuki Yamada (Kyocera) – Organic interposers

Hope to see you all in Atlanta!

For all the latest on 2.5/3D and other advanced packaging stay linked to IFTLE.

By Dr. Phil Garrou, Contributing Editor

China targets GlobalFoundries

In IFTLE 238, we noted that China was the “wild card” when it came to global microelectronics consolidation – with plenty of cash and the government behind them. [link]

China’s National IC Investment Fund, Hua Capital Management, has reportedly approached GlobalFoundries, through an investment bank. Such an acquisition would allow China to secure 14nm FinFET foundry process technology [link 1]. GlobalFoundries’ 14nm process is licensed from Samsung [link 2].

Acquisition of GlobalFoundries would enable SMIC to enter volume production of 14nm FinFET products much earlier than originally planned. SMIC began volume production of 28nm chips in cooperation with Qualcomm and has signed an agreement with Qualcomm, IMEC and Huawei to develop 14nm process with volume production slated for 2020.

Abu Dhabi’s Advanced Technology Investment (ATIC), a major shareholder of GlobalFoundries, is reported to be willing to sell its interest in GF.

In July, China’s Tsinghua Unigroup put a bid in to acquire Micron. On the packaging front, in the last year, Chinese companies have purchased bumping house FCI in Phoenix and the #4 global assembly house STATSChipPAC.

Tessera to Acquire Ziptronix

Tessera Technologies announced the acquisition of Ziptronix for $39 MM [link].

Founded in 2000 as a venture-backed spinoff of RTI International, Ziptronix is a pioneer in the development of low-temperature direct bonding technology for 3D integration.

Ziptronix’s patented ZiBond direct bonding and DBI hybrid bonding technologies. Ziptronix has commercially licensed their ZiBond and/or DBI technologies to Sony Corporation for volume production of CMOS image sensors, to Raytheon and to Tezzaron / Novati.

In 2013, Ziptronix announced an agreement with Tezzaron and Novati Technologies, a wholly owned subsidiary of Tezzaron, selling its 3D IC development lab in Morrisville NC to Tezzaron, to be operated by Novati [link].

Tezzaron Announce 8 Layer 3DIC

At the IEEE 3DIC conference in Japan, Tezzaron and their manufacturing subsidiary, Novati announce the world’s first eight-layer 3D IC wafer stack containing active logic. Claiming “…the transistor and interconnect densities per cubic mm are far higher than achievable with 2D 14nm silicon fabrication.”

Each wafer has 10 layers of copper interconnect supporting high performance CMOS logic – a total of 80 layers of interconnect and 8 layers of transistors in a finished stack as thin as a single conventional die. Tezzaron’s 8-wafer stack contains active CMOS circuitry and tungsten vertical interconnect. Wafers are 20µm thick; SuperContacts are 1.2µm diameter, 6µm deep, and can be deployed at a pitch of 2.4µm. There are no wire bonds, copper pillars, bumps, or underfill between the layers. The wafers were bonded with DBI technology, invented by Ziptronix and now available from Tessera. (see discussion above)

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…