At this week’s GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive  HVM (high volume manufacturing) applications. Certainly conference chair Rao Tummala, industry visionary whose name is synonomous with microelectronic packaging, feels the time is right to take a serious look at glass interposers both for their superior electrical performance and their promise of lower costs. The PB substrate manufacturers are also taking a serious look at this market and proposing that they can drive their technology to the required dimensions and electrical performance, though many skeptics including IFTLE are taking a “show me” attitude about these claims.

Status in Silicon

The Yole Developpement presentation pointed out that while 2.5D silicon interposer technology was fully underway at TSMC and GlobalFoundries, UMC and SPIL supposedly are near initiation, all of the rumored “driver applications,” like the Apple A7, the next gen Qualcomm phone, the Sony PS4, ST Micro’s “Wioming” application processor, wide IO memory and the next generation Altera FPGA (see discussion below) have been, at the very least, postponed. While no one would openly reveal what the current and proposed future costs are, it is believed that all of these postponements are due to cost which certainly is not yet meeting the mobile phone requirements of less than 1 cent per sq mm proposed by Qualcomm’s Matt Nowak (i.e this is roughly $550 for a 300mm wafer of interposers).

While Yole has identified at least 10 products moving towards commercialization, all of them currently require so called high density interposers (i.e. 1um L/S and as small as 10um TSV). Currently these dimensions  can only be fabricated using front end dual damascene type processing available only at silicon foundries and more recently the OSAT, SPIL.

While Yole is still projecting a greater than $1B in revenue from 2.5D TSV activity by 2017 (activity revenues including TSV etching, filling, RDL, bumping, wafer test & wafer level assembly), these projections only hold if the current “postponed applications” are quickly commercialized.

During the Amkor presentation Ron Huemoeller indicated that lowering cost could come from elimination of backside RDL on the interposers by arranging pin out on the top side high density interconnect.

Huemoeller sees high end applications being dominated by silicon, mid end applications like graphics possibly using glass and the low end applications (yet unidentified) being wide open. He sees GPU + HBM (high bandwidth memory) being adopted in 2015 and tablets and processors adopting interposer solutions the following year.

In terms of organic “interposers” he indicates that Shinko and Semco are in limited sampling of  2/2 (L/S) and Kyocera 5/5. He labels Unimicron as in “early development.”

After making the standard IFTE argument that 2.5/3DIC was needed to combat the costs of continued scaling and that system level cost savings could pay for interposer costs,  Dave McCann of GlobalFoundries indicated that GF was achieving near 100% yields with reticle sized interposers having 4 layers of high density interconnect.

McCann predicted we would see voltage regulator function on future interposers. He also described a program between Global (chip and silicon interposer), Open-Silicon (design), Cadence (EDA tools) and Amkor (assembly and test), which produced a functional processor vehicle featuring two 28nm ARM Cortex-A9 processors connected on a 2.5D silicon interposer built on a 65nm manufacturing flow. The program demonstrated first-time functionality of the processor, interposer, substrate and the die-to-substrate assembly process. The design tools, process design kit (PDK), design rules, and supply chain are now in place for other activities.

What will be the Glass Interposer Infrastructure?  

Inherently most believe that all things being equal, glass should be a lower cost interposer solution since it can be processed in large format. However, one interesting question from the audience was “…why are silicon and glass wafer the same price then ?”

Although the data from experts like Professor Kim from KAIST confirms that glass is a better electrical performance solution, especially for Rf applications, the major issue is that a complete infrastructure is not yet in place to manufacture such glass interposers.

The big 3 glass producers ( Corning, Asahi Glass and Schott) have been listening to Tummala for several years now and all 3 are involved with his GaTech interposer consortium which has been promoting the use of glass. They each have their own technologies for forming TSV, but the infrastructure appears to stop there. While Corning’s Windsor Thomas said they are nearly ready to ship rolls of glass containing TSV, the question expressed by many in the audience was “ship to who?” Schott is in the same position.

Asahi Glass (AGC), however, appears to be a step ahead, having announced the formation of Triton, to produce and deliver circuitized glass interposers (link). This certainly will help AGC better understand the market and what the technology limitations are.

Neither the “panel of experts,” the speakers or the audience had a convincing argument as to whether traditional flat panel LCD manufacturers or PCB houses would be better at handling the metallization and singulation issues that still remain with glass panels (or rolls). LCD manufacturers use aluminum, not copper and we are told by Thomas of Corning, “Have absolutely no interest in this technology at all.” The PCB industry appears interested (certainly by their presence at this meeting) but would have to change nearly every unit operation and material that they currently use in order to meet the advanced requirements of 2.5D interposers.

What can PCB based Interposers Deliver

PCB’s are of course the first interposers, i.e most of the BGA substrates that exit today are PCB technology. So really the question that is being asked is “ …can PCB technology ever produce thin film silicon dimensions?”

Hu of Unimicron indicated that moving toward 2/2 (L/S) in polymeric PCB technology was doable but would require a move from wet processing to dry processing, the use of stepper lithography, embedded copper lines  and a change of core material to minimize warpage. Even if 2um lines and spaces were possible, this would have to be done in a class 100 clean room (more cost !) and does not address the TSV and catch pad dimension issue which really determines how many layers of interconnect are needed. If materials are changed and a move to thin film processes and equipment and facilities are needed, IFTLE questions whether costs will be considerably lower.

Koizumi of Shinko showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core.

GIT Conclusions

Enough encouraging data was shown to reasonably conclude that both glass and PCB should continue to be examined to fully understand their ultimate capabilities and costs.

Altera 2.5D Postponed

For those of you who haven’t noticed, the move of Altera to Intel to build FPGAs using its 14-nm FinFET process technology [link] basically terminated the intentions of Altera to commercialize FPGAs using the TSMC CoWoS process as previously disclosed [link].

This is certainly another setback for 2.5D commercialization.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

Leti / ST Micro – Interposer Fine Pitch RDL

Passive interposers redistribute the electrical lines from the attached upper dies down to the organic substrate through μPillars, RDL, TSVs and solder bumps, thus somehow acting as a pitch adapter between dies and substrate.

Backside RDL on a passive interposer can be created by either damascene integration or “conventional”  integration as shown in the figure below.

Damascene approach mainly consists in full wafer copper plating over etched trenches followed by a CMP, allowing to retrieve at the end, a fully planarized surface. This integration allows an easy access to sub-micron line/space widths but at a higher cost, mainly due to CMP steps.

Leti / ST Micro have investigated investigate the minimum pitch that could be achieved with the conventional approach. Under their conditions they were able to achieve 8um l/s with high uniformity and reproducibility.

BESI/IMEC – Handling Ultra-thin Die

The use of ultra thin die (thickness less than 50um) requires specially designed handling solutions due to their fragility and flexibility.

BESI and IMEC have examined several tape types (UV vs thermal release), ejection systems, die size (5 x 5mm; 40um thick) and bump configurations.

They also examined both face up and face down to the wafer tape:

Their conclusions include: (1) proper dice/grind and stress relief needed to maximize die strength; (2) some UV tapes resulted in residues; (3) thermal release tapes gave larger process window; (4) stable and reliable picking of ultra-thin die can be achieved with throughputs greater than 3000 units per hour using several different hardware, maerial, process combinations.

SPTS – Low Temp Via Reveal Passivation with Stress Compensation

2.5 and 3DIC wafers require backside processing including thinning to reveal the TSV, passivation, RDL and creation of copper pillar connections. Before the wafer reveal process CMOS devices are usually temp bonded to carriers (Si or glass) and thinned to ca. 50um. The temperature stability of the temporary bonding adhesive sets a limit on the upper temp of subsequent processing steps. The current goal for this temperature would be ca. 190 C.

The backside passivation also serves to maintain the bow of the thinned wafers to a manageable level (ca. ~ 10mm) to allow subsequent processing steps. Full thickness 300mm wafers (770um) typically have incoming bow in the range of 100 – 200um. If thinned to  50um and released from the carrier the 300mm wafer would show a bow of several cm making them unprocessable and potentially lead to cracking after debond. Backside passivation stress can be tailored to compensate for the incoming wafer bow. CMOS cu/low-K wafers usually show tensile stress and thus backside stresses must be net tensile to compensate.

Compressively stressed SiN films generally give the best diffusion barrier properties. For the via reveal passivation stack compressive SiN with stress of – 100 MPa was used.

SiO films deposited using TEOS based chemistry is tunable from -200 to +200 MPa, but are must be taken since tensile SiO has a limited thickness cracking threshold.

TEOS Cracking Threshold (left) and SiN Electrical Characteristics

The final solution was to develop a 190 C SiN film with a tensile stress of +200 MPa and a cracking threshold of 7um (deposited onto compressive SiN barrier).

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

 

Hope to see you all at this years RTI ASIP. It is the 10^th Anniversary of this 3D focused meeting.

 

 

Yole – FC Market & Tech Trends

Rozalia Beica, newly appointed CTO of Yole Developpement, examined the FC marketplace. The FC market is currently growing at CAGR of 19% as a result of expanded use in memory, consumer electronics and mobile phones. In 2012 bumping capacity of 14MM 300mm equiv. was in place accounting for 81% of all “mid end” capacity.

FC technology is being reshaped by the demand for Cu pillar bumping (CPB) and microbumps which are both quickly becoming mainstream. CPB is expected to show 35% CAGR over the period 2010 – 2018.

FC capacity is expected to grow in the next 5 years in response to demand from (1) 28nm CMOS application processor (APE) and baseband (BB) applications;(2) next gen DDR memory and (3) 2.5/3DIC.

 

ASE – Board Level Reliability of BoP WLCSPs

There hsas been reduction of  the production cost for WLCSP packages for the past years. Today, many OSATs are working on further cost reduction with customized WLCSP package designs that are optimized for specific market needs.

For example, omitting the UBM layer on smaller WLCSP devices can reduce costs and may still meet the market requirement on package quality and reliability. Omitting the UBM requires 25% less process steps, from 4-mask process to 3-mask process.

ASE reports on the BLR performance of a 3-mask bump on polymer (BoP) WLCSP design vs  a 4-mask BoP WLCSP design for 0.4mm and 0.5mm ball pitch using  tin/silver/copper ( SAC) and SACNi (Ni doping) solders and reports on failure analysis.

 

The polymer material can be polyimide (PI) or Polybenzobisoxazole (PBO) with thickness of  5um to 7.5um. In most BOP WLCSP packages, ASE states that PBO is the preferred material for better stress compliance, and hence better board level reliability.

For 3-mask WLCSP design, there is no UBM. The solder ball is directly attached to the redistribution layer, using polymer 2 to define the pad opening. Therefore, the electrolytic plating copper thickness for RDL needs to be sufficiently thick to avoid any problems due to Cu consumption during SnxCuy intermetallic (IMC) formation during thermal ageing. For these reasons the Cu RDL thickness is increased from 4um, on 4-mask WLCSP, to about 8um on the 3 mask process to ensure a reliable solder joint. the thickness of polymer-2 also needs to increase to 12um polymer-2 thickness to ensure line coverage. A 12um thick polymer-2 layer creates processing challenge for PI or PBO, and the thermal stress or residual stress after high temperature curing needs to be carefully controlled to guarantee the integrity of package structure.

After board level reliability test, failure analysis was performed to confirm the failure mode. The failure modes were classified as failed at PCB side Mode A, failed at component side Mode B and solder fracture Mode C. In the failure analysis, we found that BLR failure modes are governed by shear rate applied to the tested samples. High shear rate test, like drop test, tended to fail at the component side with IMC fracture (Mode B2) or residual solder on pad (Mode B3). But, for slow shear rate test, like temperature cycling test, the fail tended to occur at the solder joint (Mode C). They concluded that 3-mask the WLCSP does not change the failure mode in either temperature cycling test or drop test.

They conclude:

– BLR temperature cycling performance is governed by the WLCSP device size (DNP). The bigger the DNP, the worse temperature cycling lifetime. This was evident for both solder materials used in this study, even though the larger device has a larger solder joint size, and there was a larger difference between SAC405 devices than SACNi devices.

–  In general, the 3-mask WLCP has worse BLR performance than 4-mask WLCSP.

–  SACNi solder gives improved BLR Drop test performance (characteristic life, and first fails) for both 4-mask and 3-mask WLCSP devices.

–  They found the same failure mechanism and failure modes on 3-mask WLCSP as 4-mask WLCSP.

 

Chip Embedding at IMS

Ultra-thin chips (less than 50 μm thick) can be assembled by either on flexible films; i.e. chip-on-foil technology or by embedding them inside the foil. Initial work by the Institute for Microelectronics Stuttgart (IMS CHIPS) dealt with attempts to glue attach Chipfilm dies onto flexible foil substrates. They have now described research with less than  20μm thickness die with a two polymer (BCB and PI) ultra-thin chip imbedding approach.

Polymers used for embedding should be flexible and at the same time strong enough to keep the chip firmly embedded. To achieve an optimal solution for the desired process IMS used a combination of polymers where BCB serves as the embedding polymer for ultra-thin chips and the PI as the  reinforcement polymer. The X sectional structure is shown below.

The PI reinforcement layer provides strong yet bendable reinforcement for the entire chip stack. The BCB embedding polymer provides excellent electrical properties, low moisture absorption, compatibility with the interconnect metals and fine pitch patterning compatibility.  The process flow is shown below. An initial “adhesion lowering layer” is initially coated on the wafer to allow for package removal once the process is complete.