Insights From Leading Edge

Monthly Archives: January 2012

IFTLE 87 JEDEC Wide IO Stds, Elpida 3D shipments start while merger rumors loom , Renesas joins 3D wide IO Club; Comments from IBM on 22 nm & Beyond

JEDEC Wide IO Mobile DRAM Standards
We have been talking about the JEDEC wide IO DRAM standards for a few years. [see IFTLE 19, "Semicon Taiwan 3D Forum Part 2"]

Wide I/O mobile DRAM using 3D stacking with TSV provides "double the bandwidth at the same power, or can cut power in half at the same bandwidth" compared to LPDDR2 and LPDDR3. It is reportedly "particularly suited for applications requiring increased memory bandwidth up to 17GB/second, such as 3D gaming, HD video and user multitasking."

Click on any of the images below to enlarge them.
Well, the spec is finally finished and JESD229 Wide I/O Single Data Rate (SDR) can be downloaded from the JEDEC website [link]

Wide I/O mobile DRAM enables 3D stacking with TSV interconnects and memory chips directly stacked upon a System on a Chip (SoC).


The standard defines features, functionalities, AC and DC characteristics, and ball/signal assignments. The specification employs "LPDDR2-like" commands and timing parameters. The 512-bit memory interface has four independent 128 bits wide channels each operating at clock speeds to 266 MHz. resulting in a total bandwidth of 17 Gb/s for wide I/O SDRAMs (4.26 Gb/s/channel). The specification supports as many as four memory banks per channel, allowing die stacking of up to four wide I/O SDRAM die. The specification calls for 1.2V signal levels.

The specification also standardizes:
– Boundary scan testing (Boundary scan logic is integrated into the die for contact and I/O testing, providing full test coverage for contacts, drivers and receivers.)
– Post-assembly DRAM test. (DRAM can be tested separately from the logic chip it’s packaged with.)
– Mechanical layout of the chip-to-chip interface.
– Memory thermal sensor locations for DRAM, to provide reliable operation given thermal gradients introduced by logic chips.
JESD229 does not control the bonding configuration between the memory and logic chips – i.e. side-by-side with interposer, or stacked memory on top of logic.

The next generation of this Wide I/O SDRAM specification, already underway, will reportedly deliver eight times the performance and support 2.5D assembly.

The JEDEC committee expects wide IO memory to be in mass production by 2014.

Over the past 12-18 months we have seen wide IO adopted by all of the major memory players. Samsung [see IFTLE 40, "Samsung wide IO DRAM…"]; Elpida [see IFTLE 57 "Elpida and MOSIS Ready for 3DIC; TSV Going "Where the Sun Don’t Shine"]; Micron [see IFTLE 38 "…of Memory Cubes and Ivy Bridges"]

Elpida Starts Sample Shipments of wide IO Mobile DRAM
In late December Elpida announced that it has begun sample shipments of 4-gigabit Wide IO Mobile DRAM which will deliver increased performance and lower power consumption, aiming these products at the smartphone and tablet device markets.

By using x512-bit, a data width that is more than 10 times larger than the width for existing DRAMs, they enable a data transfer rate of 12.8 gigabytes per second (GB/s) per chip while operating at a low speed of 200MHz. The reduced DRAM speed results in approximately 50% less power consumption compared with DDR2 Mobile RAM (LPDDR2), currently the leading DRAM choice for mobile devices, configured at the same transfer rate. Elpida plans to begin volume production in 2012. Future plans are to develop two-layer 8-gigabit and four-layer 16-gigabit high-density packages for addition to the company’s product line-up.[link]

Elpida Facing Global Memory Consolidation
There are only 6 significant DRAM suppliers left in the world: Samsung, Hynix, Micron, Elpida, Nanya, and Powerchip. Elpida, born of the consolidation of the DRAM businesses of NEC, Mitsubishi, and Hitachi in 1999, is the last remaining Japanese DRAM manufacturer. "Elpida" is Greek for "hope" and like the Greek economy, Elpida, the Japanese memory company, appears to be out of hope and financially on its last leg. The major problem is that many of Elpida’s competitors have NAND to fall back on when the DRAM market is doing badly, but Elpida has only DRAM to keep itself alive.

IFTLE views Elpida as one of the bright stars of 3DIC. Last fall IFTLE discussed the Business Week proposal that memory company consolidation was on the horizon [see IFTLE 69, "Cell Phones and Memory Consolidation"], how Elpida’s financial outlook was grim and how Toshiba was the likely merger candidate. Digitimes reports that Elpida and Toshiba are in talks to merge their business operations. The merger is being "pushed" by the Japanese government, which reportedly wants Japan to keep its DRAM technology ownership on shore.

[see Digitimes Jan 3rd, 2012 "Elpida and Toshiba Reportedly in Integration Talks"]

Others are pointing towards talks between Elpida, Micron, and Nanya. Last week Reuters reported that Elpida is in talks to merge with U.S. firm Micron Technology and Taiwan’s Nanya Technology. Elpida said it would not comment on rumors and speculation. [link]

Micron has a 10-year agreement with Nanya (until 2018) to co-develop new DRAM chip technology. The two also run contract DRAM maker Inotera Memory via a joint venture. Nanya has posted losses for seven consecutive quarters but has been kept going by funds from its parent, the Formosa petrochemical group.

Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs
At the IC Packaging Technology Expo at NEPCON Japan in Tokyo, Renesas announced that it will apply TSV technology to its mobile SoCs so that they will support Wide I/O DRAM starting with mobile phone products. The DRAM will be stacked on the back of the SoC via 1,200 microbumps. The company plans to contract out the production of advanced SoCs to a silicon foundry as well as the production of TSV. [link]

IBM Comments on 22 nm and Beyond
Subu Iyer, IBM fellow, noticed that I have been using the IC consolidation slide (below ) shown by Handel Jones of Int Business Strategies (IBS) at the Semi ISS meeting in 2010. [see PFTLE 121, "IC Consolidation, Node Scaling and 3DIC"]

Dr. Iyer informs IFTLE that IBM does not build a fab for every node except when there is a change in wafer size. "Our approach is to achieve a soft transition from one node to the other. As you may know we develop technology not just for IBM but also for Samsung, GF,ST and many others … so as these development programs are complete, the SOI technologies are manufactured at IBM and the bulk technologies are transferred to our partners. Our current fab has transitioned from 130 to 90 to 65 to 45 to 32 nm in the last 10 years or so … we expect this approach to continue. It is unlikely that we will outsource chips that we make for our mainframes, supercomputers etc. We only outsource OEM chips." IFTLE thanks Subu for that clarification.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE…………………

IFTLE 86 3D Headlines at the RTI 3D ASIP part deux

Continuing  with key developments at the 2011 RTI ASIP

 ST Ericsson / CEA Leti / Cadence
One of the best received presentations of the conference was “A Three-Layers 3D-IC Stack including Wide IO and a 3D NoC – a Practical Design Perspective –“ by Pascal Vivet, and Vincent Guérin. Going well past their allotted time during the scheduled presentation, they were brought back ( by yours truly) after the session ended to answer questions for a further 45 minutes. While some of the presentation was beyond the capability of the management and process development audience, the importance of the contribution was crystal clear to everyone.


 “Wioming” is the first application processor SOC integrated with a Wide I/O memory interface which should enable superior graphics and CPU performance in smartphones and tablets. It  is a high speed CMOS, TSV middle process with:
– multicore CPU backbone
– 4 wide IO memory controllers. Belived to be the first implementation of the JEDEC wide IO standard.
– 3D asynchronous network on chip (NoC) for logic on logic stacking


Scheduled for build are:



– Uses ST-Microelectronics high-speed CMOS library                                                                    
– Uses TSV middle (10μm) + Copper Pillar (10μm)                                                                                              – Flip-Chip packaging assembly                                                                                                                               – Face2Back, Die to Die 3D stacking assembly                                                                                                     – uses Cadence “Encounter 3D-IC” design implementation
Was taped out in fall 2011 and is currently in fabrication.
There is reportedly a ST Ericsson wide IO application processor product  in planning that will use TSV technology.  

IBM

Dan Berger IBM Manager of  “3Di” development reiterated a concept that we have heard before from IBM namely that “You need a bullet proof TSV formation process to make this all work” and that right now the “Supply chain is the toughest nut to crack – It’s good to be an IDM”. IBM is currently using 45 nm CMOS and 130 nm SiGe chip processes on a 2.5D interposer with 90 nm wiring for their Semtech products, announced last fall [ see IFTLE 27,“Era of 3D IC Has Arrived with Samsung Commercial Announcement”] which are produced in Fishkill  and their recently announced involvement with

 Micron on their memory cube commercialization [ see IFTLE 74, “The Micron Memory Cube Consortium” ].

Yole Developpment
Yole’s Perkins commenting on the TSMC statement pointed out that there’s lots of money in play here, and other people ( OSATS) aren’t going to just walk away, but are going to look for alternative solutions. The now annual Yole 3D timeline is updated below.

STATSChipPAC [SCP]
Raj Pendse, VP and CMO for SCP gave an in depth  presentation on their thoughts and approach to advanced packaging and 2.5/3D.

Sematech

Sematech’s  Arkalgud detailed the work at the Sematech “3D Enablement center” where the primary focus is on Wide IO DRAM for mobile and high performance applications.

   Their goal is to “..provide clarity and help identify gaps in standards, specifications and  technologies” Arkalud also indicated that Sematech is looking at next generation work on low time/temp Cu-Cu bonding technology that they are not at liberty to fully disclose yet.


Without providing specifics, one of the conclusions from their Sematech cost analysis is that “3D interconnect can lower the overall cost of ICs”
ASE
Hwang of ASE showed excellent electrical performance data for Cu bonded structures.

Qualcomm
 Ray of Qualcomm said that they have determined that form factor and performance are the  most critical elements for them and that the smallest form factor comes from 3D stacking so they would most likely go directly to 3D stacking.  
Synopsys
Michael Jackson of Synopsis presented the following slide to rationalize why 2.5D is happening before  full 3D stacking.




EVG
Mathias of EVG updated their status on the Zonebondâ??¢ process . We have discussed the technical details of Zonebond previously [ see “Is 3D Packaging Where it Needsto Be?” ] The EVG position is that:
 EVG has worldwide access to Brewer Science  ZoneBONDTM technology, including:
 – The right to sublicense to any EVG equipment customers.
 – The right to produce carrier wafers and EVG equipment customers  to do so.
 EVG owns own IP related to the ZoneBONDTM process and to ZoneBONDTM equipment and as shown below the right to use any materials for the process including .
– thermal release materials
– UV/IR release materials
– designated solvent release materials – thermal release materials
– UV/IR release materials
– designated solvent release materials

For all the latest on 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦..


IFTLE 85 2.5/3D Headlines at the 2011 RTI ASIP

Research Triangle Institutes 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the “3D conference circuit” for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7th 3D ASIP in Burlingame CA a few weeks ago, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.

TSMC                                                                                           

Much of the “buzz” at this years meeting certainly centered around the presentation by TSMCs Doug Yu a regular attendee of this meeting. Yu repeated the case he had made earlier at  the  Georgia Tech Interposer Conference [see IFTLE 80, “GIT @ GIT” ], for the pure foundry model for 2.5 and 3DIC,

stating that TSMC was readying full beginning to end interposer manufacturing. Yu told the audience of more than 200 that sharing the fabrication process with OSATS was not the preferred option for TSMC because “â??¦the risk for the customer is too high” and therefore TSMC would “ take full responsibility and accept full risk”. TSM is proposing that such one stop shopping ( at TSMC) will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Since the profit margin for packaging and assembly is currently substantially less than that for a foundry like TSMC manufacturing chips, cost sensitive customers appeared worried that packaging and assembly costs would increase substantially if turned over to foundries. Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing. “This is a new ballgame, the old ways of doing business are out of date for this new technology” Yu reiterated. Rumored to be currently working with only a handful of 2.5D/3D customers ( including Xilinx), Yu indicated that “â??¦new customers will have only the  integrated solution proposalâ??¦..some, but not all of them [customers] want us to work with other partners, but many like our new approach very much".

Certainly with their customer Xilinx being first to enter the market with their 2.5D based Virtex 2000T FPGA, TSMC appears ahead of the rest of the foundries in this regard. Currently, TSMC is manufacturing the Xilinx chips and manufacturing and bumping the Xilinx interposer. Xilinx is using Amkor to assemble the FPGA chips on the interposer and the interposer onto a BGA package.  Since the interposers are using 65 nm dual damascene processing for the multiple layers of RDL, in reality this is something that  the assembly houses currently aren’t equipped to handle. More on that below.

When asked about the incorporation of other foundries chips onto the interposer or chip stack, Yu responded that there is no need to go to other foundries / IDMs except for memory, and that TSMC would partner with one or more memory suppliers to have that issue resolved.
                                    Cho (Samsung) and Yu (TSMC) enjoying lunch at ASIP.                                
  Is Samsung a potential 2.5/3D partner for TSMC ?  
Microelectronic Consultants of NC

During my presentation detailing the status of 3DIC entering 2012, the issue of interposer categories came up. Basically interposers can be categorized as either being high density l/s ~ 1µm /1 µm which could only be manufactured by CMOS fabs/foundries and what we can call “coarse” featured interposers with l/s > 5 µm / 5 µm. The latter could be fabricated by ay of the OSATS who all have standard bumping and WLP processes capable of standard RDL. In a later presentation (IFTLE 86 next week) Raj Pendse of STATSChipPAC indicated that 5 um l/s and sub 25um TSV pitch was the transition point between OSAT and foundry capability

While all the OSATS have such capability, products have not yet been announced that would use such course dimensioned interposers and none of the OSATS have announced any intention to produce any interposers.   One OSAT requesting anonymity later commented “It is correct that we are not offering “coarse” interposers , although we have capability to produce them – this is because we don’t see ourselves competing in that space with foundries and don’t think it will be a viable biz worth chasing and investing capital and resources in”. Eric Beyne, I MEC, during his presentation also questioned whether coarse interposers would provide enough value to be integrated into products.  Similar responses were received from other OSATS in attendance.

Despite those comments, unsubstantiated rumors swirled at the conference that Siliconware had or was about to purchase a complete 2.5D/3D line from Applied Materials which included dual damascene capability so they could enter into manufacturing of high density interposers. Neither Applied nor Siliconware [SPIL] would confirm or deny the rumors, but it was interesting that SPIL customer, graphics chip maker NVIDIA in their presentation (see below) indicated that they would require 2.5D soon.
If the SPIL rumor is true, such a play might force other OSATS to follow suiteâ??¦.we shall see.
NVIDIA
LeiLei Zhang, of NVIDIA, made what could become the rallying cry of the upcoming 3D decade when she said  “Scaling is ending. Let’s get over it and move our resources elsewhere.” Zhang declared that for them bandwidth is the issue. She indicated that NVIDIA is likely to use a turnkey solution such as TSMC is offering with such 2.5D TSV solutions entering the NVIDIA roadmap with their TESLA and CUDA high end networking GPU product lines.   

Although she wouldn’t indicate who her fabricator partner was, Zhang detailed the Nvidia Interposer program Status as follows:
– Demonstrated working process on very difficult test vehicles
– Reliability data looks OK but limited
– Long development cycle time
– Need more industry resources – both equipment and manpower
– Thin wafer Transport not Advised
– Assembly yield limited by Interposer warpage
– Non-wetting µbump
– Need Assembly Process, die thickness, µbump, materials optimization
– Biz model unclear
– Must choose between traditional supply chain & full turnkey solutions
Xilinx
Ivo Bolsens VP and  CTO of Xilinx detailed their Virtex 2000T FPGA which he claims delivers 4X the compute performance  as the current largest monolithic device. IFTLE has previously covered the performance of this device in detail. [ see IFTLE 73, “Xilinx shows 2.5DVirtex 7 at IMAPS 2011” ]
Altera
 While Altera’s Bradley Howe predicted that “â??¦there are 8-10 years left to scaling, and then 3D will be the solution” he was quick to show 2.5D prototypes they are reading for the market, evidently a lot earlier than that. With arch rival Xilinx already sampling the market with 2.5D products that’s probably a good idea.
Seen at the RTI ASIP:

Next week we will finish up coverae of RTI ASIP. For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦

        

IFTLE 84 …. and the Winner is

Well, all the ballots have been cast. The winner of our contest was determined by who could correctly identify the most  faces that they had seen previously in the pages of  PFTLE/IFTLE â??¦and the winner is…… Dr. Beth Kesser of Qualcomm who correctly identified 38 .

Dr Kesser was shipped MRS volume 970 "Enabling Technologies for 3D Integration" edited by Bower, Garrou, Ramm and Takahashi. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s interests include developing materials and packaging technologies for the semiconductor industry, which has resulted in 7 patents, 5 patents pending, and over 33 publications in this area. Currently, Beth is the Wafer Level Packaging Product and Technology Manager at Qualcomm in San Diego. Also, Beth is the Assistant Program Chair of the 62nd ECTC to be held in San Diego, CA in May 2012 and was just elected to the IEEE CPMT Board of Governors. 

 The correct names and affiliations are shown below:

 A few fun points:
1) Most recognizable were Jack Nicholson (every single ballot got Nicholson correct!), Dora, Koyanagi-san, Morris Chang, Bob Patti and my granddaughter .
2) Most misspelled name – Ron Homuler or is it Huemoller or as one respondant labeled him  hummuler. Ron – They knew who you were but had trouble with the spelling!
For all the latest in 3DIC and advanced packaging stay linked to IFTLE……….

IFTLE 83 Orange County IEEE CPMT 3DIC Workshop

In early December the Orange County chapter of IEEE CPMT held a 1 day workshop entitled "3D Integrated Circuits: Technologies Enabling the Revolution," which included presentations by Xilinx, IMEC, Mentor Graphics, FCI, Microelectronic Consultants of NC, STATSChipPAC, Henkel, EPWorks and Apache (Ansys). The General Chair was Larry Williams from Ansys and the technical chairs were Don Frye from Henkel, Bob Warren from Conexent and Sam Karikalan from Broadcom. In the true spirit of information sharing, the intentionally low fee of $40 drew over 200 attendees for the event.

Eric Beyne of IMEC took a look at 3D challenges and progress. The standard IMEC TSV are 5 x 50um for 3D stacking moving in the future to 3 x 50 and for 10 x 100 for 2.5D interposers.

Beyne notes that nearly all options for debonding from carrier wafers are moving to RT solutions. The previously well accepted slide debonding has a small process window and is difficult with bumps on the glued interface. Brewer Science in conjunction with EVG and Suss Microtech are now promoting the Zonebond process which uses a RT release process.

As a cost reduction option, IMEC is studying the elimination of the CMP process for wafer thinning to 2um TTV on 300mm wafer down to 50um thickness. Beyne favors laminated WUF (wafer level underfilling) vs NUF (no flow underfill pre applied to the substrate) commenting that "Probably lamination is the way to go since it covers the fragile ubumps with UF before the assembly process so it’s better to handle." In addition one achieves lower surface topography using WUF.
Ted Tessier, CTO of Flip Chip Int (FCI) addressed their embedded die packaging JV with Fujikura. Fujikura’s “WABE” technology (Wafer And Board Level Device Embedded technology) involves stacking and lamination of multiple layers of Cu/PI printed circuit layers around embedded, thinned die and passive components and via filling with conductive paste. Packages can be fabricated in either a face up or face down orientation with backside thermal via options available for improved thermal performance. Multiple die and passive components can be integrated at die spacing as tight as 100um. Passive components can be embedded as well. Processing panel size is currently 250 x 350mm.

Prof Muhannad Bakir of GaTech addressed his specialty 3D stacking with liquid cooling where significant reductions in power and temperature can be achieved. Most agree that some sort of liquid cooling will be necessary for server farms in the future to reduce power usage.

Stephen Pateras of Mentor Graphics looked at the challenges and solutions for 3DIC test.
Gusung Kim CE of EPWorks, the Korean startup offering interposers indicated that customers want interposers at the same prince as high end laminate, i.e. $300/wafer for a 300 mm wafer of interposers. Kim offers glass interposers but sees most programs currently moving forward on silicon. He sees 100 um TGV (through glass vias) doable (in 100 thick glass) , but customers are asking for 10 um TGV.
David Butler, VP of Marketing for SPTS gave a nice update on their equipment for Via Reveal – High Rate Si Thinning and Low Temperature Dielectrics for Post-TSV Processing.

SPTS recommends stopping the grind ~5-10um above the TSV so you don’t expose Cu because exposed Cu would migrate. Then one selectively etches Si to ~5-7um below the oxide cap without removing the oxide. The surface is then coated with nitride (for migration barrier) and then oxide, then, after resist definition, Cu is exposed by oxide etching and RDL is built upon the exposed Cu studs.
In the SPTS tool different etch modes are used to control the etch uniformity which reportedly is typically +/-4% with a built-in etch stop process.



Low Temperature (175C deposition ) SiN Barrier is in 300mm production on CMOS image sensor. It is reportedly a dense film with <100MPa residual stress and excellent adhesion and electrical properties. Low Temperature PE-TEOS SiO2 is deposited at 175C with low leakage and high breakdown voltage. Etch and deposition are available on one or multiple platforms.

Coming up next — an extensive review of the RTI 3D ASIP Conference………

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………….

IFTLE 82 3DIC at the 2011 IEEE IEDM and other 3D and Adv Pkging topics

My Christmas and New Years time off was great; hope yours was too. Hannah and Madeline got their letters of to Santa and I had a great Texas Christmas with the grandaughters.

…and now back to 2011 conference coverage…

2011 IEDM

3DIC presentations at the recent IEEE IEDM Conference focused on potential reliability concerns.

ST Micro / Leti reported on two potential reliability issues for direct bond copper — namely stress induced voiding and electromigration. Electromigration (EM) and stress-induced voiding (SIV) testing was performed on bonded daisy chains to investigate the reliability of the structures. Test vehicles were wafers bonded at room temperature, atmospheric pressure, and ambient air and then annealed at 200°C or 400°C to strengthen the bonding.

In some NIST-type devices, they observed voids at the cathode side and copper extrusion next to the anode pads after 200°C post-bonding anneal and exposure to 325°-350°C and 3-3.5 MA/cm2. Time-to-failure (TTF) is defined as a 10% resistance variation. They make arguments to support the conclusion that the Cu-TiN interface appears to be the dominant pathway for EM — not the Cu-Cu bonded interface as might be expected. On some tested die they observed voids and copper extrusion on both opposite sides of the daisy chain showing that the structure acts as one continuous interconnect without interface separation between copper lines on the two bonded levels. In standard copper interconnects and vias chains, each copper line is separated by the metallic barrier between the line and the vias.

SIV testing of the daisy chains interconnected by direct copper bonding process after 400°C anneal and thermal stressing at 175°C-200°C and a current of 1mA for 2000hrs showed no degradation, i.e. less than 5% resistance change for all the tested samples.

They conclude that: "Direct copper bonding does not impact on the failure mechanisms concerning Cu interconnect reliability."

Koyanagi-san and his group at Tohoku University reported on their studies on W / Cu hybrid TSVs. They propose that high-density 3D-LSI die requires more than 104-105 μbumps and TSVs per chip and die thickness of <10μm with near zero remnant stress. Due to this, W TSVs may outperform Cu TSVs not only due to their ability to form sub-micron vias, but also since W does not diffuse in silicon the way Cu does, and leaves very minimum stress in active Si owing to smaller difference in CTE between W and Si. Therefore, W-TSV is preferable for high-density and high-speed TSVs with small diameter and small capacitance for signal lines.

However, W-TSV is not as suitable for power/ground (GND) lines because of its higher resistance. Cu-TSV with larger diameter and lower resistance should be employed for TSVs for power/GND lines. Cu-TSVs with larger diameter are also more preferable to suppress Cu diffusion since a barrier metal such as Ta can be conformally and uniformly formed into deep trench for TSV which effectively suppresses Cu diffusion. One can also suppress the influences of Cu diffusion on device characteristics by placing Cu-TSVs for power/GND lines apart from the active areas. Thus, the Tohoku group proposes a high-density 3D-LSI using W/Cu hybrid TSVs.

μ-Raman spectroscopy revealed that mechanical stresses increase with an increase in TSV diameter for both Cu- and W-TSV. They conclude that Cu-TSV with the size of <10μm and W-TSV with the size of <1μm leave only compressive stress in the TSV spacing region when the TSV pitch was smaller than twice of TSV size. It is important to increase the TSV pitch to larger than 2�? the TSV size to avoid peeling (inside the via), extrusion of the via metals, and cracking of the LSI die. Residual stress in thinned die changes from compressive stress for the die/wafer thickness of >100μm to tensile for thicknesses <30μm. They warn that "tensile stress leads to die-cracking due to weakening of Si-Si bond, which is a threatening issue in 3D-LSIs."

Farooq of IBM detailed their reliability studies (thermal cycling >500 cycles) and thermal stress (>275°C for 1500 hr) on 3D modules built by integrating Cu TSVs with high-k/metal gate and embedded DRAM.

They found no degradation of TSV or BEOL structures, and show that there is no significant impact on device characteristics from TSV processing and/or proximity.

TSVs were integrated at fatwire (upper metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD), built on SOI and bulk Si wafers. TSV of <100μm depth were etched with near vertical sidewalls at a minimum pitch of 50μm. An example of this is shown below.

TSV and BEOL structures did not degrade after 500 thermal cycles (-65°C-150°C), and no change in either the leakage or the wiring resistance was observed. Structures consisting of wiring and via chains above and near the TSV also showed no degradation after thermal cycling. Wafers baked at 175°C-275°C for 1500hrs showed no voiding or delamination occurred near TSVs. Frontside and backside wiring levels on a thinned wafer were connected with TSVs to create chains of 3000 links; the chains showed no change in resistance after 500 thermal cycles.

TSV insulator breakdown voltages of 250V-300V were observed.

They observed that significant shifts in device characteristics were possible for some processing conditions, in particular "FET Vt was shifted under certain etch conditions" but optimizing the etch process minimized this impact. In general, they concluded: "With optimized design and processing, stress fields associated with TSVs are significantly lower than those required for strain engineering of the devices, and are not expected to shift device characteristics."

More detail is available here [link].

Honeywell and Tezzaron to build rad hard 3D-ICs

Honeywell Microelectronics and Tezzaron Semiconductor have announced that they will be working together to produce radiation-hardened 3D integrated circuits. Honeywell’s S150 process will use Tezzaron’s 3D stacking to greatly increase circuit density without migrating to a smaller node. The resulting three-dimensional integrated circuits (3D-ICs) are also expected to use much less power than their 2D counterparts. Tezzaron CTO Bob Patti commented: "Memory can now be integrated vertically rather than embedded in the logic die. The current practical limit is around 32 Megabits, but 3D could put as much as 4 Gigabits of high-quality DRAM onto a single rad hard chip."

Tezzaron also announced a research collaboration agreement with the A*STAR Institute of Microelectronics (IME). The two organizations will improve and refine the design and manufacture of silicon interposers and work to standardize the process, flows, and process design kits (PDKs). Initial early production devices are already in development, based on IME’s TSI (through silicon interposer) technology and incorporating 3D-ICs from Tezzaron. Fabrication will be completed in IME’s state-of-the-art 300mm R&D fab. The resulting TSI technology from the collaboration will form the foundation for the TSI Consortium driven by IME, to be launched in early 2012.

IME and Tezzaron have a history of cooperation dating back to 2001, when IME provided its copper line technologies to Tezzaron for their wafer stacking endeavors.

LED testing update

We are now 4+ months into our lightbulb testing and I am happy to report that both bulbs (LED and CFL) continue to burn bright — as well they should, since you will recall the average life of an incandescent is ~1 year. [ see IFTLE 63, "Bidding adieu to Lester Lightbulb."

I have come across an interesting article which tries to explain the new light bulb test protocols and adds to what I tried to explain [link].

The winner of the contest will be announced next week — along with the answers to who all those people were!

For all the latest in 3DIC technology and advanced packaging stay linked to IFTLE……….