By Dr. Phil Garrou, Contributing Editor

ASE seeking ~ 25% stake in SPIL

By now, you have seen the news that ASE has made an offer to buy up to 25% of the shares of competitor SPIL at a 34% premium. [link]

For those of you following IFTLE, this attempt at further industry consolidation should not come s a surprise [see IFTLE 163, 195, 231, 241], although some would have predicted that offers for the big 4 OSATS would come from foundries or China Inc, not fellow OSATS.

Although ASE is making statements like “…this is not a hostile takeover” , “…ASE is seeking cooperation rather than competition”, and that this “…is purely a financial investment, and ASE will not intervene in SPIL’s operations” this is the kind of move that clearly precedes a takeover attempt.

ASE and SPIL currently have 19.1% and 10.1% shares, respectively, in the global IC packaging and testing market. The planned ASE-SPIL integration will widen the market gap against rival companies, including Amkor Technology, which has a 12% share and China-based JCET with a 10% share [link]. JCET’s acquisition of STATS ChipPAC was the first major consolidation move amongst the top assembly houses. After acquiring STATS ChipPAC in 2015, JCET now has a production capacity almost equal to SPIL. If this ASE / SPIL goes through, the pressure will on Amkor to make a move beyond J-devices.

TSMC offered “ no comment ” on the ASE bid offer [link]. ~ 90% of the backend packaging for TSMC’s fabless clients is decided by their customers. Although TSMC works with both ASE and SPIL, many customers report that TSMC appears to have a closer relationship to ASE who they use, for instance, to backup to their internal bumping capacity.

With their recent major move into packaging, TSMC is becoming a competitor to both ASE and SPIL and rumors have circulated that TSMC could acquire one of the OSAT assembly houses.

By the end of the week Hon Hai Precision Industry (which some of us remember as Foxcon the board stuffer) and SPIL announced a strategic alliance via a share swap to reject this ASE hostile takeover of SPIL [link].

TSMC and Huawei develop 2.5D 16nm Networking Processor Module

Despite earlier delays [see IFTLE 228, “Samsung Goings On”] TSMC, during its Q2 earnings call, announced that the chipmaker has begun volume shipment of chips based on its 16-nm FinFET manufacturing process.

One of their first 16nm development projects has been with HiSilicon, the chip design division of China’s telecommunications company Huawei. They have produced an ARM-based 32-core, 64-bit networking processor using TSMC 16nm FinFET manufacturing process. [link].

TSMC has stated that HiSilicon’s processor is the first fully functional networking processor implemented on its 16nm FinFET manufacturing process. As well as using the 16nm FF process HiSilicon used TSMCs CoWoS silicon interposer 2.5D packaging technology to combine the 16nm logic chips with a 28nm logic chips.

The 32-core ARM Cortex-A57 processor is aimed at wireless communications and routers and achieves a clock frequency of 2.6-GHz for next-generation base stations, routers and other networking equipment. 

TSMC to cease solar manufacturing

Through the last decade TSMC has wisely expanded into packaging, MEMS and LEDs so it was to be expected that they would also try their hand at solar. Well that experiment looks like it is over. TSMC has announced that TSMC Solar, its 100%-owned subsidiary, will cease manufacturing operations at the end of August 2015 as TSMC believes that its solar business is no longer economically viable [link].

TSMC has come to the conclusion that despite what it considers as its world-class conversion efficiency for its CIGS [Copper indium gallium (di)selenide ] technology, TSMC Solar will not be viable even with the most aggressive cost reduction plan.

“Despite six years of hard work we have not found a way to make a sustainable profit,” said Steve Tso, chairman of TSMC Solar and senior VP of TSMC.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

A few years ago in IFTLE 62, we laughed when EE Times reporters got confused and unknowingly compared 3DIC to 3D finfets thinking they were the same thing. Well, things have now gotten even more confusing as the key NAND memory manufacturers have announced commercialization of vertical – NAND memory products which some are calling 3D NAND.

We have noted before that 3D ICs can be categorized as either (A) 3D Stacked ICs (3DIC), which refers to stacking and bonding thinned IC chips using TSV interconnects, or (2) monolithic 3D ICs [see IFTLE 177, Monolithic 3DIC….] which use sequential fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy which result in direct vertical interconnects between device layers. V-NAND is an example of the monolithic approach.

Toshiba TSV stacked NAND

Last week, in IFTLE 250, we noted that Toshiba had just announced the world’s first NAND flash memory packages, which stack eight or 16 dies of NAND flash memory devices and feature 128GB or 256GB capacities. Toshiba’s new stacked NAND flash packages integrate (16) 128Gb NAND memory devices connected together using through silicon vias. The multi-layer chips by Toshiba feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50 percent less energy on write operations, read operations, and I/O data transfers than Toshiba’s current products.

The NAND flash memory chips are designed for low latency, high bandwidth and high IOPS/watt flash storage applications, including high-end enterprise SSD. For example, (64) 256GB multi-layer chips would provide 16TB of NAND flash storage, but in order to build such a drive a special controller and other peripherals would be needed.

Toshiba did not say if or when it plans to release its new TSV-based NAND flash memory devices commercially.

PMC Sierra had a working SSD demo at the 2015 Flash Memory Summitt which used the new Toshiba TSV stacked memory (see below). [link] They report that the upfront costs are minimal ( prices for these TSV stacked NAND chips have not been released publically) compared to the long term costs due to power consumption differences. PMC Sierra demonstrated a significantly higher power efficiency for the TSV flash vs standard non-TSV flash for high end enterprise storage. Such power efficiency would also positively impact consumer notebook battery life.

V- NAND

Vertical NAND memory devices, V-NAND, which some like Intel are calling 3D NAND, are fabricated sequentially and are connected on the cellular level as they layers are built.

Samsung has been working on V-NAND the longest (over a decade) announcing V-NAND based SSD, for use in enterprise servers and data centers, in 2013 and commercializing a 1 TB SSD last summer. Soon after Toshiba, SK Hynix and the Micron / Intel JV IMFT also announced V-NAND roadmaps.

From what has been publically reported, IMFT and Hynix have chosen to stack the current floating gate cell architecture ( the architecture for the vast majority of current 2D NAND) while Samsung and Toshiba have each chosen completely new vertical architectures for their V-NAND technologies. For those with interest, a comparison of these architectures has been published by NCTU Taiwan [link]

So, it looks like NAND can be manufactured both by TSV based 3DIC stacking and by 3D monolithic fabrication.

Are the advantages of TSV based NAND significant enough to compete with monolithic V-NAND which is being commercialized by all the key NAND suppliers ?

What applications would TSV stacked NAND be superior in?

Will Toshiba really commercialize two competing memory stack technologies at the same time?

As these answers become apparent, we will let you know.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Wow, the big 250!

Thanks to all of you that continue to read my updates and opinions. Thanks to all of those who have supplied me information to pass on to all of you.

I have told many of you that these blogs are my way of keeping myself up to date. I’ll keep doing these as long as I’m still having fun and as long as Extension Media and Pete Singer want me, too.

Before we get to some major 3DIC news, long time readers know I never miss a chance to update you on how my granddaughters are doing. Hannah (11) and Madeline (7) were in NC visiting a few weeks ago, so I will share this shot with you.

 

and now the news…

Toshiba Extends TSV Memory Stacking to NAND

IFTLE (Insights From the Leading Edge) which started in August of 2007 as Perspectives From the Leading Edge in the now defunct Semiconductor International has mainly focused on advanced packaging with emphasis on 3DIC since that was the hot and coming technology. By blog #12, I announced that Toshiba had would be commercializing CMOS mage Sensors with TSV (albeit one layer devices, but most would conclude, like I do, that this was the commercial start of what we now call 3DIC.

It is therefore somehow fitting that as I hit IFTLE 250 (and IFTLE + PFTLE 378 ) that Toshiba would be the first to announce the extension of TSV technology to NAND. [link] For years, I have been taking the position that NAND could not come till DRAM was commercialized since it is a less costly product. Well, since TSV DRAM has now been announced in many forms by the major DRAM players (Samsung, Hynix and Micron) I guess its now time for the NAND announcement.

Toshiba’s TSV technology achieves an I/O data rate of over 1Gbps which is higher than any other NAND flash memories with a low voltage supply (1.8V to the core circuits and 1.2V to the I/O circuits) and approximately 50% power reduction of write operations, read operations, and I/O data transfers.

They see this stacked NAND flash memory providing the ideal solution for low latency, high bandwidth solutions in flash storage applications, including high-end enterprise SSD.

 

Sold as 152 pin BGAs, the 8 stack modules are 14 x 18 1.35mm and the 16 stack devices are 14 x 18 x 1.90mm. 

UMC Enters HVM on SI Interposers for AMD FIJI

We announced the AMD FII graphics processor would use high bandwidth memory and silicon interposers in IFTLE 240 “AMD Introduces HBM on Fiji R9 390X GPU.”

 

It has recently been announced that the silicon interposers are being supplied by UMC making them the second entrant into the commercial silicon interposer business (after TSMC and their CoWoS process). The interposers are reportedly being manufactured by UMC in Singapore, at 300mm Fab 12i.

The GPU package, measuring 50 x 50 mm, will actually reduce the graphics card PCB size, because the memory has been moved to the GPU package, with four 1024-bit HBM1 stacks surrounding the GPU die (n the package see below). 1GB of HBM memory takes up 95 percent less than the same amount of GDDR5 memory, so you free up a lot of room on a circuit board. AMD has yet to announced whether their next gen Greeenland GPUs, which will use HBM2 memory stacks will be made on TSMC’s 16nm or Samsung’s 14nm process.

SK Hynix ships their HBM stacked to UMC who integrates the HBM stacks and GPU onto their silicon interposer for AMD.

Nvidia Pascal Coming in 2016

Not to be outdone by AMD, Nvidia has announced further details on the their Pascal graphics processor due out in 2016.

Nvidia’s Pascal GPU ( GP100) will feature a 4096 bit bus and four HBM2 stacks each up to 8 memory layers. The Pascal chip set will reportedly be manufactured on both TSMC’s 16nm FinFET process [link 1] and Samsungs 14nm FinFET process [link 2] later next year. Rumors are that Nvidia has taped out the GP100 at TSMC and thus should be expecting the first chips from them in Q2 2016. The GPU will be made with either 4 or 8 memory layers in the HBM stacks. They believe the Pascal GPU will be able to achieve 10x better performance compared to Maxwell.

OK, Intel, your turn…we’re waiting !

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

Merger Mania or Economics 101?

SST has recently shared an article by IC Insights entitled “Tsunami of M&A deals underway in the semiconductor industry in 2015.” [link]

While IFTLE certainly agrees with their conclusion, that mergers are occurring on a larger scale and more rapidly than in the recent past, we do not agree with their characterization “…It would be hard to characterize the huge wave of semiconductor mergers and acquisitions occurring in 2015 as anything but M&A mania, or even madness.”

As IFTLE has been preaching for some time now Economics 101 tells us that this is the natural evolution of any industry. As was explained in IFTLE 241 “Simply Obeying the Laws of Economics” [link] all industries go through cycles or stages as they mature and most of our industry is now in late stage 3 or early stage 4. IBM saw what was going on, assessed their position and got out.

A major part of these later stages is consolidation (or M&A deals). Our industry has always gone through boom or bust cycles, the difference this time is we are further along the industry maturity pathway. Actually economics also tells us that as this massive consolidation occurs those that remain will actually see less of the boom-or-bust cycles because the industry as it matures will stabilize. Those that understand this understand that we are getting ever closer to the “acquire or be acquired” phase in the electronics business and they are making their moves. Those that don’t….well they won’t be around to much longer. Still confused? Try:

 

That said, IFTLE certainly agrees with the closing statement of the IC Insights article “…the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrates the maturing of the industry… The strong movement to the fab-lite business model, and the declining capex as a percent of sales ratio, all promise to dramatically reshape the semiconductor industry landscape over the next five years.”

Wide Band Gap Semiconductors Require Advanced Cooling Solutions

While much of our industry is maturing (as discussed above) new segments are always evolving. Wide bandgap semiconductors is such a new semiconductor segment.

Wide bandgap (WBG) semiconductor materials allow power electronic components to be smaller, faster, more reliable, and more efficient than their silicon based counterparts. These capabilities make it possible to reduce weight, volume, and life-cycle costs in a wide range of power applications. WBG semiconductors have great potential as enabling materials in high-density power applications, satellite communications, and high-frequency and high-power radar making them the darlings of the defense industry.

WBG materials have the potential to:

Reduce energy losses: Eliminate up to 90% of the power losses that currently occur during AC-to-DC and DC-to-AC conversion.

Higher-voltage operation: Handle voltages more than 10X higher than Si based devices, greatly enhancing performance in high-power applications.

Higher-temperature operation: Operate at temperatures over 300°C (twice the max temp of Si-based devices).

Higher frequency operation: Operates at frequencies at least 10 times higher than Si-based devices, making possible new applications, such as radio frequency (RF) amplifiers. [link]

WBG Thermal Challenge being addressed by DARPA

While WBG materials are rapidly gaining acceptance in numerous applications, one of the challenges that remains to be addressed to fully exploit the promise of WBG semiconductors is thermal management . Alternative cooling solutions will be required to withstand the high temperatures of WBG devices.

DARPA has been addressing this issue since 2013 under their MTO ICECool program headed up by Dr. Avram Bar-Cohen. Bar-Cohen, recently recognized by IEEE with the IEEE CPMT field award (the highest level packaging award available in the IEEE) is regarded as one of the world experts in thermal management issues.

The ICECool program has many of the countries key aerospace companies such as BAE, Boeing, HRL, Lockheed Martin, Northrup Grumman and Raytheon, developing solutions for this WBG thermal problem.

The key vs previous thermal solutions (see figure below) is to remove heat at the chip as close to the transistor heat generation as possible.

Although I cannot share the specifics with you here (ITARS restrictions), I can say that significant advances are being made in several of the ICECool programs that should allow WBG semiconductors to make major impact on our microelectronics future.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…