By Dr. Phil Garrou, Contributing Editor

It’s that time of year again when Hanna and Madeline wish a very Merry Christmas to all…

December is also the final 3D conference of the year, RTI Internationals 3D ASIP conference in Burlingame, CA. Over the next few weeks we will be looking at the remaining content from the GaTech Interposer Conference and the RTI 3D ASIP conference.

Global Foundries

Zafer Kutlu of GlobalFoundries updated the audience on the “Status of Manufacturing and Design of 2.5D Packaging Technology” at his company. The GF open supply chain includes EDA and IP partners Cadence, Synopsys and Mentor Graphics and OSAT partners Amkor, ASE, STATSChipPAC and SPIL and memory stack supplier Hynix.

The ATACAMA test vehicle, was used for tool/line setup, base investigation on interposer design and processing, supply chain setup. The KALAHARI technology baseline qualification test vehicle, for CPI qualification and final inputs to DM and PDK.

Kutlu announced that they would be ready with PDK Rev 1.0 in 1Q 2015.

Ga Tech

Muhannad Bakir of GaTech was invited to share his concepts on silicon bridge interconnects and 3D micro fluidic cooling solutions that he is working on for the DARPA ICECool program. Bakir was asked to “Bring the real Data” and that he did as you can see from the picture below.

Bakir brought Data to 3D ASIP

Concept 1 is a linking interconnect technology that use self aligned silicon interposer tiles and bridges. The tiles are aligned using pyramidal pits etched in the silicon and mated with 300um solder balls (as shown below) The interposers can be linked and interconnected using the same ball and socket alignment concept. Connection between interposer and mother board or chip and interposer is made using the GaTech “spring”  interconnects as shown. Although I am not yet sold on using the spring connection in HVM, we will keep an eye on this technology as it is developed.

The second concept pertains to microfluidic cooling for silicon interposer modules.

Silicon dice with electrical microbumps, fluidic microbumps and vias, and micropin-fin heat sinks were fabricated and flip-chip bonded on a silicon interposer. Micro pin fins are etched into the back side of the chip and TSV created in the pin fins to connect to the next level.

Compared to chips that are air cooled, the micro fluidic module shows significantly cooler operation (i.e. 98 C max vs 64 C max).

Stay tuned because working with Altera, they are creating such cooling channels in the backside of a live FPGA.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

GaTech Global Interposer Conference

The 4^th Annual Global Interposer Technology Workshop At GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon. Some of the panel discussions I have seen discussing the pros and cons of various interposer alternatives have been at this meeting due to the broad technical scope of its attendees.

Joining Rao Tummala as co-chairs were Matt Nowak of Qualcomm and Subu Iyer of IBM.

Yole

Representing Yole Developpement I presented an update on 2.5/3D focusing on thee new 3D memory architectures which have been needed for silicon interposers to really take off.

The audience was also forced to endure my lecture on packaging nomenclature which is getting completely out of hand.

Leadframes, BGA substrates and pieces of silicon with high density wiring and TSV are all interposers. The term 2.5D was a joke and the term 2.1D or others such as 5.5D similarly are jokes with no technical meaning. What the laminate community is beginning to call 2.1D is simply a higher density BGA substrate.

IBM

IBM’s Subu Iyer, an IBM Fellow, IEEE Fellow and front end practitioner for many decades has been a long time supporter of this Global Interposer Conference.

Always one to speak his mind Subu was blunt and to the point on two key issues during the panel session at this conference; (a) interposer definitions and (b) the presumed interposer cost structure.

He agreed that 2.1, 2.5D etc. has no real meaning and is only confusing non packaging practitioners. Here is the now infamous exchange with Rao Tummala [link]

Subu: “I find the whole concept of 2.5D fairly atrocious. I have banned its use [in IBM].”
Rao: “what are you going to call it?”
Subu: “Interposers, like God intended it to be.”

While nomenclature is important to keep concepts straight, even more important was the discussion on the relative costs of silicon vs glass vs laminate interposers. Subu’s point was:

“…high density interposers will all cost the same whether glass or laminate or silicon…the cost is not materials dependent but rather density dependent”

This is a point  that I have been trying to make myself for a few years now on IFTLE since the concept of the glass interposer became all the rage. As Subu said, interposer costs will all be approximately the same if the densities are equal and the equipment sets are the same.  In the chemical industry, from whence I came, the rule of thumb was that raw materials were responsible for approx. 10% of the total cost.

The key is NOT that glass is a low cost material, but rather whether one can manufacture fine features on large glass panels . Panel size and equipment set cost and throughput (yielded) will determine the cost of glass interposers not (I repeat) not the fact that window pane is cheaper than a silicon wafer.

Low cost equipment to create high density features on  large panel substrates (which obviously won’t be silicon)  IS a worthy goal for both glass and laminate providers,  lets just not loose track of what the key factors are. PANEL SIZE…EQUIPMENT SET COST…THROUGHPUT

In fact, a t the 2011 GaTech Global Interposer Conference Yole Developpement predicted that panel lines would be required for 2.5D interposers to attain a low enough cost to be widely adopted in the chip packaging community [link]

GaTech Glass Panel Consortium

At the IEEE Global Interposer Technology workshop in Nov Rao Tummala announced the formation of a “Panel based Global Glass industry Consortium” for “low cost, ultra miniaturization, high performance and Si like ultra high IO interconnections to address both small and ultra small system needs such as smartphones, wearables, IoTs and medical systems.”

Tummala continued “ we started looking at glass in 2010….today we have 50 global companies involved…GaTech can now access the complete ecosystem to develop and apply this technology to single chips, with lower cost than todays packages, multi chip in 2.5D architecture, similar in IO pitch to todays Si interposers but at much lower cost and ultimately to 3D system architectures”

GaTech continued that they “are producing advanced 2D, 2.5D and 3D system packages in its 300mm panel facility and looks forward to transferring the technology to 510mm panel fabs.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

TMV vs PMV

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared below.

Samsung EM describes the driving force for this new technology as the added adhesion that they get by replacing the solder TMV fill with copper in the PMV.

Seeking input from Glenn Rinne of Amkor, IFTLE found out that Amkor has run both processes and seen that the laser formed vias have both cavities and protrusions in the via walls due to the filler in the mold compound. The cavities serve as a “roughness” which anchors the solder fill and the filler particles protruding into the vias actually shadow the deposition of seed layer when copper is plated into the holes so they concluded that the solder, which is “conductive enough” actually shows better adhesion and is a cheaper process.

TSMC Continues move into packaging

TSMC is purchasing a plant in Longtan, Taiwan from Qualcomm for $85MM and turning it into a facility devoted to the development of the advanced integrated fan-out wafer-level packaging (InFO-WLP) technology. TSMC could initiate manufacturing as early as 2016 on 16nm chips, but HVM date will depend on “customer demand” [link]

TSMC and Samsung battle for Apple and Qualcomm Orders

It is reported that both Apple and Qualcomm will likely buy a larger proportion of 14 nanometer smartphone chips from Samsung rather than TSMC beginning in the second half of 2015 [link].

Given that Samsung has more advanced manufacturing technology to produce fin field-effect transistor, the company is reportedly more likely to win Apple’s contract for A9 processor production, said research institute Bernstein Research.

The Commercial Times reports that Qualcomm has already started working with Samsung to develop the chips. The Economic Daily News adds that Qualcomm has already placed orders with Samsung.

3D Memory Stacks Finally Arrive

For those of you struggling with all the new memory architectures that have been announced, I recommend the recent article by Yole Developpement which details announcements by Hynix, Samsung, Micron and Tezzaron [link]. With the recent Samsung announcement of mass production of 64 GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have now announced the commercialization of TSV based memory architectures.

Different applications will have different requirements in terms of bandwidth, power consumption, and footprint. As we move into 2015 several industry segments have announced applications using the new memory stacks. Intel recently announced that their Xenon Phi processor “Knights Landing,” which will debut in 2015 will use 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth for high performance computing applications.  AMD and Nvidia have also announced the use of HBM in their next generation graphics modules like the Nvidia Pascal due out in 2016.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

Continuing our look at the 2014 IMAPS Conference held in San Diego…

K&S

Colosimo of K&S examined high productivity Thermo-compression FC bonding. In traditional FC assembly, the chips are tacked down to the substrate and then solder joints are melted and mass reflowed in an oven. Mass reflow (MR) becomes more difficult as the pitch of the solder bumps becomes finer due to control of solder flow and warpage of the package when the die and substrate are heated and cooled together. These issues are exacerbated for thin die and die stacks. Thermo compression (TC) was developed to locally heat the solder without subjecting the entire substrate to the heating and cooling cycle.  This requires the bond head heat past the MP of the solder and then cool down to a low enough temp to pick up the next die from the wafer mounted to tape. Current tools today can do this in 7 to 15 seconds (a few hundred units/hr) which is substantially slower than todays standard FC process.

The newly developed K&S TC  tool reportedly can process 1000-2000 chips/hr.

Shinko

Shinko detailed their studies on 3D stacking an SoC die and a memory die in a SiP package.  The fig below shows X-sectional image of the 3D Sip. The structure has a bottom die (6mm sq) with TSVs, stacked on an organic substrate and a top die (9mm sq) stacked on the back side TSV of the bottom die. The bottom die has 10um TSV on 40um pitch.

MEOL (mid end of line) processing flow is shown below. The bottom wafer with copper pillar bumps on its front side and blind TSV is attached to a carrier and thinned to expose the TSV and passivated. The carrier is debonded and the die are sawn for assembly.

The figure below shows the die stacking and packaging flow. The bottom die with copper pillar bumps is assembled onto the BGA substrate. Next the microbumps on the top die are bonded to the TSV pads of the bottom die. The finished assembly is encapsulated and solder balls are attached to he BGA package.

BLR (board level reliability) comprising Temp cycling ad drop testing is shown in the following table. Weibull plot of temp cycling shows first failure at 2,344 cycles and 0.1% failure at 1194 cycles.

Samsung EM

Samsung Electromechanics examined the fabrication of Fine featured organic interposers. The next gen packaging such as wide IO memory – logic packaging (JEDEC requires min bump pitch of 40um) requires connection on less than 50um pitch. The Samsung EM process flow using photoimageable build up layers reportedly is capable of less than 5/5 L/S with micro-vias on 50um pitch. The layers can be connected with Vias with min 10um dia.

Univ. Texas

Paul Ho’s group at U Texas has examined the impact of copper grain structure and material properties on via extrusion in 3D interconnects.

The copper vias they examined were 5.5 x 55um in 780um thick Si. In sample A the copper grain size was uniform. In sample B the copper grains were a mixture of large and small grains. The average elastic modulus for A TSV were 117 MPa and for B 93 MPa. TSV extrusion was found to be 117nm for A and 147nm for B. The smaller more uniform grains were found to exhibit higher yield strength and therefore less via extrusion. Stronger Cu/Si interfaces are also shown to achieve less via extrusion.

GaTech Mechanical Eng

Charles Ume of GaTech reported on his studies detailing the effect of bump pitch, package size, Mold compound and substrate thickness on PBGA warpage.

FEA studies reveal that solder bump pitch, package size and mold compound thickness affect he maximum PBGA thickness significantly, but substrate thickness does not.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2014 IMAPS Conference held in San Diego…

Corning

Shorey of Corning Glass gave an update on glass panel fabrication. He noted that “there are challenges in applying standard plating processes to glass,” but Autotech has recently reported significant progress in the ability to metallize glass vias using new adhesion promoters. They show complete fill with little overburden in 80um holes in 300um glass.

They also showed 370 x 470 x 0.3mm glass panels. A Rudolph Jetstep S3500 was used to create “~3um L/S…with additional work we fully expect to be able to resolve < 3um L/S”.  Smallest vias shown were 35um in 100um glass.

Rudolph Technologies

In an aligned presentation, Ruhmer of Rudolph discussed high resolution patterning to enable panel based advanced packaging.

When examining litho steps for panel processing Rudolph points to the following key items: minimum resolution, overlay accuracy, sidewall angle and CD control, depth of focus (DoF), exposure field size and warped panel handling capability.

– optical characteristics of suitable litho systems should offer N/A of 0.1 to 0.15 in order to meet L/S resolution requirements for high density interposers (1-2um)

– depending on the complexity of the interposer 5 or more mask layers per side can be required. In general the overlay accuracy should be ~ 1/3 the resolution limit of the system, so for a resolution of 1.5um the overlay accuracy should be 0.5um. Reconstituted substrates for FO-WLP is more complex due to die shift.

– accurate focus control across the wafer is required for tight CD control and consistent sidewall angle in photo dielectrics

– depth of focus for back end processing requires 10um or greater range, not typically available in front end steppers.

– exposure field size should at least cover one die to avoid stiching.

– in initial panel based FO-WLP testing warpage of approx 10mm was observed for a Gen 2 glass panel. Equipment with  warped handling features like switchable and compliant gaskets on chucks and handlers ae needed for litho and other processing steps.

Corning / Unimicron / Qualcomm

Corning, Unimicron and Qualcomm reported on their low cost interposer development program.

They sought to show feasibility of interposer manufacturing on their 200um thick 508 x 508mm glass panel format. Daisy chains are connected with 100um TGV (through glass vias) and 8/8 L/S.

The process flow using ABF dielectric is shown below.

Early handling led to glass breakage. The ABF lamination (Ajinomoto) gave the thin glass panel mechanical support more handlable.  Then vias were created through the ABF.

Warpage of the glass panels were compared to laminate (BT) panels of the same size with 200um core thickness. The glass panels showed 3X lass warpage.

DNP

DNP reported on a comparison of fabrication processes and electrical performance of silicon and glass interposers. I should note that these appear to be DNP processes, not necessarily standard processes. For instance they comment that silicon is fabricated on 200mm lines but glass can be fabricated on large panel lines. The facts actually are that Si is fabricated commercially on 300mm lines and large panel glass interposers are in R&D stage.

Their silicon and glass processes ae compared below.

In the silicon process, the holes are formed by ICP-RIE. The wafer is then thermally oxidized and coated with PECVD SiN. The holes are seed sputtered then plated with Cu, CMP’ed and both sides covered with Cu/PI RDL. TSV are on 200um pitch.

In the glass process, 50um TSV on 200um pitch are formed in 0.3mm glass by focused electrical discharge (Recall AGC is a proponent of this method). After Ti/Cu seed the vias a electroplated with copper and the surfaces CMP’ed. Copper / PI RDL are added to both sides.

Glass interposers showed better high freq. performance than silicon as was expected.

Shinko

Mori of Shinko described their development of Glass Interposers with fine pitch ubumps and their warpage results. They examined glasses with CTE’s of 3.2 and 9.5 ppm and corresponding moduli of 73 and 90 GPa. Their design rules are shown below.

Three laminates were examined with properties shown in the table below:

Warpage of the die on interposer on substrate showed that warpage of the assembled stack is lowered with lower CTE laminate substrate but is not affected by the CTE of the glass Interposer. Modeling verified these results.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

3D ASIP

It’s that time of year again to be thinking about registering for the RTI sponsored 3D ASIP (Architectures for Semiconductor Integration & Pkging) which will be held at the Burlingame Hyatt on Dec 10-12 [link].

RTI ASIP has been focused on 3DIC and 2.5D for 11 years now. As we are now finally seeing  commercial commitment from the memory suppliers and the graphics module manufacturers hopefully we are observing 2.5/3DIC  finally taking off. Unlike other, more academic conferences, RTI ASIP has always been focused on the commercial and business aspects of bringing 3DIC to the market place.

This years program includes two special pre-conference symposia . A  ½ day symposia 2.5/3D IC design tools and flows led by Herb Reiter will include speakers from Cadence, Mentor, Apache design, GF, Rambus and Qualcomm. There will also be a half day tutorial on the current state of the art in 2.5/3D processing led by yours truly with “drill and fill” covered by Dean Malta of RTI; Temp bond and via reveal presented by Severine Cheramy of Leti and assembly presented by Laura Mirkarimi of Invensas.    As a special bonus, those attending the processing tutorial will receive a free copy of “The Handbook of 3D Integration Volume 3: 3D Process Technology” edited by Garrou, Koyanagi and Ramm.

The regular conference includes presentations by Micron, Xilinx, Nvidia, GF, Synopsys, Nanium, Unimicron ad many more . Of special interest should be the updates on their DARPA ICECool  3D cooling programs by Bakkir of GaTech and Gaynes of IBM Watson and the IoT (Internet of things) presentations by Beica of Yole and Schulz of the silicon integration initiative.

Hope to see you there.

Amkor – Extending Mass Reflow to Finer Pitch Copper Pillar Bumping

Another key paper from the recent 2014 IMAPS Conference in San Diego was by Fernando Roa of  Amkor concerned with extending the current processing envelope for Copper pillar bumping using mass reflow (MR).

Thermo compression (TC) is typically applied for copper pillar bumping. In general, it is a slower more expensive assembly process since each die has to be positioned and mated before moving on to the next die. A bonding head is typically used to hold the die flat and in alignment with the substrate while heat is applied to complete the connection. In general MR throughput is 2X that of MR.

In contrast, MR bonding places the die and then reflows them all at once.  Std FC attach and capillary underfill is shown below vs thermo-compression (TC) bonding.  TC typically underfills with non conductive paste (NCP) or film since capillary underfills are more difficult to use with copper pillar bumps because of their fine pitch.

Amkor typically uses the MR process flow for copper pillar bump (CPB) from 200 to 100um pitches with minimum changes to the standard process flow.

For fine bump pitch (b), since the bumps are much closer together there is less room to create solder mask defined pads as show below. Since the bump diameter is close to the typical width of the trace they are allowed to form connection directly on the trace.

While typical MR assembly relies on solder self alignment during reflow, MR of solder to trace is more difficult since self alignment to solder catch pads is not possible. In MR of fine pitch bumps the solder wraps around the trace in contrast to TC joints that typically show solder squeezing out of the joints because of the compression.

Very precise selection and control of die thickness, substrate construction and substrate finish is necessary to reduce or eliminate solder shorts and non wets. Roa indicates that Amkor efforts are underway to extend MR to finer pitch bumping activities.

By Dr. Phil Garrou, Contributing Editor

Rumors on the SCP Acquisition

We have discussed the Acquisition of STATSChipPAC (SCP) in recent blogs [see IFTLE 195,  “STATS in play….” and IFTLE 198, “….STATSChipPAC suitors named…”.] In late August, Bloomberg News reported that Jiangsu Changjiang Electronics (JCET) and Tianshui Huatian Technology were working on offers for SCP [link].

IFTLE continues to hear rumors from multiple credible sources that the deal with JCET is imminent and that final price is being negotiated. While denials are being floated by JCET, we all recall that similar denials were also rampant in the recent IBM / GF deal till the last minute.

IFTLE is also hearing that during these negotiations SCP, like IBM, is loosing key personnel throughout the organization. But, whereas IBM personnel movement was to ultimate acquirer GF, not so for SCP and JCET. Rumors from SCP indicate that JCET will not be retaining any key Singapore management in an effort to lower their cost position. As JCET waits to lower the ultimate acquisition price, IFTLE believes they are also lowering the overall value of SCP. A company is its people!  There are also unsubstantiated rumors of customers leaving SCP because of this chaos.

While it may be 2015 before the deal is consummated, IFTLE can see SCP falling from the #4 OSAT position and is probably already behind PTI.

Will SLIT replace TSV?

At the recent IMAPS meeting in San Diego Xilinx and SPIL presented the paper “Cost effective, high performance 28nm FPGA with new disruptive Silicon-less Interconnect Technology (SLIT).

In the traditional Xilinx silicon based FPGA module the FPGA die with microbup interconnect are connected to the 4 layers of 65nm interconenct on the silicon inerposer which then has TSV and c4 bumps to connect power/grd and other incoming sgnals.

In the new SLIT technology the same FPGA slices are mated to 65nm intrconenct on silicon but no TSV are required since ther is selective Si removal and backside contact formation along with required inline wafer warpage control. The structure is EXPECTED to give lower cost while delivering better electrical performance. The structures are compared below.

TSV “drilling and filling” are eliminated as are thin wafer handling, backside reveaand many inspect and metrology steps.

(a) traditional Xilinx FPGA with silicon Interposer; (b) FPGA without interposer

(C) SLIT in X-section

The 65nm interconnect are created on std bulk silicon The bottom most dielectric layer is selected to have high selectivity during subsequent backside etch. The top of the metallization interconnect layer is capped in 45um pitch pads and microbumps.

The FPGA die are  thinned diced and stacked onto the interconnect wafer. After reflow the ubump gap is underfilled and overmolded and the mold cmpd is ground down to expose the die top surface.

Subsequent wafer thinning is done to the dielectric etch stop layer.  Contact holes re etched in the dielectric and pads and balls are created/placed.

The main processing issue is wafer warpage, especially after the full silicon removal. Stresses are balanced with a reinforcement layer and other stress controls during the processing.

This is certainly a very interesting proposed structure and IFTLE will be keeping an eye on SLIT processing.

More from IMAPS in subsequent blogs

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Nanium

Most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers.

NANIUM also has extensive volume manufacturing experience in WB  multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

In 2012 Nanium licensed the 300mm FC bumping and Spheron fan-in WLCSP technologies from Flip Chip International (FCI) [link]. After completing line setup and qualification for that technology, the company added the capability to manufacture fan-in WLP product.

Today, they call themselves a “Wafer Level Packaging solution provider” as more than 90% of their business is now WLP.

In May we discussed Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” that proposed eWLB as an alternative to 2.5D silicon with sufficient capability for many applications in high volume at reasonable cost.  [ see IFTLE 194, “…… SEMI Singapore part 3: Nanium, Fujitsu, EVG”]

NANIUM has now announced commercialization of a 29nm, 25mm x 23mm (about the maximum reticle size allowed),  fan-in WLCSP  on 300mm wafers for customer  Custom Silicon Solutions (CSS).

CSS reports that such large dies are usually packaged in WB-BGA or FC-BGA with underfill material between bumped die and FC substrate for board-level reliability.

Naniums WLCSP has 1,188 solder balls on a  0.7mm BGA pitch. It has successfully passed more than 400 temperature cycles on board (-25 – +100 C). Die are 475um thick.

IFTLE Agrees that WLCSP technology has traditionally been limited to chips less than 7mm and the packaging community has been looking for technologies to allow the manufacture of greater than 10mm WLCSP.

ITLE has contacted Nanium for further “insight” and learned that they use 380um BGA solder balls that collapse to 300um stand off height after reflow. Reliability testing of the large WLCSP are done without underfill and do not have a polymer collar or similar technology improving their reliability. PBO based devices pass 400 cycles and PI based devices pass 600 cycles. Nanium does note that the customer is underfilling when assembling to the board “to be on the safe side.”

When asked directly what they key technology breakthrough was/is Naniums’s Steffen Kroehnert responded, “There really in not one big thing…there are a lot of small things…material dielectric choice makes a big difference…design features such as trace and pad design and size , copper area loading, Cu thickness, thick UBM and optimization of solder ball  alloy all contributed.”

IBM Deal Done

Every once in awhile I break with normal journalistic decorum and like a little boy in the school yard get pleasure from shouting “I told you so” (OK…maybe a little more than every once in awhile).  My little Italian grandmother (Nonna) told me not to gloat when you were right about something because no one likes such people… but it’s hard to resist. [For my non US readers, gloating is “…dwelling on one’s correctness with smugness.”]

IFTLE came to the conclusion that IBM would sell off their semiconductor business several years ago when it became clear that future node fabs would cost far more to construct  ( $4-6B) than the IBM semi business was making on a yearly basis (~ $1B). These simple economics would eventually prevail. As they pulled so called “IBM friends and family” around them in NY a few years ago, it became clear that they were positioning to have one of these “friends” buy the business and become their supplier. It has been clear for more than a year that Global Foundries was the logical choice.

Some were shocked when rumors leaked that IBM was having to sweeten the pot with significant cash in order to get GF to take over their money loosing semiconductor operation. But, as I have explained previously, that’s what is required when  you take over a business that’s loosing ~ $2B / yr . What Global gets out of this deal is not the manufacturing capability or the customer list, but rather the people and the IP. Once they restructure I see this as a good deal for GF and for IBM employees who obviously were no longer required by their now ex employer.

IBM has now officially announced the deal with Globalfoundries [link].  IBM will pay GF $1.5B to take over their chip manufacturing operations, which will continue to produce processors used in IBM systems.

Recently reported revenues from IBM’s Systems and Technology segment, which includes the company’s computers, declined 14%. The company’s other hardware segment–the Power systems, based on IBM-designed computer chips, fell 12%.

Cu WB at TI

TI began shipping copper WB, which delivers a 40% increase in conductivity, in its products in 2008.  Today, all of TI’s assembly sites are running copper WB on all TI package types, including BGA, QFN, QFP, TSSOP, SOIC, PDIP and others.  Copper is currently 71 percent of TI’s total WB usage. Existing analog and CMOS silicon technology nodes have been qualified with copper WB, and all new TI technologies and packages are being developed with copper WB.

TI is currently shipping about two billion units of copper wire bond technology each quarter.  TI has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

It’s been awhile since we looked at what is new on the dielectric market so we checked with a number of dielectric suppliers and asked what was new in their product lines.

Dow Chemical

The old Rohm & Haas organization has been running the Dow Electronics Materials business for a while now, basically since they were acquired by Dow. I knew they would do well when I observed them make the ill advised low-K SILK product quietly go away.

They certainly have beefed things up in the BCB product line as follows.

• Toughened BCB has been developed with 3X the elongation at some expense to CTE
• A Dry film grade is being developed with thicknesses up to 100um
• A positive-tone, aqueous developable product, BCB, 6505 is fully commercialized
•  A BCB based temp bond adhesive, XP-130215,  for wafer thinning and 3D stacking is being sampled

I have compared the properties of a few of these new products to standard photo BCB 4000 below.

The PI community has not been standing still either. PIs always known for their high temp stability and their superior mechanical properties has had some catching up to do when it came to curing temperature amongst other properties.

HD Micro offers the following product lines.

C-4 flip chip RDL layers:

–        HD 4100 negative tone photo PI

–        HD8800 positive tone photo PBO

–        HD 8900 positive tone low cure temp photo PBO

2.5/3D Adhesives:

–        HD 3000 non photo temp adhesive

–        HD 7000 photo PI permanent adhesive

Stress Relief and Passivation Layers:

–        PI 2545 non photo wet etch PI

–        HD 8800 positive tone photo PBO

–        HD 8900 positive tone photo PBO low cure temp

Properties of these materials are compared below:

Zeon

Zeon is introducing the new positive tone photo “olefin based” Zeocoat  CP 3010 designed to deliver a low cure temp, low stress coating. Below are the properties of the polymer determined after a 180 C cure.

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

There is an old proverb that states “All things Come to Those Who Wait.” It is exemplified by the French cartoon (below) showing a cat patiently waiting for a mouse to exit his hole in the wall. I personally am not the waiting type wanting to get things done ASAP but most civilizations look at patience as a virtue.

We’ve discussed the leading edge before. The leading edge is where the money is made. So while you don’t want to be too early, you certainly don’t want to sit back and wait to see if something is going to happen and let others drain all the profit from that early period of introduction.

Now having said that, let me counter by saying that “All things don’t come to those who wait”. I waited for thin film  MCMs to take off in the 90’s and early 2000’s and they never did.  A lot of us gambled and in that case – lost. Life is a gamble !

TSV technology and 2.5/3D has had its own  dichotomy. We couldn’t sit back and allow others to get there first so we all anteed up our time and money without any assurance that there is big money to be made on this technology. Like the cat, we have been waiting (some more patiently than others) for 2.5/3D to enter HVM when in fact there has been no assurance that the mouse wasn’t going to exit from another wall (i.e another technological solution as happened in thin film MCMs).

Anyone who understood what TSV technology could bring to the party, knew that HVM and actually new product design itself could not expand until foundry technology was available (since TSV were/are clearly going in during chip fabrication) and memory stacks were available, since foundries don’t make DRAM. Of course it all has to be at the right price, but if its not even available, what matters the price?

In terms of foundries TSMC [see: IFTLE 122, “TSMC officially ready for 2.5D….”, ] was the first to announce and GlobalFoundries is not far behind [see; IFTLE 142,  “GlobalFoundries 2.5 / 3D at 20nm…” or IFTLE 164, “Semicon Taiwan contd: GlobalFoundries Manocha Interview”  ] so those at the leading edge can now design in 2.5D. But what about memory ??

While UMC [see: IFTLE 135, “UMC / SCP Memory on Logic…” and a few others have made noise about entering the 3D market space they appear to be significantly further behind.

The status of memory

Memory, as IFTLE has noted several times, has been slower coming.

The DRAM industry has been undergoing significant consolidation in the last few decades. The recent acquisition of Elpida by Micron has left 3 major players in the DRAM business as shown below.

DRAM Mkt Share of the Big 3 [Source: Gartner 2014]

Moving forward the main roadmaps for DRAM suppliers all address: (1) reduce power consumption, (2) satisfy bandwidth requirements and (3) satisfy density requirements , all while maintaining low cost.

With DDR architecture running into a brick wall the memory suppliers have been focusing on new architectures that will deliver lower power, higher bandwith memory solutions.  These include wide IO-2, HBM (high bandwidth memory) and HMC (hybrid memory cube).

Definition, standardization and scale up of these memory technologies has simply taken longer than any of us would have liked, but these are the new architectures what will take advantage of TSV stacking technology.

TSMC has recently compared the different memory architectures relative to DDR and one another  in terms of bandwidth vs power and price.

Memory Architectures vs bandwidth, power and price. [TSMC]

Comparison of New Memory Architectures

As we head into the fall of 2014 the last probably most important of the big 3 memory suppliers, Samsung,  has now announced production of TSV based memory stacks [see: IFTLE 209, “Samsung announces TSV based DDR4 ….” ].

So we are about to have HBM for graphics modules, wide IO-2 for mobile products and HMC for HPC and high end servers. Now there can be no more excuses.

Within the next 18 months, if we do not see product introductions announced,  2.5/3D will begin to fade away until it is only remembered as another one of the bad bets we made attempting to stay on the leading edge…

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…