By Dr. Phil Garrou, Contributing Editor

Let’s take a look at Samsung’s System LSI activities per their recent Investor program. ICs and applications that were highlighted are shown below.

Chronological advances in the Exnos microprocessor which are now being manufactured at 10nm are shown below.

Samsung has maintained a position as supplier of mobile processors, image sensors and display driver ICs. Looking into the future Samsung sees the main application drivers as:

Samsung System LSI is a provider of integrated total solution for mobile. They feel that innovations in semiconductor technologies will be the key driver in various new applications that adopts AI/Deep Learning, 5G networking, and smart mobility. Samsung LSI is now on the path to be a key player for 5G and autonomous mobility, and is investing for future device intelligence.

This will require a lot of advanced packaging!

For all the latest in advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Sony had some interesting things to say about their semiconductor and imaging technology businesses at their recent investor relations day May 22^nd in Tokyo. As the industry moves forward to 5G, they seek to provide both hardware solutions and content services. Probably most startling to those in attendance appeared to be their announcement of a major focus on their mobile smartphone business.

Shigeki Ishizuka, Exec VP of Imaging products and mobile communications business discussed their theme of “light to display” as shown below. Imaging products and solutions is currently a 660B Yen business for Sony.

Their key applications for real time broadcasting include not only sporting events and concerts but also business to business communications, the education market which they call “active learning solutions” and medical room imaging solutions.

The medical business is described below and consists of both surgical imaging and life sciences.

Their newly developed 3D surgical microscope allows doctors to operate without looking into the eye lenses of the microscope and the image can be shared real time with the whole operating team.

In the mobile communications segment Sony smartphone (Xperia) unit sales have decreasing since 2014 (see below). They will now focus on 5G phone solutions to revive their business position in that segment.

They will be seeking to advance smartphone competitiveness vs the industry leaders by bringing all their internal technology and their external partnerships to bear. They expressed a need to especially improve the design.

Post presentations, most of the questions focused on this announcement of increased focus on the mobile segment. When questioned about whether 5G mobile was an area that they HAD to be in, Sony answered that the technology hurdle for 5G is “quite high” including antenna technology “…. multi antenna array for beam focusing and switching has never happened before….high technology solutions are needed…its not like you can purchase an LSI chip and write some software and develop a solution…we will have to acquire these solutions and mature them” IFTLE assumes this answer was meant to mean that this is not likely to be a commodity product and would require the technical expertise that only companies of Sony’s stature could deliver.

When asked whether it was logical to focus on smartphones where Sony now has less than 1% market share they answered that “…with respect to smartphones the share is low-right- that’s a pity…we don’t have much product offering and product capability is very low….” The rest of the answer did not clearly explain how they intended to turn this around other than they awould be focusing all their internal technical expertise on solving this problem.

It will be interesting to see if Sony can really become competitive with the likes of Samsung and Apple in the future 5G arena.

For all the latest in advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

At the recent IMAPS Device Packaging Conference outside Phoenix Hamid Eslampour, CMOS BU Product Management, of GlobalFoundries (GF) discussed Advanced Packaging in the Foundry Space.

Eslampour indicated that todays networking, machine learning, and other high-end computing applications have created the need for architectures that allow for processing of massive amount of data located in nearby memory through communication with the CPU/ GPU with low latency, parallel processing, and high data rate.

To enable these solutions, advanced Si nodes with High-Speed-SERDES (HSS), enhanced HBM-PHY, and highly integrated package technologies are required. The packaging solutions they see providing the level of integration required include MCM, 2.5D, and 3D.

The challenge for foundries such as GF is to enable these solutions through co-design with the customer within a business model that provides the package design, technology integration, and OSAT manufacturing processes required.

High bandwidth and high performance computing technologies for silicon and packaging are shown below. Such high performance devices will require < 40um pitch copper pillar bumping and fine line interconnect (< 10/10 L/S).

14nm designs are in customer development with 7nm and beyond designs in pathfinding.

Current GF interposer capabilities are shown below and include 10um TSV on 40um pitch, up to 3 metal layers of 0.8um L/S interconnect:

GF has the following supply chain in place:

Higher bandwidth trends drive higher number of HBM stacks, larger silicon interposers and larger power dissipation issues.

For all the latest on Advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

China is by far the largest consumer of semiconductors reportedly accounting for 45 percent of the worldwide demand for chips, used both in China and for exports. More than 90 percent of its consumption relies on imported ICs.

At the end of 2016 IC Insights reported that China was responsible for ~ 11% of the worlds wafer capacity.

China has been working to reduce its dependence on technology imports, including computer chips for several years. In March, it was reported that state-backed China Integrated Circuit Industry Investment Fund Co. is in talks with government agencies to raise at least $24B to build up China’s domestic semiconductor industry. Recently, the Wall Street Journal reported that China is poised to announce a new fund of ~ $47B for development of its semiconductor industry and close the technology gap with the U.S. and other rivals.[link]

While the existence of such a fund has been rumored for months, the size of the fund has been hard to pin down. A few weeks ago, Reuters reported that the fund would be $19B, while Bloomberg reported $31.5B two months ago. The exact number appears to be under consideration among the Chinese leadership, and tied to the increasingly tense trade negotiations with the United States. If $47B is indeed the correct number, it would be identical in size to the $47 billion fund that was financed by Tsinghua University, to spur the development of an indigenous semiconductor industry back in 2015.

While China is playing catchup in many semiconductor areas, it has also been placing its bets on new areas like 5G wireless and AI (artificial intelligence) chips. [link].

China releases its first cloud AI chip

Beijing artificial intelligence (AI) chip maker Cambricon Technologies Corp Ltd has just announced two new products, a cloud-based smart chip Cambricon MLU100 and a new version of its AI processor, Cambricon 1M, in Shanghai on May 3^rd.

The cloud chip MLU100, developed by China’s Cambricon Technology, is China’s first cloud artificial intelligence (AI) chip developed to have big data processing ability, for image and voice searching [link].

Cambricon 1M is the company’s third generation AI chip (gen 1 was in 2015) for “edge devices.” An edge device is a device which provides an entry point into enterprise or service provider networks such as routers, routing switches, integrated access devices (IADs), multiplexers, and WAN (wide area network) access devices. Using TSMC 7nm technology, the AI chip can be used in smartphones, smart speakers, cameras, and smart driving.

Cambricon MLU100 supports cloud-based machine learning, including vision, audio and natural language processing. It can process under complex scenarios, such as “…with huge amounts of data, multi-tasks, multi-modality and low latency.” This processor reportedly can provide 166 TFLOPS in high-performance mode with energy consumption of no more than 110 watts at peak. The MLU100 is built with TSMC 16nm technology.

Lenovo has announced that their ThinkSystem SR650 server is based on the MLU100. Products built around MLU100 were also announced by Sugon and iFlytek who also announced collaboration with Cambricon [link]

For all the latest on Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

TSMC Introduces WoW Technology

At the TSMC Technology Symposium in Santa Clara, the company discussed their new Wafer-on-Wafer (WOW) silicon wafer stacking technology for the 7 and 5nm nodes. The “new” technology connects chips on two silicon wafers reportedly using 10um TSV. Those of us who have been following 3DIC for over a decade recognize this as W2W 3DIC. Even the name isn’t new, since Fujitsu introduced their version of WoW technology in 2010 which we discussed way back in in IFTLE 181.

TSMC first teased us with this potential technology back in 2014 at the IEEE IEDM.

The TSMC technology stacks and interconnects die while still part of the full silicon wafers vs their previous 2.5D technology CoWoS that uses silicon interposers. The advantage is obviously that this tech connects all die on two wafers in one process step. In terms of performance, direct 3D stacking has always been known as the highest performance lowest latency solution.
As we have known for a decade at least, there are several issues with W2W technology: (1) yield – bad die on wafer 1 will be connected to good die on wafer 2 resulting in a bad stack. This precludes this technology from being a viable solution for silicon that doesn’t already offer high wafer yields. Ideally, TSMC reports that chip yields should be 90% or higher to use TSMC’s Wafer-on-Wafer technology. (2) quite obviously this technology is most relevant for low-power silicon, where heat is less of an issue and (3) Also importantly, readers of IFTLE know that this solution works best for chips that are identical like memory stacking, but not for ships of different sizes and different I/O configurations which would require redistribution (RDL) before alignment and stacking is possible, thus increasing cost.

So far, TSMC has reportedly achieved “2-layer stacks, in which two silicon layers that are mirror images of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.”

Since TSMC currently manufactures graphics cards for both AMD and Nvidia and there are some predicting that we will see stacked GPUs from the WoW technology. “There won’t be latency problems between the connected GPUs as the wafer has the ability to let the GPUs communicate quickly, meaning we could see dual-GPU graphics cards based on current GPUs like the Polaris and Pascal GPUs from AMD and NVIDIA, respectively.” [link]

Certainly they wouldn’t be hyping the technology if there weren’t real customers urging them to move forward with it. It will be interesting to see if they give a more complete description of WoW at the IEEE ECTC in a few weeks. If so be sure that IFTLE will get you the details.

What about designing these complicated structures ??

Cadence Teams with TSMC for full WoW Design Flow

Cadence has announced that its full suite of Cadence digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology. [link]

Cadence announced a new WoW reference flow to complement their other TSMC integration solutions ( InFO and CoWoS). They described the following design flows, tools and methodologies that will enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process as follows:

• Innovus™ Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
• Quantus™ Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
• Voltus™ IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
• Tempus™ Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
• Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
• Virtuoso^® Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
• OrbitIO™ interconnect designer: Provides interface connectivity,  device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
• Sigrity™ PowerSI^® 3D-EM Extraction Option: Offers electrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
• Sigrity PowerDC™ technology: Thermal analysis solution with interposer and die analysis capabilities that allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
• Sigrity XcitePI™ Extraction:  Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
• Sigrity SystemSI™ technology: Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation

For all the latest on Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a look at the latest Yole update on Fan out Packaging by Jerome Azemar that was presented at the IMAPS 2018 Device Packaging Conference.

As we have discussed before, fan out packaging can be embedded in laminate or embedded in mold cmpd (EMC) . Chips can be placed face up or down with various options for interconnections.

Their look inside a smartphone gives an interesting perspective on where fan out packages are being used and where they can be used.

Yole sees automotive radars as an interesting market for fan out solutions

– fan out used in Rf and radar applications

– since 2015 Infineon has shipped > 10MM Radar IC in eWLB packages

Yole reports that technical challenges still exist for fan out as shown below:

They see high density fan out (like TSMCs InFO) fan out being in competition in the future for HPC (high performance computing) and AI (artificial intelligence) applications with silicon 2.5D solutions.

While panel production would certainly reduce costs (more units per operation) such technology is not ready and will have large capital equipment costs. They see production being mainly on wafer through 2022.

CMOS Image Sensor Market

IC Insights Optoelectronic, Sensor, and Discrete report concludes that the CMOS Image sensor market is not approx. the same size and growth rate as the LED business [link]. An interesting comparison…

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

IFTLE has extensively discussed the applicability of the Ziptonix technologies (acquired and now owned by Xperi): ZiBond (oxide-oxide bonding) and DBI (copper-oxide to copper-oxide “hybrid bonding”) [for example see IFTLE 303, “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7” and refs therein]

These technologies have now been commercialized in areas such as COS image sensors, Rf and MEMS. These are all wafer to wafer bonding applications. As of yet, a die-to-wafer process has not been developed for manufacturing, imposing W2W limitations such as the requirement that die sizes match and yields are high.

At the recent IMAPS Device Pkging Conf in March, Wang of Xperi discussed the “Design, characterization and testing of large area and high density 3D direct bond interconnect which discussed development of such a die to wafer technology.

DBI’s key attribute is the formation of electrical interconnects at low temperatures and pressures as shown below:

The technology requires highly polished (CMP’ed) surfaces (less than 1nm deviation across wafer surface topology is typical) .

The Xperi goal was expressed as developing a process for HBM memory stacks by stacking 4 double sided DBI memory die with the following attributes:

– throughput – 3000uph                       – no underfill

– no solder                                             – stack consecutively then batch anneal

For die to wafer bonding they followed he following process sequence:

The design that was evaluated for a HBM stack contained 10um pads on 40um pitch.

D2W vs W2W electrical test for their test vehicle is shown below:

Die to wafer reliability for a 31K daisy chain are shown below:

It will be interesting to see whether this data will extrapolate to the fabrication of real HBM die stack in the future.

For all the latest in Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The March Issue of Electronic Cooling magazine contains a great summary article on the IBM effort in the DARPA ICECool Program [link]. I recommend reading the full article which I will summarize here.

When today’s standard cooling technology, air cooling with fans, does not meet the required needs, advanced water cooling approaches are examined. Traditional water cooling approaches replace the heat sink with a cold plate that provides more efficient heat transfer. But, because of its electrical conductivity, water cooling requires isolation measures to protect the chip, and requires large channels to cool large high-power die at reasonable pressure drops.

As part of the DARPA ICECool program, seeking to develop appropriate cooling technologies for 3D chip stacks, IBM developed a new chip-embedded cooling approach, utilizing a nonconductive fluid, doing away with the need for a barrier between the chip electrical signals and the fluid. This chip-embedded cooling technology pumps a heat-extracting dielectric fluid into ~100μm cooling channels, between the chips at any level of the stack. The coolant removes the heat from the chip by boiling from liquid-phase to vapor-phase. It then re-condenses, dumping the heat to the ambient environment. Since this system doesn’t need a compressor, it can operate at much lower power compared to typical refrigeration systems.

The dielectric coolant is fed in at the center of the die, moves through radially expanding channels, and exits at the edges of the die. This approach (shown below) provides better energy efficiency and maximum critical heat flux with the resulting reduced flow path.

To modify an IBM microprocessor module for embedded cooling the package lid was removed to expose the processor die, a deep reactive ion etch (DRIE) of the processor die was performed to generate the 120 µm deep cooling channels structures in the backside the processor and a glass die was bonded to the etched processor die to create the top wall of the micro-channels and a brass manifold lid, which provides for coolant supply and return, was bonded to the glass manifold die and the organic substrate using an adhesive. The coolant enters the module and passes through 24 inlet orifices to distribute the flow among the corresponding 24 radial expanding channels as shown below.

The figure below compares the performance of the standard air cooled module with the new embedded liquid cooled module. The cores temperature were measured with coolant inlet temperature in both cases at 25 ºC; a dielectric coolant mass flow rate of 9 kg/hr at a pressure drop of ~11 psi. The temp of the air-cooled processor levels off at around 70 ºC as the system fans speed up (~65%) to prevent overheating whereas the liquid cooled system is running at 40 – 45 ºC. At the highest power operation (4.3 GHz) the reduced operating temperature results in over a 10 watt decrease in the power consumed by the microprocessor along with a significant reduction in fan power (15+W) .

Apple to Replace Intel chips in Macintosh Computers

Bloomberg is reporting that Apple, which has used Intel processor chips in its computers since 1995, is planning to use its own chips in Mac computers beginning as early as 2020 (code-named Kalamata), replacing processors from Intel (link).

For all the latest on Advanced Packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

OSRAM licenses m-transfer printing from X-Celeprint

IFTLE has discussed m-transfer printing for several years, first with Semprius [ see IFTLE 203 “Apple Acquires LuxVue µ-assembly Technology” ] and then at licensee X-Celeprint [see IFTLE 354 “The Case for µLED Displays”]

We have seen Teledyne using the technology in several DARPA programs and have heard rumors of the technology being used to develop mLED displays.

It now appears that a major player in word wide LED component marketplace has significant interest in the technology because OSRAM now reports that they have entered into a technology and patent licensing agreement with X-Celeprint for their m-transfer printing technology (link)

Exactly how will OSRAM use this technology in their LED products?? We’ll be keeping an eye out and report back to our readers…

μ-transfer printing basics [link]

Starting this week we will begin going over some of the presentations at the IMAPS Device Packaging Conf held every year outside Phoenix, AZ. At one of the keynote presentations Raja Swaminathan of Intel discussed his work on the Bill Chen Heterogeneous Integration Roadmap.

If you read this blog regularly you have probably picked up on the fact that IFTLE has little tolerance for bad nomenclature and/or redundant nomenclature. So, let’s consider the term “heterogeneous Integration” what this means is basically combining (i.e integrating) things that are not the same (i.e. heterogeneous)…i.e. a DRAM memory module is not heterogeneous integration (but would be homogeneous integration) . So is this something new ?? In the 1990s we called them multichip modules. Today that is also called a SiP. Too many terms meaning nearly the same thing for my liking.

But…given that the community has appeared to latch onto this catch phrase lets look at what the roadmap committee is doing about the naming.

Swaminathan makes the point that on package integration is more compact, low power and higher band width than off package connections (see below).

In order to improve on the meaningless terms 2.5D, 2.1D etc they are proposing that we consider these as 2D enhanced architectures as side by side active silicon interconnected at high densities using either organic or silicon based interposers.

So, TSMC’s CoWoS would be 2DS with TSV, ASEs FoCoS would be 2DO chips last and Intel’s EMIB would be 2DS without TSV.

Technologies are compared I terms of density below:

Swaminathan concludes with a slide showing on of the main themes of IFTLE for the past decade “Packaging technologies will become more wafer-fab like.”

For all the latest in advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

ASE, TDK Embedded Chip Joint Venture begins

Taiwan’s ASE has initiated a joint venture with Japan’s TDK Corp to produce embedded packaging solutions in Kaohsiung Taiwan. ASE has 51% ownership in the venture which currently employs 150 people.

With initial capital of $51MM , ASE Embedded Electronics Inc has started operations manufacturing embedded substrates using TDK’s (SESUB) technology (see IFTLE 238 “ASE & the Apple watch, ASE / TDK JV…” and IFTLE 347: “ASE Embedded Packaging Solutions” )

AI vs IoT

AI and IoT both buzz words that are predicted to drive the electronics industry over the next decade. ITLE is bullish on AI, not so much on IoT. As I have explained before my opinion is formed from a packaging perspective and while I think AI will need all the latest high end packaging solutions, I still perceive that most IoT will require the absolute lowest cost, stripped down packaging available. AI platforms are an intimate combination of hardware and software but certainly will be requiring the latest that we have to offer in high end packaging solutions.

AI processing will go into home control devices, autos, surveillance systems, airplanes, wearables and things we have yet to think of. AI processing is unique in that traditional customers Amazon, Google and Apple, have begun to design their own AI chips, in hopes of differentiating their products from those of rivals. This has major ramifications for companies like Intel and Nvidia, which will now be competing with their customers.

While I certainly am not an AI expert, we all must quickly up our knowledge in this area which I see leading advanced packaging into the next decade. A list of current participants has recently been compiled (shown in the table below) (link)

Recently on “Graphics Speaks” Kathleen Maher has looked at how some of these cloud companies, IP companies, and the traditional semiconductor companies all have conflicting ambitions in the AI market place . I recommend reading the full article.[link]

While cloud companies like Google appear to be favoring custom chips to augment CPUs and GPUs, Semiconductor and IP companies are designing chips to enable efficient hardware and neural net systems and Intel is proposing an open platform ecosystem based on Xeon, FPGAs, and specialized processors like Nervana and Saffron.

Google

Google’s Tensor Processing Unit (TPU), was introduced last year. Their initial beta customer Lyft, is using AI to recognize surroundings, locations, street signs etc. The cloud-based TPU features 180 teraflops of floating-point performance through four ASICS with 64 GB of high bandwidth memory. These modules can be used alone or connected together via a dedicated network to form multi-petaflop ML supercomputers that they call TPU pods.

Apple

The best known mobile AI processor is included in the Apple iPhone X. Apple’s A11 is a 64-bit ARM 6 core CPU with two high performance 2.39 GHz cores called Monsoon, and four energy efficient cores, call Mistral. The A11’s performance controller gives the chip access to all six cores simultaneously. The A11 has three-core GPU by Apple, the M11 motion coprocessor, an image processor supporting computational photography, and the new Neural Engine that comes into play for Face ID and other machine learning tasks.

Amazon

Amazon is reportedly developing a chip designed for artificial intelligence to work with the Echo and other hardware powered by Amazon’s Alexa virtual assistant (link). The chip should allow Alexa-powered devices to respond more quickly to commands, by allowing more data processing to be handled on the device vs the cloud.

Nvidia

Nvidia has announced its new Volta GPU with 640 tensor cores, which delivers over 100 Teraflops. It has been adopted by leading cloud suppliers including Amazon, Microsoft, Google, Oracle , and others. On the OEM side, Dell EMC, HP, Huawei, IBM and Lenovo have all announced Volta-based offerings for their customers.

Microsoft and Intel’s “Brainwave”

Microsoft has teamed with Intel and is offering their Stratix 10 FPGAS for AI processing on Microsoft Azure (see below) codename “Brainwave” (link) . Intel is proposing FPGAs  + processors for AI work. Intel is reportedly focusing on the Stratix X FPGA as a AI companion to Intel’s Xeon processors.

Intel’s 14 nm Stratix 10 FPGAs accelerate Microsoft’s Azure deep learning platform using FPGAs with “soft” Deep Neural Network (DNN) units synthesized onto the FPGAs instead of hardwired Processing Units (DPUs). Brainwave is designed for live data streams including video, sensor feeds, and search queries.

Intel

Intel is making a major play in AI. Intel has multiple processor options for AI, including Xeon, FPGAs, Nervana, Movidius, and Saffron (link).

Saffron Technology was acquired by Intel in 2015. It develops “..cognitive computing systems that use incremental learning to understand and unify by entity (person, place or thing) the connections between an entity and other “things” in data, along with the context of their connections and their raw frequency counts…. Saffron learns from all sources of data including structured and unstructured data to support knowledge-based decision making.” It is being used extensively in the financial services industry.

In 2016, Inte­­­l announced acquired Nervana, a startup developing AI software and hardware for machine learning. In 2017, Intel revealed the Nervana Neural Network Processor (NNP) designed expressly for AI and deep learning.

Intel acquired Movidius in 2016 to get VPU (visual processor unit) technology for machine learning and AI. Intel’s Movidius devices include dedicated imaging, computer vision processing, and an integrated neural compute engine. Applications for VPUs include automobile license readers at bridges and toll roads, airport security screening, drone surveillance and the many applications of facial recognition.

ARM – Trillium Platform

The Arm Trillium Platform includes Machine Learning (ML) and Object Detection (OD) processors with Arm software, and the existing Arm compute library and CMSIS-NN Neural Network kernels.

It will be interesting to see hope the packaging community develops solutions that will be compatible with these advanced high speed HPC applications.

For all the latest on advanced packaging, stay linked to IFTLE…