Finishing up our look at the Suss Technology workshop at SEMICON West.

Nanium

Ricardo Gai, head of eWLB engineering at Nanium gave a presentation on wafer level fan out packaging, FO WLP. Nanium, headquartered in Portugal, is derived from the following bloodlines:

Click to view full screen.

Nanium has been in 300mm HVM of  FO WLP since Q3 2010 and has shipped more than 350MM packages. For a complete discussion of eWLB see IFTLE 124, “Status and the Future of eWLB.”

Process Challenges with eWLB:

• Warpage

– Warpage and shape changes during processing; stiffness is a key parameter to control;

– Equipment modifications are required to handle FO-WLP wafers

– hardware – new end effectors and new chuck sealing

– software – upgrades for warpage handling

• Die-Shift – In case of complex devices like (Multichip SiP), mask aligners are not capable of overlay requirements and a stepper is required.

Multi-Layer RDL for multilayer RDL the overlay must be smaller than the die shift. This also requires stepper technology.

Click to view full screen.

Fine RDL Line Width / Space and Fine Ball Pitch – – better resist technology is necessary to achieve L/S = 10/10

• Cost Pressures

– more die per carrier by using smaller edge exclusion zone

– larger substrate sizes

– 300mm and large panel processing to reduce costs.

• Future Challenges:

– thinner substrates will require temp bonding and front side protection

GlobalFoundries

Jon Greenwood of GlobalFoundries gave a presentation on 2.5/3D readiness for HVM. Global Foundries is dedicated to support the Collaborative Partner Model:

Click to view full screen.

They are creating a supply chain where GF is responsible for the wafer processing and backside integration (BSI) and assembly is owned by the OSAT partners.

Click to view full screen.

As we have discussed before [see IFTLE 142, “GlobalFoundries2.5 / 3D at 20nm…” ] 2.5D interposer work is ongoing in Singapore and 3D activity is in NY. In June 2013, they announced a certified set of design flows for 2.5D interposers. As the next slide shows, by 2015 they hope to offer TSV “in all nodes.”

Click to view full screen.

Greenwood announced that GF thinks their 2.5D and 3D packaging capabilities are proven and their primary focus moving forward is yield and COO reduction.

Amkor Ron Huemoeller Sr VP of Advanced Product Development at Amkor presented their position on 3D/2.5D Market readiness.

Design capability status – established

– Mass production of optical sensors since 2008

– Worlds first fully integrated MCM TSV product started production in 2011

– System integrated architecture proven on many platforms such as:

– multiple logic on Si  interposers

– logic + memory on Si interposers

– memory / memory stack

– memory / logic combination

Manfacturing Capability

– fine pitch Cu pillar in HVM

– wafer thinning equipment and infrastructure in place

– TSV etch equipment and infrastructure well-established

– Backside passivation – equipment and infrastructure well-established

– Backside bumping – equipment and infrastructure well-established

– wafer support – equipment and infrastructure in place but still needs improvement

Click to view full screen.

– Assembly can be done chip-on-substrate, chip-on-wafer or chip-on-chip

– more work is needed on testing memory prior to committing to package stack.

Memory

– End customer chooses memory supplier (only primary memory sources today)

– Receive as KGM on tape and reel

– receiving 2, 4 die stacks in wide IO format

Amkor now sees interposer use reaching “value markets” post 2015.

Click to view full screen.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

Finishing up our look at the presentations at ECTC 2013 in Las Vegas.

Shinko and CEA Leti detailed their presentation entitled “Warpage Control of Silicon Interposer for 2.5D Package Applications.”

Large silicon-interposers when attached to an organic substrate can cause significant warpage problems. Shinko / Leti examined several warpage control techniques including:

– Using a  “chip first process” where chips are mounted on the interposer first  vs “chip last process” where the silicon-interposer is mounted on the organic substrate first and chips are mounted onto the interposer last.

– using various underfill resins.

– using Sn-57Bi solder and thus lowering peak temperature 45-90 degree C. This reduced warpage after reflow to 75% of that using SAC305.

Comparison of warpage using different assembly sequences is shown below.

Click to see full screen.

Warpage of silicon-interposer using three types of underfills (shown below) for  0 level assembly (micro bumps) is shown below. Maximum warpage using U.F. A1, A2 and A3 were 108, 123 and 132mm, respectively. The lowest warpage was obtained at using U.F. A1. With U.F.A3, solder bump open failures were observed. The authors conclude that “… using underfill material with low Tg and high storage modulus for 0 level leads to high reliability.”

Click to see full screen.

TSMC and customer Xilinx presented “Reliability Evaluation of a CoWoS-enabled 3D IC Package” which used FEA to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Focus was especially on the fatigue failures of the C4 and BGA joints. Experimental data collected on CoWoS test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme.
Results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid.  While a  thicker lid has the higher stiffness and better co-planarity, the higher constraint from the thicker lid induces higher stress inside the package which negatively impacts  C4 bump fatigue and the micro-bump Ti/Al delamination.

C4 bump layer underfill with Tg of 70 C or 120 C, were studied. The underfill with lower Tg has higher driving force to C4 bump fatigue. When temperature is above Tg, the underfill has much lower Young’s Modulus which has much lower capability to protect C4 bump; and therefore the underfill with lower Tg has higher driving force to C4 bump fatigue. On the contrary, the underfill with lower Tg has lower driving force to Ti/Al delamination in the micro-bump structure. TheC4 underfill with lower stiffness can play as a buffer layer and results in lower driving force to Ti/Al delamination in microbump.

Click to see full screen.

IMEC reported on “Key Elements for Sub-50μm Pitch Micro Bump Processes.”
Scaling the ubump pitch from hundreds to a few tens of microns is not straightforward. Several process parameters need to be taken into account to allow a reliable Cu(Ni)Sn ubumping process. One of the challenges for fine pitch Cu(Ni)Sn stacking is to obtain a high bump uniformity. The non uniformity prevents Cu and Sn from having good contact and subsequent intermetallic formation and increases the risk of underfill entrapment.

A bump scheme that offers better margin for alignment error is better based on a scheme where the size of top die bumps is smaller than the size of the bottom pads. For example it is better to achieve  20μm pitch with 7.5μm bump on 12.5μm pad than with 10μm bump and pad because  equal bump and pad diameter can tolerate only 2μm misalignment whereas the  7.5μm/12.5μm bump/pad can tolerate 5μm. This is a significant difference when working close to the stacking tool’s limit of alignment accuracy.

Details on the plasma treatments necessary when attempting to plate into these fine featured plating resists are also discussed.

RTI  detailed a process for the fabrication and bonding of 100 and 200um  thick silicon interposers with filled 4:1 AR copper filled TSVs and front side and backside multilevel metal copper/ thin film polymer  routing layers in their presentation ”Fabrication and Testing of Thin Silicon Interposers with Multilevel Front side and Backside Metallization and Cu-filled TSVs.”

Click to see full screen.

For most applications, the desired thickness for Si interposers is below the thickness at which unsupported wafers can be safely handled through the necessary fabrication processes (i.e. 100 -200um). In these cases a temporary wafer support system, consisting of a carrier wafer and a layer of a temporary adhesive, must be used.

3M’s Wafer Support System (3M WSS™) and Brewer Science’s WaferBOND 9001™ were the temporary bond materials selected in the RTI program. Multilevel metal was done on either side of the interposer using polymer thin film dielectrics. The front side of the device wafers was patterned with two layers of Cu and three layers of polyimide (HD-4100 from HD Micro). After frontside patterning, the wafers were bonded face-down to temporary carrier wafers coated with temporary adhesive. Backgrinding and CMP were used to thin the wafers to a nominal thickness of 100 um. After thinning, a backside Cu routing pattern was formed between two layers of either  BCB 4024-40 (Dow Chemical), HD-8930 (polybenzo-bisoxazole [PBO] HD Microsystems), with curing temperatures of 250˚C and 200˚C, respectively, at or below the temperature limit of the temporary adhesive. The polyimide that we used for the front side MLM structure has a recommended cure temperature of 375 C which would be incompatible with any currently offered temporary adhesive.

Both the 3M and the Brewer wafer bonding solutions were found to be compatible with the processing of the different spin-on dielectric materials used to fabricate frontside and backside MLM structures. Successful debonding of the carriers was done both at the wafer level before dicing and at the die level after dicing and bonding to a substrate.

In both, the 100um and 200um interposer thicknesses with 25um or 50um diameter TSV respectively, an annealing step was found to be successful in preventing Cu from extruding from the TSVs during the subsequent polymer curing steps. Electrical testing before and after thermal cycling showed the high yield and stability of all of the interposer structures irrespective of the dielectric materials choice.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

Am I the only one who missed Semicon West?

I had a full week of workshops and 1-on-1 meetings set up for Semicon West, but due to the Korean crash, United canceled my Sunday flight and rebooks me for Tuesday night (I’m a million mile flier, so imagine the service the peons got!) then my replacement Delta flight was cancelled on Monday again with no seats on flights into SF, Oakland or San Jose till late Tuesday. I finally concluded some things are simply not meant to be.

The Suss technology forum that I helped set up and was set to moderate went on without me so I’d still like to cover some of the materials that were presented there.

Let’s look first at the material suppliers.

Lord

Le of Lord gave a presentation on their photo definable silica filled epoxy “solder brace” material which they propose to use as a final passivation in a standard WLP redistribution process.

We are shown data concluding that the “solder brace” shows better thermal cycling reliability (-40 to +125 C) and drop test results then an unidentified “PI” , but without clear understanding the identity of the PI and all the design dimensions involved (such as thickness of the screen printed epoxy vs the spun PI) it is hard to draw any substantial conclusions from the data.

Since screen printing is not a usual unit operation in a standard redistribution process this might be a barrier to acceptance for such a filled product.

Click to view full screen.

Brewer Science

Smith of Brewer Science detailed the separation technologies available for their ZoneBond Process. The temporary adhesive ring of the ZoneBond process can be removed either by immersing the temp bonded wafer on a perforated carrier in a solvent bath as shown below:

Click to view full screen.

Or,  by trimming the narrow bonded ring post fabrication to release the device wafer, where:

–          Debonding occurs at room temperature.

–          Separation occurs at the carrier-to-adhesive interface, not the adhesive-to-device interface.

–          Device is mounted in the film frame and is firmly supported on a vacuum chuck during debonding.

This allows higher-temperature-capable adhesives

–          Thermally stable in bonded pair to 240°-260°C (depends on processing parameters)

Click to view full screen.

Dow Corning

Ho of Dow Corning presented their new silicone based bi-layer temporary bonding solution. Their Bond/Debond Process Flow is shown below.

– Spin-coat bi-layer (release and adhesive layer)

– Room temperature bonding / debonding

– post-bonding cure on hot plate

– no plasma or lasers necessary

– fast mechanical debonding

Click to view full screen.

Dow Chemical

Gallagher of Dow Chemical detailed their photo and laser patternable plating resists and dielectrics for WLP and 3D TSV.

Their Novolac (positive) and Acrylate (negative) resists are capable of a brad thickness range.

Click to view full screen.

Their Cyclotene (BCB) dielectrics are laser patternable and their Intervia (epoxy) dielectrics show excellent vertical sidewalls. They also highlighted BCB as a temporary bonding solution which shows high thermal stability during backside processing ( , 1% weight loss at 300 C per hr) and clean RT mechanical peel-off debonding.

Suss

Lutter, of Suss, compared the temporary bonding solutions that Suss supports focusing on the room temp mechanical debonding solutions.

Click to view full screen.

The mechanical release at RT is described as follows:

Click to view full screen.

Zonebond and several other solutions show excellent TTV (2-3um) after thinning to 50um.

Click to view full screen.

Flex frame tape is a key to good debonding and cleaning . The principle of Suss debonding is shown below.

Click to view full screen.

IEEE 3DIC

The IEEE’s premier 3DIC conference is on tap for the USA again this year. The conference will be held in San Francisco the first week of October. You can register here [link]

Let’s take a look at the program:

Click to view full screen.

Wednesday, October 2nd  – Free Tutorials!

13.00 – 14.00 Tutorials: 2.5/3DIC Players, Products & Markets, Rozalia Beica – Yole Developpement

14.00 – 15.00 Tutorials: 3DIC – Prof. Mitsu Koyanagi, Tohoku University

15.00 – 16.00 Tutorials: Design for 3DIC, Prof. Paul Franzon – NCSU

16.00 – 17.00 Tutorials: TSV and Interposer Design for High Performance and Low Noise,  Kim- Kaist

17.00 – 18.00 Tutorials: Monolithic 3DIC, Zvi Orbach

Thursday, October 3rd

08.30 – 09.45: Keynote Speaker: Prof. M. Taklo, SINTEF, Title:” E Brains”

09.45 – 10.15: Invited Talk I “ 3DIC Activity at Tohoku “  Prof. Mitsu Koyanagi, Tohoku University

13.00 – 13.30: Invited Talk II – “A Perspective on Manufacturing 2.5/3D”  Robert Patti, Tezzaron

17.00 – 18.00: Panel Session “Progress and Outlook for 3D ICs and 2.5D Systems –

Moderator: Jan Vardaman, TechSearch

Friday, October 4th

08.30 – 09.00: Invited talk III “The DARPA ICECool Program”  Avi BarCohen, DARPA

Hope to see you all there.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

Finishing our look at the June 2013 ConFab packaging activities.

Amkor

Bob Lanzone, Sr VP of Engineering Solutions for Amkor, like the other OSATS sees smartphones and tablets driving the market moving forward.

Click to view full screen.

If you ever wondered who the key players were in each of the mobile phone IC functions, Lanzone used this enlightening slide from Gartner.

Click to view full screen.

Amkor’s update on Copper Pillar technology indicates an expected doubling in demand this year and continued expansion into “all flip chip products.”

Click to view full screen.

Their “TSV status” takes credit for being the first into production with TSMC and Xilinx.

Click to view full screen.

Looking at the 2.5D TSV & Interposer Supply Chain they see:

• High End Products : Networking, Servers

– Silicon interposers ; < 2um L/S, < 15nsec latency, > 25k μbumps per die

– Amkor is engaged with Foundries to deliver silicon interposers today

• Mid Range Products : Gaming, Graphics, HDTV, Adv. Tablets

– Silicon or Glass interposers ; < 3um L/S, < 25nsec latency, ~10k μbumps/die

– Not actively pursuing glass interposers yet as infrastructure still immature

• Lower Cost Products : Lower End Tablets, Smart Phones

–  Silicon, Glass or Laminate interposer ; < 8um L/S, low resistance, ~2k μbumps

– Must provide cost reduction path to enable this sector

– Working with laminate supply chain to enable

They are targeting 2014 for their “possum” stacking as shown below:

Click to view full screen.

Click to view full screen.

Siliconware (SPIL)

In the presentation “The expanding Role of OSATS in the Era of System Integration,” Mike MA , VP of R&D for SPIL looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.

Click to view full screen.

He discusses the two current business models for 2.5D, which are the “foundry model” supported by TSMC and the “collaboration model” supported by GF and UMC. He now adds a third model “the OSAT turnkey model which is now supported by TSMC.

SPIL is the first OSAT to propose this OSAT centric model where the interposer is fabricated by the OSAT who then assembles and tests modules made with chips from multiple sources.  The impediment to this route in the past has been the lack of OSAT capability to fabricate the fine pitch interposers, which require dual damascene processing capability, which until now was only available in the foundries. SPIL has now announced the equipment for fine pitch interposer capability (>2 layers, 0.4-3um metal line width and 0.5um TSV ) has been purchased and is in place.

Ma indicates that while the foundries are not happy with this SPIL proposal, their customers, especially their fabless customers have been very supportive.  He feels the inherent lower cost structure of OSATS will have a positive impact on the 2.5/3D market which has been somewhat stagnant since the FPGA and memory product announcements in 2010.

Click to view full screen.

SPIL also announced a wafer level fan out (WLFO) program on 370 x 470mm organic based panels which they feel is a potential low cost solution for those with lower density interposer requirements.

Click to view full screen.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

Continuing with our look at the 2013 ECTC.

Siliconware detailed the “Integration Challenges of TSV Backside Via Reveal Processing.”

After via formation, finished CMOS wafers or interposers are temporarily bonded to glass carriers. The TSV are ‘ revealed ‘ by Si back grinding and plasma etch steps, passivated with PECVD nitride, and CMP’ed to open the Cu pillar area. The via reveal processes must maintain acceptably low

TTV to allow subsequent bonding/stacking steps. Also the process temperature must be lower than the carrier bonding adhesives which is a particular challenge for the dielectric deposition step. The SPIL backside reveal process is shown below.

Click to view full screen.

A major challenge of the via-reveal process is control the exposed copper TSV height, because incoming wafers to via reveal can have significant compounded variation, such as TSV depth uniformity, glass thickness uniformity, adhesive thickness uniformity and Silicon thickness uniformity after grind.

SEMATECH and RPI reported on their studies on “Backside TSV protrusion induced by thermal shock and Thermal Cycling.”

The TSVs used for this study were fabricated on 300mm wafers with a TSV height of ~50μm

and an aspect ratio of ~10:1. The front side of the TSV wafer is bonded face down on a handle wafer and  backside-thinned to reveal the TSV and metallized to form testing lines and pads. The cross section schematic below shows the structure.

Click to view full screen.

Various combinations of thermal loads (RT –  200 C – 400 C) and ramp-up/cool-down rates (0.167 C/s to 25 C/s) are used for thermal shock and thermal cycling tests. No TSV protrusion is visible at 200 C or below, while larger TSV protrusions are observed at higher peak temperatures.The avg TSV protrusion height, collected from 108 single TSVs under 3 testing pads over each die, increases from 0.1μm at 250 C to about 0.5μm at 400 C.

Click to view full screen.

The TSV protrusion varies significantly from TSV to TSV, resulting in big error bars. This is reportedly due to the grain boundaries in each TSV (particularly near the Cu testing pads) being very different from TSV to TSV, indicating that the key mechanism for the protrusion could be related to the Cu grain boundary diffusion.

SEM images of the TSVs reveal delamination is observed at the interface between the Cu TSV and the Cu testing pad on top of the TSV-1, while delamination between Cu TSV sidewall and oxide liner is found in TSV-2.

Click to view full screen.

IMEC also reported on protrusion issues in their paper “Impact of Post Plating Anneal and TSV Dimensions on Cu Pumping.”

When Cu-filled TSVs are exposed to high temperatures during BEOL processing, compressive stresses arise in the Cu TSV due to the large difference in coefficient of thermal expansion with the surrounding Si. These stresses are partly relaxed by irreversible extrusion of the Cu, a phenomenon known as ‘Cu pumping,’ which may damage  the BEOL layers on top of the TSV. In order to reduce the amount of Cu pumping during BEOL processing, a high temperature anneal step can be applied after TSV plating and before Cu CMP.

IMEC, who is generally given credit for offering an anneal solution  protrusion problem in 2011 has now  used optical profilometry to study residual Cu pumping in TSVs with different post-plating anneals and different TSV dimensions ( 5 x 50um vs 10 x 100um ). In total ~ 4000 TSVs were inspected. Within one sample the Cu pumping values show  an intrinsic large spread, therefore the distribution tail rather than the median is determining the impact on BEOL reliability. Lower pumping was found in TSVs annealed at higher temperatures and for longer times. The sinter conditions of 20 min at 420 °C were confirmed as optimal post-plating anneal conditions.. However, in order to effectively control the impact on BEOL reliability, development efforts should also be aimed at reducing the Cu pumping distribution width.

Click to view full screen.

SUNY Binghamton and SEMATECH presented their work on the “Mechanism of Low Temp Cu-Cu Direct Bonding for 3D TSV Package Interconnect.”

While the solder-based approach for connecting chips to packages or chips to chips has become the industry standard for at least the first generation of 2.5/3D products, but the potential to significantly drive this approach to finer pitch interconnects is limited. The leading method for fine pitch chip-to-chip interconnects (pitch of 10 microns or less) is generally believed to be Cu-Cu direct bonding. In the direct bonding of Cu to Cu, the flatness of the surface on a small scale (~1 micron) or a large scale (wafer or die scale) and the chemical condition of the surface play important roles in the quality of the bond. Other factors such as the Cu grain size and grain orientation may also impact the quality of the Cu-Cu bond.

Therefore, it is necessary to use a reducing gas to decompose the oxides. Forming gas, which is a mixture of H2 and N2, can provide such a reducing environment to decompose copper oxides effectively.  Prior attempts to surface passivate / clean including self-assembled monolayer passivation, plasma cleaning and chemical mechanical polishing with a formic acid clean all result in  improved bond quality as a result of the passivation and cleaning approaches used. The Bingham / Sematech group CMP’ed the copper in the presence of benztriazole which protects the copper surface during CMP, but does not prevent oxidation once the CMP is complete. The cleaned surfaces were then exposed t atmospheric conditions for varying times and reexamined by XPS (Xray photoelectron spectroscopy)

Cu2O and CuO can observed on the clean Cu surface after a short atmosphere exposure (1 minute), while Cu(OH)2 and/or CuCO3 can be observed on the surface after longer exposures longer exposures (>30 minutes).

Wafers were cleaned by Ar sputter cleaned (NA) or annealed at 200ºC in forming gas (FGA).  Both wafer pairs were bonded within minutes after cleaning by thermo-compression bonding with a force of 80 kN at 195°C for 5 minutes. Samples of NA and FGA wafers exposed to the atmosphere for 30 min and then examined by XPS showed both CuO and Cu2O but no Cu(OH)2.

The NA and FGA Bonded Wafers were characterized by CSAM looking for voiding. The image of the bond interface for the FGA wafers indicates  an absence of voids for almost the entire interface, whereas the image of the bond interface for the NA indicates voids throughout the interface. They attribute the better bonding for the FGA wafers to more effective Cu oxide removal by the forming gas anneal.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

Those of you that are readers of SST know from the editorials and blogs of Editor Pete Singer that the ConFab is Solid State Technology’s annual conference and networking event. This year, it was held in June 23-26 in Las Vegas.  The overall theme of this year’s conference is “Filling the fabs of the future.” IFTLE put together two sessions on packaging  which were jointly sponsored by IEEE CPMT and ConFab.

The most significant packaging announcement from the ConFab was SPIL announcing that they have put dual damascene in place and are ready to start supplying high-density interposers to the industry.

Sony CMOS Image Sensor 3D Stacking

Fellow bearded blogger Dick James of Chipworks, in his presentation “Inside Today’s Hot Products” showed some great X sections of the Sony IMX135 13 Mpixel CMOS Image sensor. One of the first stacked image sensors it consists of a 90nm back illuminated sensor bonded F2F with a 65nm image processor.

Click to view full screen.

IBM Orthogonal Scaling

Subu Iyer, IBM Fellow, lectured on his theme of “orthogonal scaling.” His premise is that classical silicon scaling is saturating and we need orthogonal approaches to “scale all aspects of the system including footprint and power.” Subu sees scaling continuing down to the 7nm node, but  “the cost per transistor has begun to saturate.”

Click to view full screen.

He predicts that the next component of Advanced System Integration will be 3D Integration:

– large interposer platform for heterogeneous integration

– Die Stacking

– stacking of logic die (high and moderate power)

– stacking of memory die (low power)

– Wafer level stacking

His example of stacked memory is the Micron IBM program on stacked memory:

Click to view full screen.

TI Thins Down Packaging

Devan Iyer, worldwide Dir. of Packaging for TI showed the thickness progression from the 1.75mm SOIC to the 0.075mm PicoStar-2G

Click to view full screen.

Iyer points out that while Package families are  proliferating, each package type has a “sweet spot” combination of cost, performance, form factor and reliability, driven by:

•Cost

•Electrical speed, power distribution and noise immunity

•Power dissipation

•Thickness, weight, PCB area consumption

•Board level reliability (BLR, drop)

•Environmental reliability

•Technical maturity vs. risk in high-volume manufacturing

•Testability

•Compatibility with Si process

STATS

Anderson of STATSChipPAC  points to smartphones and tablets driving our industry right now.

Click to view full screen.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

Continuing our look at key presentations from the 2013 IEEE ECTC Conference.

IMEC and Brewer Science reported on the “Integration and Manufacturing Aspects of Moving from  Waferbond HT 10.10  to ZoneBOND in Temporary Wafer Bonding.” Temporary wafer bonding has become a key element in the emergence of 3D Stacked IC technologies. In the past, approaches such as IMEC’s have relied on the “thermal slide process” to debond the thinned wafer from the carrier.  There was a desire to move away from this process for several reasons including: (1) stresses that are generated can cause cracks in thinned wafers, especially those containing TSV; (2) slide debond normally conducted > 200 C which accelerates solder diffusion; (3) cannot slide debond if already on dicing frame since no dicing tapes can take temps > 200 C.  This led to the development of the ZoneBOND process which has been described previously.

Integration Changes Required for the ZoneBOND process

In the standard process sequence edge trimming is done to the device wafer prior to temporary bonding. If this is done in the ZoneBOND process, the find that adhesive is trapped in the trimmed region of the wafer and clogs the grinding wheel during backside thinning.

A new integration scheme is proposed where edge trimming occurs after the bonding step as shown below.

Click to view full screen.

Debonding is performed at room temperature in a SUSS DB12T debonder. First, a wet edge preparation is required in order to eliminate the high adhesion area of the adhesive layer between the 2 substrates. Then, the thin device wafer still bonded to the carrier is laminated onto a dicing tape on frame. Next, the room temperature peel off debonding separates the thin wafer from the carrier while the thin wafer is still on tape and on frame. A final cleaning step on tape is performed to remove adhesive residues from the device wafer.

CEA Leti reported on their comparison between the  “WSS and ZoneBond Temporary Bonding Techniques.”

The ZoneBOND technique requires silicon carriers that are treated with an antistick layer with an edge exclusion to ensure the adhesion. Temporary glue can be deposited either on the device, either on the carrier. Bonding is achieved under elevated temperature and separation requires a specific soaking of the bonded pairs to preliminary remove the adhesive from the edges.

Click to view full screen.

The WSS system requires transparent carriers as the temporary adhesive is cured after bonding by UV exposure. Separation is enabled by a laser exposure which modifies a sensitive layer (named LTHC for Light to Heat Conversion) that has been deposited before bonding on the carrier.

Click to view full screen.

Pros and cons of the processes are given in the attached table.

Click to view full screen.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.

Continuing our look at the Osaka ICEP conference held in April 2013.

ASET and Tohoku Univ

ASET and Tohoku Univ reported on the effects of thinning on DRAM and CMOS device characteristics. Basically the thinner the chip becomes, the more likely it is that mechanical stress will alter the device characteristics and that ionic impurities will contaminate the transistors.

Perhaps most importantly they thinned a 65nm NMOS DRAM to 200 um by mechanical grinding and then further thinned down to 30um by stress free CMP. They then examined the data retention time of the chip vs thickness (see below). Data retention of the 30um thick device was ½ of that of the 200um device!

Click to view full screen.

DNP

Dai Nippon Printing and AIST have examined the fabrication of interposers on 300 mm wafers and attempted to reduce cost.

500um thick interposers with 50um diameter TSV were fabricated on 300 mm wafers, insulted with SiO2 (TEOS based PECVD), filled with ECD Cu and the Cu CMP’ed to remove overburden (50-100um). They note that it was “difficult to form void free TSV due to he high aspect ratio (10:1).  Backside RDL was done with PBO dielectric (8um deposited and 50% shrinkage). They conclude that this process flow eliminates the need for wafer support since the 500um thinned wafers can be directly processed without support.

Click to view full screen.

ITRI

ITRI described their studies on the assembly of 3D stacked chip with 30um pitch microbump interconnects using both non conductive paste (NCP) and anisotropic conductive film (ACF).

The bump structure for NCP bonding is shown below. Cu/Ni/Sn solder micro bumps are connected to Cu/Ni/AU micro bumps. For ACF Cu/Ni/AU micro bumps are joined to Cu/Ni/Au micro bumps.

Click to view full screen.

The NCP was an epoxy thermoset. Properties of NCP and ACF are shown below.

Click to view full screen.

The NCP assembled chip stack passed 1000 cycles of TCT and 1000 hrs of HTS without any failures. The ACF assembled stacks all failed after 85/85 testing for 100 hrs and showed 7% failure after 500 cycles of TCT.

ITRI also reported on the reliability performance of two capillary underfills with different Tg and CTE used for µbump bonding on a silicon interposer.

The 20 um pitch µbumps were composed of 5um Cu / 3um Ni / 5um Sn2.5Ag (solder cap). Thermo-compression bonding was used to interconnect the µbumps at 280 C for 15 sec and the gaps then filled by one of the two underfills. Their properties are shown in the table below.

Click to view full screen.

Temp cycling data resulted in the Weibull plot shown below. The mean time to failure of underfill A (higher Tg) vs B was 20% higher.

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Ishihara Sangyo Kaisha (ISK)

ISK described the development of oxidation resistant Cu nanoparticles (50nm). Cu ink was prepared and printed (13um thick). Thermal treatment [ 200 C for 60 min under N2 + O2 followed by 250 C for 60 min under N2 + H2] This thermal sequence “burns” off the organics and sinters the particles to form a 0.2um copper film with 0.5um cm resistivity.

Osaka Univ

Osaka Univ reported that Cu to Cu joining can be accomplished using Cu nanoparticle paste (10-20nm particles in glycol protective solvent) They examined the shear strength of the joint vs thermal treatment atmosphere and temperature. The strongest bond (40 MPa) was achieved through 673 K bonding for 300 sec under 15MPa pressure with a N2/O2 atmosphere.

Tohoku Univ and Korea Institute of Industrial Tech

Tohoku Univ and Korea Institute of Industrial Tech studied the interfacial reaction between solder filled TSV and copper pillar bumps. Ti layer  (50 – 400nm thick) was used as barrier layer between solder and Cu pillar bump. Thermal aging for 500 hrs at 150 C was conducted and the interface examined. IMC thickness increased with aging time and as thickness of Ti increased the IMC thickness decreased.

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Finishing up our look at the 2013 IMAPS Device Packaging Conference

Leti

Leti examined the reliability of die to wafer bonding using copper/tin interconnects.  Above 232 C tin rapidly reacts with copper to produce higher melting point intermetallic compounds.

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They studied thermal cycling, TC (500x -40 to +125 C) and high temp storage, HTS (84 hrs at +125 C) for both underfilled and non underfilled Cu/Sn joints and found that TC has a more pronounced negative effect on yield and electrical performance than HTS.

After thermal cycling one finds increased growth of the Cu3Sn layer and cracks at the Cu/Cu3Sn interface. Underfilling has a positive impact on yield and electrical performance.

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Leti also addressed the thermal and mechanical challenges of 3DIC integration.

In terms of mechanical issues, everyone agrees that BOW is the problem. Potential solutions include:

– compensation layers on both sides to match stress.

– compliant interconnect

– increase interposer thickness

– control polymer encapsulation.

The following is an interesting plot that they use to make the point that a thicker substrate is better for mechanical stiffness. IFTLE thinks this is a bit of an over simplification since it depends on the modulus of the insulator layers and the encapsulation and their thicknesses. Certainly the general conclusion is correct.

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Dow Chemical

Dow Chemical and Fraunhoffer IZM presented new data on BCB based  temporary bonding adhesive. The process flow for temp bonding is shown below:

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Wafers can be bonded at 80 C with a bond time of ca. 1 min. and subsequent oven curing at 210 C for 1 hour. They find no alignment shift after curing. Wafers show no voiding or delamination after 1 hr at 325 C indicating excellent stability for all backside processing.

Mechanical debonding at room temp needs no irradiation or chemical treatments to release the thinned wafer. The mechanical debond is reported to be “residue free.”

If bumped first, one can coat twice to build up greater than 80um of BCB. Mechanical peel off reportedly does not delaminate any bumps. Subsequent cleaning is done with IPA.

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Dow has also developed a pre-applied underfill materials set. We were shown 25um thick film roll that was 330mm wide.

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Dow also gave an update on the new BCB XP 120201 a new low stress version of their positive tone, aqueous developable 6500 series. It has reported  cure temp less than 180 C and an elongation at break now greater than 25%.

STATSChipPAC (SCP)

SCP, one of the acknowledged leaders in fan out WLP announced the use of a new organic dielectric which results in more robust mechanical performance and now allows the packages to pass -55 to +125 thermal cycling. They have gotten 11 x 11mm 28nm die in 14x14mm substrates on 0.4mm pitch to pass reliability.

For the latest on 3DIC and advanced packaging, stay linked to IFTLE…