By Dr. Phil Garrou, Contributing Editor

The IMAPS Device Packaging Conference was once again held in March in Arizona. Here is a look at some of the more interesting papers from the conference.

AMKOR – 2.5/3D Readiness

In Amkor’s presentation on 2.5/3D readiness, the following slide showing product qualifications was of special interest.

2.5D & 3D product qualification data is shown below:

GlobalFoundries TSV Readiness

GlobalFoundries TSV technology is qualified and ready for HVM ramp for all <28nm nodes Fab 8. Std TSV size is typically 5 x 55um.

Thermo-compression bonding is used for assembly.

• First, thin TSV die bonded chip to substrate (CoS) using non conductive paste (NCP)
• Top dies then bonded chip to chip (CoC) during 2nd bond on top of first stack
• TC-NCP process is used to minimize stress on ULK layers during cool down

Warpage characterization is critical during design and reliability phase of development along with production yield improvement.

• 3 different backside passivation layers were assessed in terms of impact of film stress on warpage
• Backside passivation film stress does not play a big role in overall package warpage
• Top Die Thickness impact on warpage
• Package level warpage in the order of 125um was measured at peak temperature for 100um thin top die
• With 260um thick top die package warpage was reduced to 80um at peak temperature
• Packages with 100um top die and thus increased stress / warpage clearly showed cracks appearing in the Cu pillar joints. Thus higher warpage clearly leads to degraded electrical performance of copper pillars in the corners of the package

CEA Leti

While most of us were focused on 3D stacking of memory chips, CEA Leti was studying the stacking of capacitor chips. Using the PICS capacitor technology of IPDIA, Leti demonstrated that a smaller thin film cap footprint could be achieved if silicon caps are stacked and connected in parallel.

Several attacking technologies are proposed including TSV and more traditional WB.

Various packaging solutions are presented including a molded version (shown below) but IFTLE strongly disagrees the inference that such packages can withstand near 400C since IFTLE has expressed many times that thermal stability needs t be determined from isothermal TGAs NOT ramp TGAs like the one show. Ramp TGAs tend to highly exaggerate the thermal stability of the samples in question, for instance epoxy mold compounds are NOT stable at anywhere near 400C.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The Taipei Times headline on April 18^th read “New packaging may spur TSMC growth” adding that despite its weak revenue growth guidance for this quarter, TSMC, might see stronger growth from next quarter thanks to its InFO (integrated fan out) packaging technology [link].

The Times reports that InFO could help TSMC beat rival Samsung and win more A10 application processor orders from Apple, because the technology offers “…lower costs, higher speed and thinner form factor when compared to conventional flip chip packaging”. TSMC is preparing a complete InFO portfolio aimed at different package sizes and applications. In a conference call with investors on last week, TSMC CEO C.C. Wei stated that they have almost completed equipment installation and expect to complete customer product qualification shortly. They plan to ship volume production shortly. Estimates are that the revenue contribution from InFO packaging could total US$300 million this year.

IFTLE has previously reported that TSMC had purchased a facility in Longtan, Taiwan (from Qualcomm for $85MM) and was turning it into a facility devoted to the manufacturing of integrated fan-out wafer-level packaging (InFO-WLP) technology. [see IFTLE 219 “TSMC INFO factory…” [link]

Apple is expected to unveil its new iPhone in the second half of this year. Daiwa Capital Markets analysts estimates that Apple’s order split for A9 processors (last generation) was 45% for TSMC and 55% for Samsung, but projects TSMC could take more than 50% of the A10 processor business, due in part to the superior packaging technology now being offered by TSMC. Other smartphone chip vendors are reportedly looking at adopting TSMC InFO packaging technology in the near future.

IFTLE has reported previously that TSMC lost the chance for making Apple A3 processors to Samsung because it lacked the capability to package and test the chips [link].

YSIC (Yuanta Securities Investment Consulting) claims the InFO technology is at least 20 percent cheaper than flip chip packaging. YSIC notes that “… it is becoming more difficult to solely rely on front-end tech node migration to drive better performance and cost” , a statement that should be very familiar to readers of IFTLE.

In 2014, IFTLE discussed TSMCs announced ambition of becoming a major player in full back-end packaging services with their plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 [ See IFTLE 190 “TSMC Focus on Packaging….”] [link] . Based on this roadmap, TSMC would become the 3rd leading packaging company in Taiwan by 2016, trailing only ASE and SPIL.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Wide band gap semiconductors are extremely attractive for power electronics applications. GaN is a binary III-V wide-band gap ( 3.4 eV) material. Since GaN transistors can operate at much higher temperatures and work at much higher voltages than gallium arsenide (GaAs) transistors, they make ideal power amplifiers at microwave frequencies.

GaN has shown to have applications in optoelectronic, high-power and high-frequency devices. Because GaN offers very high breakdown voltages, high electron mobility, and saturation velocity it is also an ideal candidate for high-power and high-temperature microwave applications like RF power amplifiers at microwave frequencies and high-voltage switching devices for power grids.

GaN devices target both military (ship-board, airborne and ground Radars and high performance space electronics) and commercial applications ( base station transmitters, C-band Satcom, Ku-K band VSAT and broadband satellites, LMDS and digital radio).

There are basically two manufacturing (growth) processes, based on either Silicon or Silicon-Carbide substrates. GaN-on-Si has a significant cost advantage that is driving down the cost curve.

Initially, it seemed GaN-based devices would be affordable only for military applications, such as the development of electronic warfare, radar, and high security communications systems. However, material maturity, improvement in yield, expansion to 4” wafers and lower-cost silicon growth process has reduced GaN-based device costs and therefore an economical option for commercial applications as well.

Growth of the GaN device market has required the development of novel packaging solutions. Since GaN HEMTs are thermally limited significantly below the electrical capability of the devices. The challenge of a GaN HEMT is its heat flux at the gate fingers, which cannot be effectively addressed by conventional packaging and thermal management systems.

The DARPA ICECool program is developing liquid cooling solution for such hot GaN devices. [see IFTLE 119, “ICECool putsThermal Issues Back in Focus”.]

Non liquid cooling solutions are also under development at facilities such as HRL (Hughes Research Labs). While thermal heat spreaders are usually limited by the TIM (thermal interface materials ) used to attach them, The HRL solutions electroplate the heat sink right on the back side of the GaN device or module. For instance see the process sequence below, developed by Herrault and co-workers at the HRL Labs in Malibu CA.

First, GaN dice are temporarily bonded face down onto a carrier wafer using a temporary adhesive layer. The silicon body wafer, which consists of through-wafer cavities, is also bonded face down onto the carrier wafer, as depicted in the figure (a). Next, a Ti/Au seed layer is sputtered over the wafer, and copper is electroplated and subsequently polished down to the surface of the silicon wafer as shown in (b). This step forms the integrated thermal heat spreader. Therefore, there is intimate contact between the high-thermal-conductivity heat spreader and the high-power-density GaN device, which is beneficial for high-performance thermal management. The silicon body wafer was used as a polishing barrier for the copper removal, enabling a flat and smooth backside for additional processing steps. The combination of use of a silicon body wafer, electroplating and chemical mechanical planarization (CMP) process eliminates the need for a bonding layer between the chip and the heat spreader, and therefore reduces the overall thermal resistance from junction to baseplate.

The body wafer with copper-embedded GaN dice is then released from the carrier wafer. Front-side electroplated gold connectors and bond pads are then fabricated using standard microfabrication technologies. The silicon cap with TSV allows connections to the outside of the module.

The technology is compatible with integration of multiple chips (GaN, CMOS, SiGe) from different semiconductor technologies and with different thicknesses since the chip thicknesses are absorbed by the plated copper which is subsequently CMP’ed.

Compared to conventionally mounted GaN power amplifiers (PA) using AuSn solder, an electroformed (called ITAP) X-band PA showed 1.4x improvement in CW Pout (4.4W at 8 GHz) while the ITAP Ku-band showed 1.3x improvement in CW Pout (4W at 12 GHz). Compared to silver epoxy mounted PAs the improvement was 2x and 1.5x, respectively.

The figure below plots Junction temperature vs. dissipated power density using gate resistance test structures. The electroplated heat sinks (ITAP 1 & 2) increase the power handling by 1.45x (for Tj of 150°C) or reduce Tj by 40°C (at 2W/mm dissipated power density).

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The Taipei Times is reporting that the Taiwan Fair Trade Commission has suspended its review of ASE’s bid to take over SPIL (link). ASE’s prior acquisition of a 25% stake in SPIL has raised anti-trust concerns and fears that the merger would undermine competition in the market.

The decision means a victory for SPIL who has fought the acquisition. SPIL, which has repeatedly urged the commission to terminate the review of the acquisition welcomed the FTC’s decision.

ASE released a statement saying it will continue with our plan to acquire 100 percent equity interest in SPIL through all legally permissible means and avenues.” ASE will be able to continue raising its ownership in SPIL through open market purchases including intra-day trading, block trades, and acquisition of SPIL’s Nasdaq-listed American depositary receipts. If ASE’s stake in SPIL exceeds the 33% threshold, ASE will need to apply to Taiwan’s Fair Trade Commission (FTC) to merge with SPIL.

Intel Admits Moore’s Law Coming to an End…Predict What Might be Next

The recent issue of MIT technology review noted that “Intel will slow the pace at which it rolls out new chip-making technology, and is searching for the appropriate successor to silicon transistors.” (link)

They note that Intel in their 2015 10K report last month disclosed that it is slowing the timing at which it moves to the next scaling node. Intel has already pushed back the debut of its first 10nm chips from the end of this year to sometime in 2017 noting that it can’t keep up the pace it used to.

We all know it is becoming more difficult to shrink features further in a cost-effective manner, but this doesn’t mean that future devices will stop improving. Intel says that in the future, it will make improvements to the way chips are designed. They add that for many important new applications such as wearable devices and medical implants, chips are already powerful enough and power consumption is more important.

William Holt, who leads the company’s technology and manufacturing group, speaking at the International Solid State Circuits Conference said that for chips to keep improving, Intel will soon have to start using fundamentally new technologies in about four years. While Intel has not yet announced silicon’s successor, most technologists feel that the two leading candidates are spintronics and tunneling transistors.

Neither of these technologies offer increases in computing power and neither are ready for volume manufacturing. Both would require major changes in how chips are designed and manufactured. While neither offer speed benefits over silicon transistors, the new technologies would, improve energy efficiency something important for many leading uses of computing today, such as cloud computing, mobile devices, and robotics. Future chips connect to household, commercial, and industrial objects and thus will need to be as energy efficient as possible.

Sine packaging experts need to be aware of what’s going on in the front end lets take a look at these technologies.

SPINTRONICS

Conventional electronic devices rely on the transport of electrical charge carriers – electrons – in a semiconductor such as silicon. Spintronics or “spin transport electronics”( also known as magnetoelectronics), depends on the intrinsic spin of electrons and the associated magnetic moment, in addition to its fundamental electronic charge, in solid-state devices. Devices follow the simple sequence:

1 – information is stored (written) into spins as a particular spin orientation (up or down),

2 – the spins, being attached to mobile electrons, carry the information along a wire, and

3- the information is read at a terminal.

Spin orientation of conduction electrons survives for a relatively long time which makes spintronic devices particularly attractive for memory storage and magnetic sensors applications, and, potentially for quantum computing [link].

Tunneling FET

The basic TFET structure is similar to a MOSFET except that the source and drain terminals of a TFET are doped of opposite type. A common TFET device structure consists of a P-I-N (junction, in which the electrostatic potential of the intrinsic region is controlled by a gate terminal. The device is operated by applying gate bias so that electron accumulation occurs in the intrinsic region. At sufficient gate bias, tunneling occurs when the conduction band of the intrinsic region aligns with the valence band of the P region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region and current can flow across the device. As the gate bias is reduced, the bands becomes misaligned and current can no longer flow.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 SEMI European 3D Summit.

McKinsey

A very interesting chart from McKinsey on 2014 economic profit in the microelectronics industry (below). It is clear that very few companies are responsible for most of the economic profit.

The big 5 of Intel, TSMC, Qualcomm, TI and Samsung contributed > 70% of the entire industries economic profit for the last 15 years.

The following are the top 10 2014 assembly and test companies.

While market share is key in most semiconductor industry segments, there is no such link in assembly and test. Partnerships and portfolio appear to be the most important factors I assembly & test.

Their key trends for Assembly & test are:

None of these should be a surprise to readers of IFTLE.

Fraunhoffer Inst

In a joint presentation by the different Fraunhoffer Institutes in Germany, Andy Heinig show the following comparison of their SiO2 and polymer based processes.

They indicate that the required number of routing layers not only depending on component complexity (i.e., pin count, pitch), but also on interposer material composition ( i.e. polymer vs SiO2 based)

– Polymer-based interposers with increased width and spacing of interconnect require a minimum of 3 metal layers

– Finer L/S of SiO2-based interposers allows routing on a single metallization layer

– Different consideration for power/ground nets (larger line/space) necessary

3M

The 3M wafer support system for thinning and backside processing has been around for several years. Their standard process is shown below.

They are also developing a thermal cure adhesive that can be mechanically debonded. This eliminates the LTHC layer and the laser module. Properties are shown below.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations from the 2016 SEMI European 3D Summit that took place in January.

System Plus Consulting

System Plus Consulting showed an interesting cost comparison between AMD graphics modules with DDR5 vs HBM memory as shown below.

Also of interest is their look at the supply chain for the new AMD 2.5D module. ASE is assembling die from TSMC and Hynix on a UMC silicon interposer and mounting on an Ibiden substrate.

Also of interest is their assessment of the Hynix HBM process cost.

The Samsung 4 GB DDR4 DRAM stacks consist of 7um TSV on 67um pitch with 33um ubumps. The process uses thermocompression bonding, wafer level NCF underfill and Suss temporary bonding with Nissan (formerly TMAT) silicone underfill.

IMEC

Eric Beyne who has been active in 3DIC since its early beginnings focused on technologies that will be important for 3DIC to further penetrate the electronics industry. Beyne started out with a look at where 3D TSV technology sits as we enter 2016, namely interposers, FPGAs, graphics modules and memory stacks (shown below)

Beyne sees the TSV themselves continuing to shrink going from the standard 5 x 50um a few years ago to a 2 x 40um in the near future. This has required changes in Cu barrier layer and Cu seed dep as shown below.

He proposed the following IMEC ubump strategy:

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Sony Samsung and Omnivision are locked in a technology battle for superiority in CMOS image sensors. While Sony has the lead in stacking technology, i.e. stacking the sensor on top of the image processor and connecting them with TSVs, OmniVision and Samsung quickly adopted the same technology and gained design wins using stacked chip products.

Rumor is that Sony will be working with GlobalFoundries on chip stack CIS, instead of Samsung to avoid any conflict with Samsung who is also in the CIS business.

We recently updated the latest from Sony [see IFTLE 272] Now lets look at some of the latest activity from Omnivision and Samsung.

Omnivision CIS

We last looked in depth at Omnivision in IFTLE 199 [ see IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors…”]

The Omnivision OV13860 introduced in late 2014 is a 13 MP back side illuminated sensor with 1.3um pixels (actually larger than other 13MP sensors). It is the first Omnivision’s CIS built with stacked die technology which separates the imaging array from the image sensor processing circuits in the stacked structure. This allows for more functionality to be incorporated on the sensor die while resulting in a smaller size due to the stacking. [link].

Omnivision then announced the OV16850, a 16MP imager for smartphones. Using an 1.12um pixel and leveraging OmniVision’s stacked die technology, which captures stills and video in native 16:9 aspect ratio. This was followed by the OV23850 a 23.8 MP high resolution CIS. (images below [link]

Credit: Chipworks

Credit: Chipworks

Samsung

Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect as shown below. [link]

Credit: Chipworks

Credit: Chipworks

iPhone 6s Plus Fingerprint Sensor

The Apple iPhone 6s now has a “touch ID” fingerprint sensor embedded in the Home button.

While it is now used for unlocking the phone , it will also be used for identification purposes for Apple Pay mobile payments. It will also probably be used for other online services in the future.

The new device has the same structure and capacitive technology as the previous one, but with changes in sensor design and packaging.

The 12.5×10.9mm sensor is incorporated within a rectangular shaped housing composed of a stainless steel ring and an aluminum base. The sensor is protected by a sapphire window coated with two different materials and supported by innovative assembly of dies and flex PCB. The finger print sensor allows it to scan the fingerprint just by pushing the button. The sensor has a resolution of 10,752 pixels with a pixel density of 500ppi. It uses a capacitive touch technology to take an image of the fingerprint from the sub epidermal layers of the skin.

The new sensor has two die, a sensing die manufactured with 65nm CMOS technology and an 0.18um ASIC logic die. The new sensor is implemented with TSV (shown below) which allows a better packaging and connection to the flex connector.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the SEMI 2016 ISS meeting.

Pacific Crest

Daniel Bakshet of Pacific Crest Securities pointed to the following changes in the semiconductor industry:

– economics are becoming challenged as process complexity increases

– compute functions are shifting from local to the cloud

– PC, tablet and smartphone demand is decelerating or declining

– signs of maturation are emerging as M&A becomes a dominant theme

They use the figure below to make the point (as we have for several years in IFTLE) that moving to a lower node no longer results in lower costs.

They see less demand for advancements in local compute capability as more of the compute function is conducted in the cloud.

They project that device growth is more likely to come from lower end products and thus not likely to require leading edge chips. They actually predict a reasonably good chance that incremental wafer demand declines at the leading edge, while previous nodes thrive.

They see autonomous Vehicles and Robotics as the areas of future growth.

Micron

Micron’s presentation by Mike Sadler, VP of corporate Development focused on consolidation in the memory industry with the following interesting slide showing acquisition and partnership driven capacity growth at Micron.

Gartner

Bob Johnson of Gartner showed this nice summary of when the remaining players have announced that they will continue scaling.

SMIC

Sonny Hui of SMIC showed the following figure of the % of devices manufactured (assembled) in China.

Amkor

Ron Huemoeller focused on Amkors high density SWIFT and SLIM packaging which we have detailed previously [see IFTLE 243 Amkor Fan Out Package Platforms] with the following product positioning slide and the following expected timeline.

China’s Tsinghua group looking to buy into Global Packaging Industry

Reuters recently discussed the offers to acquire 25% stakes in ChipMos, PowrChip and SPIL by the Tsinghua group in China. [link]

The Chinese state-backed conglomerate aims to buy into the island’s technology sector as a step toward building China’s own semiconductor industry. Tsinghua made offers in quick succession late last year for a quarter each of chip testing and packaging companies Powertech Technology Inc, ChipMOS Technologies Inc and Siliconware Precision Industries Co Ltd (SPIL). The company plans to inject a total of $2.6 billion into the three in exchange for stakes plus one board seat at each with no management control. The offers came after Micron Technology Inc rejected Tsinghua’s informal $23 billion takeover bid on the presumption of U.S. national security concerns.

Shareholders of Powertech and ChipMOS approved the plans in January as they seek capital to expand and survive in a global chip sector experiencing record merger and acquisition activity.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

The annual SEMI ISS (Industry Strategy symposium) meeting took place as usual in January in Half Moon Bay CA. What was different was something that IFTLE has been predicting for while: “In the future when the front end community runs out of advances they will begin to focus on assembly/packaging.” Well…the future is NOW.

Intel

Intel’s Corporate VP Babak Sabi got on the packaging bandwagon with his presentation “Maintaining the IC Scaling Edge through Packaging.”

He showed the following detail on their Altera FPGA demonstrator using their Intel EMIB technology [for technology detail see IFTLE 209 “Samsung announces TSV based DDR4; What is Intel eMIB?”]

The following is an interesting comparison of Intel’s understanding of feature size vs substrate technology.

Qualcomm

Mike Campbell of Qualcomm focused on “module and 3D packaging as the new integration path for semiconductors.”

Showing the following example for future SiP heterogeneous integration in a 2.5D format and the required enabling technologies.

SEMI

Dan Tracy – Dir of SEMIs Industry research group also focused in packaging in his presentation “It’s All About Packaging—In this Materials World That We are Dealing With” using materials supplied by TechSearch Inc.

Looking first at materials supplier consolidation:

Mobil products are certainly the driver for packaging.

He offered the following comments for individual markets:

Mold Compounds

– $1.2B market size

– stable Japanese supply base

– focus on warpage control, CTE, low moisture, low ionics

– molded underfill (MUF) for CU pillar FC

– high TC and high V apps emerging

Underfill

– global mkt $250MM

– currently 30+ suppliers [note from IFTLE so this is ripe for consolidation]

– new resins and fillers for fine pitch requirements

– No flow applied prior to chip placement – both liquid and film based

– use of mold compound as underfill

– increased use of board level underfill for CSP, BGA, WLPs

Wafer Level Dielectrics

– $90MM market

– requirements for new material entrants include – low temp cure, low warpage

IBS

Handle Jones of IBS presented the following projection for wafer level packaging which he claims is being driven by Apple. Note he projects that we will be approaching 1MM WLP wafers/month by 2020.

Jones also noted that with the acquisition of STATSChipPAC, JCET has become the worlds 3^rd largest OSAT.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the 2015 3D ASIP, conference we’ll look at the presentations from some of the memory suppliers and users.

Toshiba

Higashi form Toshiba discussed TSV technology for NAND flash. IFTLE did not take this to be a product announcement, but rather a technology status report.

We are all aware that flash faced major obstacles continuing normal scaling so it recently moved to monolithic stacking. NAND scaling will stop its planar 2D approach at 10 nm. All market players have developed 3D NAND technologies where the memory cells are now vertically aligned. There are many competitive monolithic transistor stacking technologies reported as shown below.

Higashi proposes that TSV flash will be required to achieve the high performance ( low latency and IOPS/W ) and low power required for performance SSD.

23Gb and 256Gb prototype chip stack is shown below.

At the 2015 Flash Memory Summit, they showed a prototype SSD using this TSV based NAND.

It was proposed that the first application may be data center servers.

Micron

During Tom Gregorich of Micron’s discussion on “Challenges in the Development and Deployment of Ultra High‐Performance 3Di DRAM Systems,” he noted that the ASIC to DRAM interface s what controls the bandwidth and power usage. The Micron HMC uses SERDES interface which is great for performance but in order to make it in consumer products they will need a new interface type to drop pricing.

AMD / Hynix

3D ASIP supporters Bryan Black of AMD and Minh Suh of Hynix updated the 3D ASIP audience on the status of Hynix HBM memory stacks and the status of the first graphics product to hit the market with TSV stacked HBM memory, the Radeon R9 Fury Series GPUs.

The interposer is made by UMC in the 300mm Fab 12 foundry (UMC) in Singapore. UMC is reported to have entered into volume production very recently (July 2015).

Hynix compared current HBM1 to the soon to be released HBM2 in the following slide.

The feel that the new generations of HBM will expand their use into more market segments.

Tezzaron

The Patti architecture and manufacturing process are quite different from the 3 main DRAM suppliers. In terms of architecture he separates not only the control functions but also has a separate layer for the I/O. This allows them to deliver “the right I/O for every need.”

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…