The recent Semi Industry Strategy Symp (ISS) occurred in Half Moon Bay CA a few weeks ago. In the past this has been a treasure trove of information on how and why the IC industry is making the moves that it does. Let’s take a look at some of the key papers from this conference.

IBM

IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Volumetric scaling will be critical to future performance enablement

– Tightly coupled modules and components

– 3D stacking and interposer integration

Casey examined the current state of interposer substrates and showed the following comparison:

 

 

 

 

 

 

 

 

Linx

Linx consultants looked at “Chemicals and Materials in Semiconductor Devices.” IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores.

 

 

 

 

 

 

 

 

 

 

Linx lists 3DIC among the major 5 challenges for the IC industry in the future.

 

Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base.

IMEC

An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm.” She offered the following roadmaps for 3D applications and TSV dimensions.

And the following CoO Analysis for their  3D process flow.

IHS

IHS examined semiconductors in the electronics value chain.  An unexpected piece of data is that consumers are spending more on hardware (HW) than content i.e.:

IBS

Our friends at Int. Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. They expect Capex decreases in 2014 (small decline)  and 2015 (large decline).

While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ½ semi sales will come from 32nm and below.

They also conclude that low power and low cost will dominate the application space for 32nm or less devices.

They continue to predict that cost/gate will no longer be a cost driver.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

 

 

Finishing up on the IEEE 3DIC meeting from Oct 2013 in San Francisco lets look at some of the remaining key papers from the conference.

Tohoku Univ – Lattice Distortions in Thinned Silicon

Professor Koyanagi and coworkers at Tohoku Univ and GINTI [ Global Integration Initiative – see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati” ]

It is accepted that to achieve compact-sized 3DIC each functional wafer should be thinned to 50μm or less. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping and local deformation in the stacked die .  Moreover, the weak mechanical strength of the extremely thin die/wafer itself has a potential concern lead to die breaking for 3DIC integration, because thin LSI chip with high density TSVs is highly fragile and more easily damaged. Hence, it is important to understand the impact of chip’s mechanical strength on device reliabilities decreasing die thickness, especially below 50μm thickness.

Koyonagi and co-workers have found that the Young`s modulus (E) of Si substrate begins to noticeably decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted which induces the Young`s modulus reduction and consequently weakens the mechanical strength.

DRAM chip of 200μm thickness were bonded to a Si interposer and thinned down to 50, 40, 30 and 20μm respectively. The measured retention characteristics of DRAM cell on these thicknesses of silicon are degraded dramatically below 50-μm thickness, i.e. the retention time of DRAM cell in 20μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip.

They assume that the band-gap energy in the thin chip is affected by the distortion of the lattice structure, hence effect on a minority carrier lifetime, consequently shortening the retention time of DRAM cell.

Fujitsu – Influence of Wafer Thinning on Backside Damage

Fujitsu is known for their ultrathin WOW process [ see  “Development of Multistack Process on  Wafer-on-Wafer (WOW)”

Ultra-thinning to 10 microns or less of Si wafer is expected to realize small TSV with low aspect ratio and coupling capacitance. Subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.

The authors acknowledge that further investigations are necessary to find “hidden residual defects” and to understand the influence of thinning on memory devices (see Tohoku discussions above).

ASE / Chiao Tung Univ – Low Temp Bonding

ASE and National Chiao Tung Univ  have studied three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, for application of 3D interconnects.

Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 C. Cu and In samples were bonded face-to-face with a bonding pressure of 1.91 MPa, followed by a heating temperature of 170 C for 50 min. Sn/In and Cu samples were bonded face-to-face with a bonding pressure of 1.91 MPa, at bonding temperature of 180 C for 50 min.

Cu/Ti samples were bonded face to face with a bonding pressure of 1.91 MPa, at a heating temperature of 180 C for 50 min.  They add that Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This last structure is especially significant if one can really do such bonding at 180 C . Their EDX investigation of the interface shows that “…apparently there is a Cu layer at the bonding interface instead of Ti layers…due to lower activation energy at the surface, Cu tends to diffuse towards the surface  …”  IFTLE feels this combination certainly deserves further study.

All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.

RTI – 10um Pitch Bonding of Hetero Materials

Matt Lueck of RTI Int described their successful demonstration of the use and reliability of Cu/Sn microbumps for the fine pitch interconnection of heterogeneous semiconductor die. InP die have been bonded to Si substrates using a 6.4 mm × 5.12 mm area array of alloyed Cu/Sn microbumps on 10 μm pitch.

A key technological challenge facing the 3D integration of heterogeneous semiconductors is the formation of high density metal interconnects between dissimilar substrates, such as compound semiconductors (CS) and Si. Due to the difference in the coefficients of thermal expansion (CTE), one can expect: 1) some misalignment between microbumps fabricated on the CS substrate and the Si substrate during bonding at an elevated temperature; and 2) bond interconnects will experience shear strain as the bonded die pair is cooled to room temperature and during any subsequent thermal excursions.

To estimate the magnitude of the misalignment, they calculated the relative change in distance between corner microbumps in a 10 μm pitch 640 × 512 array on CS die vs. Si die. Operability was determined by electrical testing of long daisy-chains of bumps.

The average channel yield was approximately 97% for both InP-Si and Si-Si die pairs translating into the array operability greater than 99.99%. The reliability of InP-Si and SI-Si die pairs was compared after 500 thermal cycles of -40 – 125 C. No significant change in yield was seen for the homogeneous Si-Si die pairs. The InP-Si die pairs that were underfilled showed a 2.8% decrease in channel yield whereas those not underfilled showed a 13.9% decrease.

They conclude that Cu/Sn micro bumps can be successfully and reliably used for integration of InP and Si die.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

Continuing our look at the 2013 GaTech Interposer Conference.

CORRECTION to IFTLE 178:

A reader has written in to indicating that the FPGA chip described in the Xilinx/SPIL paper was fabricated by TSMC not UMC .

Corning and Schott Glass

As discussed in IFTLE 170, Windsor Thomas of Corning gave a presentation entitled “The manufacturing readiness of Glass interposers” and Schott glass followed with a presentation entitled “New Ultra-thin Glass for Microelectronics.”

Since the whole LCD infrastructure is based on thin glass we certainly did not need any convincing that large panel, uniform, thin glass is available in roll and/or large panel format. Corning like Asahi Glass and Schott glass has been researching the formation of TSV (or TGV) for several years now and all appear somewhat able to form through vias down to maybe 25um. The real question is how do we than use this feedstock to get low cost glass interposers.

Though we were shown some Cu fill experiments, neither Corning nor Schott  indicated that they would enter the interposer market, did not indicate who such a partner would be and in fact stated that their discussions with the FPD industry( which they most certainly now supply) indicate that there is absolutely no interest in FPD suppliers entering the interposer supply market.

IFTLE concludes that if any of the current glass suppliers want to see glass become a interposer substrate material and more broadly a preferred packaging substrate material, they must resolve who will actually be supplying the final packaging products.

Asahi glass has attempted to fill this void with Triton, their JV with nMode [see IFTLE 141, “100GB Wide IO memory; AGC Glass Interposers; Nvidia talks stacked memory” ] Corning and Schott have not yet indicated what their proposed solutions are.

Shinko

Koizumi-san  of Shinko discussed glass substrate prototyping status. Shinko points out that glass cores can be used to mimic Si like interposers or build-up PCB substrates.

He showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core. Modeling calculations show that the glass internal stress is mainly caused by the total copper layer thickness.

Altera

John Xie of Altera examined the use of organic interconnect for stacked die integration.  Altera’s take on Interconnect resolution trends are compared below. The proposal is that organic build up (BU) substrate (dry processed) is rapidly approaching the capabilities of this film BE of line packaging on silicon.

Xie contends that high end substrate suppliers are quickly approaching 2/2 L/S and will allow direct attach to substrate and elimination of the interposer as shown below. This in turn will be a cost reduction driver. He calls this 2.1D or Ultra high density organic  interconnect. They can currently get 92um bump pitch, 8um lines and 80um vias. Their 2 year goal is to obtain 55um bump pitch, 2um lines and 20um vias.

Zeon

Zeon introduced their ultra tine dry films for Interposer RDL applications. Properties of the Zeon “cyclo olefin” polymer film are shown below.

Ushio

Ushio addressed large area litho tools for 1 – 5µm  L/S. They claim their tool is capable of 2µm L/S in a 70 x 70 sq mm area.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

Continuing our look at the 2013 GaTech Interposer Conference.

Amkor

Ron Huemoeller of Amkor addressed interposer use, defining the markets and materials options as follows:

Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role.

Silicon Interposers

Product Applications

– Gaming, HDTV, mobile tablets, computing, servers

– High end graphics cards will be the initial focus of HBM memory integration

– mobile space has the potential to follow based on availability of low cost solutions

 

Visible and Anticipated Demand

– continued low volume production of FPGAs and ASICs

– moderate volumes for high end graphics cards; HBM cost/availability driven

– high volumes for mobile; interposer cost driven at less than $0.01 per sq mm.

 

Market Longevity

– expect to have a very long life cycle

– long term continued use through deconstruction of very high end node logic to address system level cost and power related memory integration issues.

Amkor describes the silicon interposer supply chain

–  Current

– TSMC – not supplying to the industry

– UMC and Global Foundries – both have limited capacity and neither desires to be a merchant supplier

– Future

– Yet unannounced merchant supplier

– use of depreciated equipment and excess capacity

– lowers cost vs tier 1 foundries

– supply interposer without desire to bundle chip fab.

Organic Interposer Sources:

– Tier 1 Shinko, SEMCO

– 2/2 (L/S) 10/22 (via/pad); very limited sampling

– Tier 2 Kyocera

– 5/5 (L/S); 18/30 (vias/pads); very limited sampling

– Tier 3 Kinsus, Unimicron

– early development

 

GlobalFoundries

Dave McCann of GlobalFoundries examined market needs for interposers. McCann used the latest Gartner data on SoC costs to point out that development costs for a 10nm design are expected to approach $400MM.

GF again made the case that “DIS-integration” can actually offset scaling costs, i.e.:

GF indicates that the yield of high density interposers is high (“..approaching 100%”), even for  full retical sized; 4 metal layer top side, 1 metal layer backside structures.

GF has come up with the following roadmap for silicon, high density laminate and glass.

Like Amkor, GF has mapped 2.5D requirements by market space and come up with the following.

Also similar to Amkor GF pointed out that the industry needs a low cost high volume source of  high density interposers. Although showing their capabilities for interposer fabrication, interestingly they did not offer themselves up as the solution.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

Finishing up our look at the fall 2013 IMAPS meeting.

Xilinx / SIliconware

We are all aware of the Xilinx / TSMC / Amkor partnership to develop the first comemrcial 2.5D FPGA module. Since that announcment in late 2010 there have been rumors about Xilinx looking for lower cost second sources. Last summer, Siliconware (SPIL) announced the instillation of a dual damascene line for fabrication of high density interposers. [ see IFTLE 158, “2013 ConFab part 2: Amkor and Siliconware”]

At the fall IMAPS meeting Xilinx and SPIL  shared results from their progra to 2.5D 28nm FPGA program.

The high performance FPGA die (it appears manufactured by UMC)  is a 4 slice 28nmchip mounted on a 25 x 31mm 100um thick Si interposer with 45um pitch microbumps. The interposer is assembled onto a 45 x 45mm organic BGA with 180um C4 bumps. The figure below shows the structure in cross section. SPIL is manufacturing the interposer and doing the assembly.

Nanyang Univ / IME

Copper TSV exert thermo-mechanical stress on silicon due to the CTE miss match. This stress can result in variability of the device mobility and mechanical reliability issues. This can be alleviated by using a oxide liner that has a lower elastic modulus such as some of the “low-k” dielectric materials (black diamond). This would reduce the keep out zone and in addition such materials will lower the parasitic capacitance of the circuit.

These Singapore institutions looked at the use of low-k carbon doped oxides to serve as a more compliant layer TSV insulator layer due to its lower modulus (7.2 GPa vs plasma enhanced TEOS with modulus of 75GPa) . The FEA analysis shown below indicates that the low-K materials “should” lower the stress exerted by the Cu TSV on the silicon. Micro raman spectroscopy on samples verifies that the use of a  low-k liner results in less compressive stress exerted by the Cu TSV on the silicon between the TSV.

CV measurements show that the capitance is reduced by 26% ( k of peteos = 3.9 vs low-K of 2.88).

[ IFTLE sees no discussion of mechanical reliability comparisons. Since low-k is known for being very fragile, I wonder whether the TSV stress will fracture the low-k material which would show up as less stress on the silicon?]

Cannon

Cannon, normally associated with front end (FE) lithography addressed “Lithography Process Optimization for 3D and 2.5D Applications.” Cannon has developed the FPA-5510iV and FPA-5510iZ TSA steppers to support high density processes and to support implementation of 2.5 & 3D technology. A comparison of their specs is shown below.

In a typical backside manufacturing process, patterned wafers are bonded face down to a support wafer before being ground and thinned. The bonding and thinning process causes shape distortion in the wafer. Downstream processes require litho that produces patterns that can overlay such distortions with high accuracy. These systems also employ vacuum assist functions to compensate for large wafer warpage.

AT&S / EPCOS

In July 2013 AT&S (Austria) and TDK-EPCOS announced that they were cooperating on embedding technology to allow standards development and increased customer acceptance [link].

The embedding technology developed by AT&S is shown below:

The authors propose that the use of PCB real estate is lowest for an emedded component and showed the following comparison to a 3x3m die + 10 resistors packages with a QFN (45mm sq)vs flip chipped (21mm sq) vs embedded 916m sq).

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

Will Monolithic 3D IC Technology become a real competitor to 3DIC with TSV

The language of 3DIC is certainly a bit confusing. In the past I have made fun of EE Times reporters confusing BE finfet technology with TSV based 3DIC. [ see IFTLE 62 “3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues” ].

There is also confusion brewing concerning TSV based 3DIC and what can be called monolithic 3DIC.

Back end (BE) 3DIC with TSV is a parallel process where each layer or stratum is fabricated with TSV separately and subsequently joined. Monolithic 3DIC is a front end (FE), sequential process where a second layer of silicon is deposited or grown onto the first finished chip and the transistor and interconnect processes are repeated.

The issue with the sequential process has always been the temperatures required to deposit or grow a second crystalline layer of silicon on top of the IC. It is difficult to overcome the 400°C process temperature limitation imposed by the use of aluminum and copper IC interconnect  when creating the second layer of silicon and implanting and annealing the second layer of transistors.

For instance the early work of Akasaka-san at the LSI R and D Labs of Mitsubishi Electric described the basic concept of monolithic 3DIC as shown below.

Akasaka, Y., Nishimura, T., Concept and Basic Technologies for 3DIC”, IEEE Proceed., nt. Electron Device meeting, vol. 32, 1986, p. 488

It was clear nearly 30 years ago that “to fabricate 3-D IC successfully, a wafer temperature during the crystallization should be kept low enough not to destroy the device or not to change the device performance fabricated in the beneath layer”. They proposed that the key was to “to control the thermal profile in the polysilicon layer” and Akasaka proposed “…a laser or an electron beam recrystallization is thought to be a suitable method due to their effective low process temperature.”

Certainly laser annealing has come a long way since the first prognostications of Aksaka.

Zvi Or-Bach of Monolithic 3DIC is now proposing the use of smart-cut® for the formation of the second strata (and not amorphous silicon crystallization) with shielding layers to protect the first strata interconnect, as shown below.

Will these advances allow monolithic 3DIC to compete with TSV based 3DIC ? Some say that sequential 3D technology can be much less complex and expensive to implement,…maybe we will be finding out soon.

CEA-Leti recently announced an agreement with Qualcomm to assess the feasibility and the value of sequential 3D technology [link]. The program between Leti and Qualcomm reportedly “..will  allow the critical assessment of this technology in the context of practical applications, further evaluating the potential impact of this sequential 3D technology for future industrialization.”

In early January Taiwan’s National Applied Research Laboratories (NARL) said can use monolithic 3D-IC technology to make “super chips” [link].They reported that it “enables 150 layers of chips to fit in space once used to stack a mere two chips using traditional technology while helping improve signal propagation speed and provide a higher order of connectivity.”

[ IFTLE note – “150 layers is likely the silliest marketing statement  I have seen since IBM and 3M released the headline claiming “3M and IBM today announced that the two companies plan to jointly develop …. stacked silicon towers…..commercial microprocessors composed of layers of up to 100 separate chips.”[link]

At the recent IEEE  IEDM meeting Taiwan’s National Nano Device Laboratories described  fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memory. To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then thinned and planarized the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints.

Merck to Purchase AZ Electronic Materials (AZEM)

Consolidation in the microelectronics industry continued in Dec when Merck agreed to buy AZ Electronic Materials SA (AZEM) for $2.6 B [link]. Merck which controls the liquid crystal market for flat panel displays now becomes on the largest photoresist suppliers.

Intel Invests in SBA Materials

Startup Santa Barbara Materials (SBA Materials) with patented “Liquid Phase Self Assembly” technology is a nano–‐structured, advanced siloxane based approach to porous compositions that could have use in electronics, optical and energy storage arenas. IFTLE has been keeping an eye on SBA for several years since they appear to be the only SiO₂ dielectric choice for Low K IC chips that can actually deliver on sub 2.5 Dk [ see “Low-k dielectric family introduced by SBA Materials” and IFTLE 138,  “Foundry Intel; 300 mm Capacity; SBA Low-K Oxide”].

SBA has recently closed  a series B financing round which included Intel Capital as one of the investors. [link] CEO Bill Cook indicates that more will be coming on the strategic investor front “soon.”

2013 Semi Award to Xilinx

SEMI has announced that Xilinx is a recipient of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer “which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging” Liam Madden  accepted the award on behalf of the Xilinx which includes Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young.

Semi stated that “Xilinx use of a silicon interposer in their packaging of advanced FPGA represents a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die…. While the elements of redistribution layers on silicon, TSVs, and microbumps were already available [they had not been combined commercially] to provide this high bandwidth, low power packaging solution.”

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

By Phil Garrou, Contributing Editor

The 2013 IEEE IEDM was held in WDC the 2^nd week of Dec. Let’s take a look at some of the key 3DIC presentations there.

Micron

Chamdrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking. He does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

Micron proposes that “…3D integration faces several equipment and fundamental technology challenges. Bonding dicing and packaging equipment have not evolved to the same level of control capability as front end equipment technologies.” In terms of fundamental technologies they see challenges in thin wafer handling, thermal budget management and stress constraints.

New techniques will be required to test the silicon interposers with TSV and 3D devices keeping  test costs low. Ability of probe technology to handle finer pitch TSV tips, eliminate probe created scrub mark defects, and handling of thinned wafers are all viewed as significant challenges.

3D stacking also introduces intra die defects due to several processing steps, which needs to be detected and understood. Thinned die and multiple materials with different thermal expansion coefficients also create thermo-mechanical problems that can lead to test and probe issues.

TSMC

Doug Yu and the TSMC packaging group described the integration of Rf chip and array antennas using FO-WLP packaging technology.

Low dielectric constant and thick substrate are two essential factors for a wide-bandwidth patch antenna. The band for 60 GHz system in US is from 57-64 GHz, which can be achieved with mold cmpd. (MC) dielecric constant of 4 and MC thickness of MC, h1, is chosen to be 300 μm

LTCC and PCB substrate are currently used for integration of mm-wave antenna with RF chip but there are power consumption issues. The high power dissipation results from interconnect losses from chip to antenna through bumps or balls. “Antenna-on-chip” is other proposed solution to reduce the signal loss, but silicon is lossy and degrades the antenna efficiency.

The TSMC antenna structure is depicted in the figure below. It consists of two RDLs sandwiching mold compound. One is for patch radiator with the size of w × l = 890 × 1020 μm2 on the top of MC and the other one is for feeding structure embedded in the polymer on the bottom of MC as shown in the figure.

This FO-WLP array antenna integrated technology has been approved for millimeter wave system applications. High gain array antennas of 14.7 dBi, low-loss interconnects of 0.7 dB and small form factor of 10 × 10 × 0.5 mm³ can be achieved with the technology. So called “InFO-WLP” is reported to be an excellent technology for system scaling of low power millimeter wave applications on high-data-rate wireless communication.

Comparison of power savings, parasitics and system performance/size is shown below.

NC State

Paul Franzon presented on applications and design styles for 3DIC. When comparing 2.5D interposers vs 3DIC stacking . While 3DIC technology offers a substantial advantage in interconnect power efficiency and bandwidth density (effective wiring density * bit rate), their thermal flux is higher, complicating cooling. On the other hand, interposers add more cost than just TSV processing, which will keep them out of lower cost markets such as mobile. Two big advantages for interposers are that they reduce the need for power/ground feedthroughs

and physical standards. This was a significant barrier to the adoption of Wide IO but can be overcome through adoption of appropriate standards.

ASET

 

Aoki of Hitachi and collegues at ASET described activities on IC stacking using vias last / backside. Compared with the “via-middle”, the “backside-via-last TSV” can reduce process cost because TSV revealing is unnecessary. The via-last TSV process has two main advantages: first, modification of the BEOL process is unnecessary and, second, reliability concerns such as the “copper extrusion (pop-up) problem” do not arise.

ASET studied a process flow using the thinning after bonding approach. This is the process used by Tezzaron. With this method, temporary bonding is not necessary, so process cost should be reduced.

The process flow of thinning-after bonding is shown below . First, copper bumps embedded with polymer are formed on three wafers. Co-planarization of the copper/polymer surface by CMP is used to form a flat bonding surface. The step height between the copper bump and polymer was kept to below 50 nm across the entire wafer surfaces. The wafers (“LSI-wafer 1” and “Si-IP”) are then subjected to face-to-face (F2F) bonding.  Copper-copper bonding was achieved by applying hydrogen-radical cleaning. Next, the bonded wafer is subjected to wafer thinning and backside-via-last TSV processes Total-thickness variation (TTV) of the thinned wafer was kept to around 1.4 μm. A backside-via-last TSV was connected to copper/low-k interconnects. The diameter and length of the TSV were respectively 7 and 25 μm. After that the backside-via-last TSV processes, the bottom wafer “LSI wafer 2” is directly bonded to the previously bonded wafers in back-to-face (B2F) configuration. A three-layer-stacked CMOS wafer was successfully fabricated by the above-described processes.

To maximize interconnect resources, contact of the TSVs with the copper/low-k interconnects should be restricted to the lowest interconnect level possible. Cross-sectional SEM images of the stack is shown below.

Fabricated  devices exhibit high TSV yield of at least 99.2% and low TSV capacitance (about 40 fF). The transmission performance of the TSVs is 15 Tbps/W. Copper/low-k damage is reportedly negligible after via-last TSV formation. TSV-contact wiring needs only two interconnect levels. The estimated KOZ is up to 2 μm from a TSV because of low silicon stress (less than 50 MPa).

Tohku Univ.

Koyanagi’s group at Tohoku Univ reported on “Reliability Issues Related to TSVs.”

 Mechanical Stress Induced by TSVs

It is known that a compressive stress is induced in the Si substrate next to Cu-TSV. Mechanical stresses decrease as the TSV size decreases whereas they increase as the TSV spacing decreases.

Cu Pop-up from TSVs

Cu extrusion (pop-up) occurs at Cu-TSV surface when Cu-TSVs are annealed at higher temperature. Cu extrusion increases as the TSV size increases and the annealing temperature increases.

Cu Diffusion from TSVs

It is very important in order to suppress Cu diffusion from TSVs that a barrier metal layer is uniformly formed with a high step-coverage within Si trenches before Cu electroplating for Cu-TSV formation. Step-coverage of barrier metal depends on the size and aspect ratio of Si trench.

Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient.

Reliability Issues in Thinned Wafer

Cu diffusion from backside surface of the surface of Si substrate is more significantly influenced

as the Si thickness is reduced. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside.

DRAM Retention Degradation by Si Thinning

The retention characteristics of DRAM cell are degraded depending on the reduction of the chip thickness. The retention time of DRAM cell in the 20-μm thick chip is dramatically shorted by approximately 40% compared to the 50-μm thick chip.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

The 2013 IEEE IEDM was held in WDC the 2^nd week of Dec. Let’s take a look at some of the key 3DIC presentations there.

Micron

Chamdrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking. He does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

Micron proposes that “…3D integration faces several equipment and fundamental technology challenges. Bonding dicing and packaging equipment have not evolved to the same level of control capability as front end equipment technologies.” In terms of fundamental technologies they see challenges in thin wafer handling, thermal budget management and stress constraints.

New techniques will be required to test the silicon interposers with TSV and 3D devices keeping  test costs low. Ability of probe technology to handle finer pitch TSV tips, eliminate probe created scrub mark defects, and handling of thinned wafers are all viewed as significant challenges.

3D stacking also introduces intra die defects due to several processing steps, which needs to be detected and understood. Thinned die and multiple materials with different thermal expansion coefficients also create thermo-mechanical problems that can lead to test and probe issues.

TSMC

Doug Yu and the TSMC packaging group described the integration of Rf chip and array antennas using FO-WLP packaging technology.

Low dielectric constant and thick substrate are two essential factors for a wide-bandwidth patch antenna. The band for 60GHz system in US is from 57-64GHz, which can be achieved with mold cmpd. (MC) dielecric constant of 4 and MC thickness of MC, h1, is chosen to be 300μm

LTCC and PCB substrate are currently used for integration of mm-wave antenna with RF chip but there are power consumption issues. The high power dissipation results from interconnect losses from chip to antenna through bumps or balls. “Antenna-on-chip” is other proposed solution to reduce the signal loss, but silicon is lossy and degrades the antenna efficiency.

The TSMC antenna structure is depicted in the figure below. It consists of two RDLs sandwiching mold compound. One is for patch radiator with the size of w × l = 890 × 1020 μm2 on the top of MC and the other one is for feeding structure embedded in the polymer on the bottom of MC as shown in the figure.

This FO-WLP array antenna integrated technology has been approved for millimeter wave system applications. High gain array antennas of 14.7 dBi, low-loss interconnects of 0.7 dB and small form factor of 10 × 10 × 0.5 mm³ can be achieved with the technology. So called “InFO-WLP” is reported to be an excellent technology for system scaling of low power millimeter wave applications on high-data-rate wireless communication.

Comparison of power savings, parasitics and system performance/size is shown below.

NC State

Paul Franzon presented on applications and design styles for 3DIC. When comparing 2.5D interposers vs 3DIC stacking . While 3DIC technology offers a substantial advantage in interconnect power efficiency and bandwidth density (effective wiring density * bit rate), their thermal flux is higher, complicating cooling. On the other hand, interposers add more cost than just TSV processing, which will keep them out of lower cost markets such as mobile. Two big advantages for interposers are that they reduce the need for power/ground feedthroughs and physical standards. This was a significant barrier to the adoption of Wide IO but can be overcome through adoption of appropriate standards.

ASET

Aoki of Hitachi and collegues at ASET described activities on IC stacking using vias last / backside. Compared with the “via-middle,” the “backside-via-last TSV” can reduce process cost because TSV revealing is unnecessary. The via-last TSV process has two main advantages: first, modification of the BEOL process is unnecessary and, second, reliability concerns such as the “copper extrusion (pop-up) problem” do not arise.

ASET studied a process flow using the thinning after bonding approach. This is the process used by Tezzaron. With this method, temporary bonding is not necessary, so process cost should be reduced.

The process flow of thinning-after bonding is shown below. First, copper bumps embedded with polymer are formed on three wafers. Co-planarization of the copper/polymer surface by CMP is used to form a flat bonding surface. The step height between the copper bump and polymer was kept to below 50 nm across the entire wafer surfaces. The wafers (“LSI-wafer 1” and “Si-IP”) are then subjected to face-to-face (F2F) bonding.  Copper-copper bonding was achieved by applying hydrogen-radical cleaning. Next, the bonded wafer is subjected to wafer thinning and backside-via-last TSV processes Total-thickness variation (TTV) of the thinned wafer was kept to around 1.4μm. A backside-via-last TSV was connected to copper/low-k interconnects. The diameter and length of the TSV were respectively 7 and 25μm. After that the backside-via-last TSV processes, the bottom wafer “LSI wafer 2” is directly bonded to the previously bonded wafers in back-to-face (B2F) configuration. A three-layer-stacked CMOS wafer was successfully fabricated by the above-described processes.

To maximize interconnect resources, contact of the TSVs with the copper/low-k interconnects should be restricted to the lowest interconnect level possible. Cross-sectional SEM images of the stack is shown below.

Fabricated devices exhibit high TSV yield of at least 99.2% and low TSV capacitance (about 40 fF). The transmission performance of the TSVs is 15 Tbps/W. Copper/low-k damage is reportedly negligible after via-last TSV formation. TSV-contact wiring needs only two

interconnect levels. The estimated KOZ is up to 2 μm from a TSV because of low silicon stress (less than 50 MPa).

Tohku Univ.

Koyanagi’s group at Tohoku Univ reported on “Reliability Issues Related to TSVs”

 Mechanical Stress Induced by TSVs

It is known that a compressive stress is induced in the Si substrate next to Cu-TSV. Mechanical stresses decrease as the TSV size decreases whereas they increase as the TSV spacing decreases.

Cu Pop-up from TSVs

Cu extrusion (pop-up) occurs at Cu-TSV surface when Cu-TSVs are annealed at higher temperature. Cu extrusion increases as the TSV size increases and the annealing temperature increases.

Cu Diffusion from TSVs

It is very important in order to suppress Cu diffusion from TSVs that a barrier metal layer is uniformly formed with a high step-coverage within Si trenches before Cu electroplating for Cu-TSV formation. Step-coverage of barrier metal depends on the size and aspect ratio of Si trench.

Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient.

Reliability Issues in Thinned Wafer

Cu diffusion from backside surface of the surface of Si substrate is more significantly influenced

as the Si thickness is reduced. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside.

DRAM Retention Degradation by Si Thinning

The retention characteristics of DRAM cell are degraded depending on the reduction of the chip thickness. The retention time of DRAM cell in the 20-μm thick chip is dramatically shorted by approximately 40% compared to the 50-μm thick chip.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

First things first:

A message from Hannah (9) and Madeline (5):

2013 IWLPC

The 2013 IWLPC Conference was held in San Jose CA this past fall. Lets look at a few of the key packaging papers.

Rudolph Technologies

Klaus Ruhmer of Rudolph Technologies addressed the convergence of front end (FE), back end (BE) and flat panel Display technologies that is happening in order to meet the requirements of mid end packaging technologies such as 2.5D  on interposer, 3D stacked chips or very thin fan-out packages.

Back-end patterning demand is moving well into the single digit micron range (< 5μm L/S) for current high density applications. One way of reducing cost while achieving such dimensions  is to take advantage of economy of scale brought about by larger format processing.

Glass interposers for 2.5D lend themselves to diverge from traditional round wafer form-factors and move to small rectangular panel sizes used early on by the FPD industry. It is thought that processing such panels will require manufacturing techniques which have previously been utilized for Flat Panel Display manufacturing.

A cost analysis by Rudolph concludes that a 1.7X cost reduction in lithography can be achieved  by going from a 1X stepper and 300mm glass wafers to a 550 x 650mm glass panel (gen 3 LCD panel) using their panel lithography systems (all other things being equal).

Nanium

Nanium has been recently involved with establishing 300mm production of FOWLP [see IFTLE 124 “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP?”]

At the IWPC they announced the 300mm scale up of FCI’s (Flip Chip Int) Spheron fan-in WLP technology. They were able to show process capability and reliability on a 500um pitch test vehicle. They are in the process of evolving this to 350u pitch.

Deca

We have discussed the Deca adaptive patterning technology previously [see IFTLE 124 “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP?”]

At the IWLPC Boyd Rogers presented the reliability results for a  4X4mm², 0.4mm pitch 72 IO test vehicle shown below.

They are in the process of doing board level cycling and drop testing.

450mm on Hold??

Several reports including Paul Van Gerven of Bits & Chip and Charile Demergian of Semiaccurate are reporting that ASML has stopped 450mm litho development.

Van Gerven reports that customers  Intel, Samsung and TSMC do not appear to be on the same page moving forward. Demergian reports that he has heard that Intel “…was delaying 450mm production by a considerable amount.”

Starting in July, ASML minority equity investments by its largest customers. Intel was the first acquiring 15% equity ownership. Part of the deal was a contractual commitment from Intel for advance purchase orders for 450 mm and EUV development and production tools. In August, TSMC took a 5% stake in ASML ( $1.04 B) and  TSMC committed  $341 million to ASML’s R&D programs.

While it has been widely reported that volume production at 450-millimeter was scheduled to start in 2018 at the 10nm node, these recent announcements could indicate that this 2018 start date might be optimistic.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

At the IEEE 3DIC in SF in October, DARPA program manager Avi Bar Cohen presented the history of device cooling at DARPA and how it has evolved to the embedded cooling of 3D stacks.

It is well known that microprocessor frequency stopped increasing around 2005 when air cooling met its limits.

Traditional cooling involves heat rejection to a remote fluid involving thermal conduction and spreading in substrates across multiple material interfaces as shown below.

Such technology cannot:

– limit  the device “junction” temperature rise

– selectively target the thermally-critical devices

– extract heat efficiently from a 3D package or 3DIC stack

What is needed to take us to the next level is an embedded cooling solution at the die level. As we have discussed before [ see IFTLE xxx ] the DARPA ICECool program is divided into fundamental and applications phases with the goal of providing “… the fundamental thermofluid building blocks for the utilization of Intra and Interchip evaporative cooling in 3D DoD electronics.” It was envisioned that inter and/or intrachip cooling would be used to bring the cooling function directly to the site of the temperature rise on the device.

Fundamental programs addressing the cooling of 3D stacks include :

GaTech / Rockwell  – STAECOOL

IBM / Stanford – Integrated Silicon Two Phase Cooling

The 3D focused portion of the ICECool applications program has a goal of “enhancing the performance of embedded high performance computing systems through the application of chip-level heat removal with kW-level heat flux and heat density with thermal control of local submillimeter hot spots.”

At the December ICECool Applications kick off meeting in WDC Bar Cohen introduced the two 3D focused program winners GATech / Altera and IBM:

GaTech / Altera – SUPERCool which has the goal of bringing microfluidic cooling to the Altera FPGA.

IBM will also participate in this phase of the contract focusing on “bringing embedded chip cooling to a high ed server and showing the extendability to 3DIC stacks.”

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…