Iyer also listed the following packaging challenges for materials and assembly.
Iyer also listed the following packaging challenges for materials and assembly.
(2) small gap align with IR light
(3) correct alignment for offsets caused by impact of the chip touching the substrate
(4) final align during the bonding while the solder is molten.
Over 600 submitted abstracts resulted in ~300 presentations (verbal and poster) and the highest rejection rate in the industry. Key to this years conference success were Program Chair Beth Keser from Qualcomm, General Chair Wolfgang Sauter from IBM, and Assistant Program Chair Alan Huffman from RTI Int.
Even though you came to this blog to read about packaging, clearly understand that packaging is driven by IC fabrication (the front-end) and that will never change.
IC fabricators make their big profits on the leading edge node, not on the older, more available nodes.
New materials are introduced on the leading edge, and once these processes are locked down (qualified), they are very hard to change. This is why equipment suppliers and materials vendors have always spent much of their hard-earned profits on trying to get qualified into the next generation node products.
Everyone reading this blog understands the “Moore’s Law Coming to an End” arguments. Exactly when it will happen is, to me, less relevant than the fact that it is happening or has already happened for many mid-tier IC fabricators.
In the latest issue of Future Fab Int Singapores IME updates their 2.5D through-silicon interposer (TSI) technology development [link]
GQ Lo, deputy Director Director of Research, and his 3D group point out that "3D IC…is confronting bottlenecks, such as tools for designing optimal 3D systems and thermal solutions for 3D ICs" and that "2.5D through-silicon interposer (TSI) technology is gaining momentum, both in the foundry and the outsourced semiconductor assembly and test (OSAT) universe."
They state that interposer technology provides easier fabrication, alleviates 3D thermal bottlenecks and supports the fabrication of heterogeneous integration. They demonstrate the fabrication and characterization of a 2.67 x 4.3 cm2 interposer on a 300 mm processing line. Processor + memory integration is an ideal 2.5D application since "dies can be heterogeneous (e.g., logic and memory) and can belong to different technology nodes (e.g., 28nm for logic and 40nm for memory, or 130 nm for BiCMOS chips."
The TSV (12 µm x 100 µm ) were Bosch etched into a 300mm wafer. TEOS oxide was deposited to isolate the TSV from the silicon substrate; Ti / Cu sputtered as a barrier metal and copper seed. Copper was electroplated, and overburden removed by CMP after copper anneal. Three single-damascene processes were applied to form frontside M1, via and M2 on top of the TSV.
ZoneBOND technology was used for wafer temporary bonding and de-bonding. TSV wafer was back-ground to near TSV depth, the remaining silicon substrate was etched to expose the TSV from the wafer backside and low temp dielectric films deposited and CMP’ed. Back side barrier metal and Cu seed were sputtered on the back side dielectric, and the RDL was plated up, patterned and bumped.
The cross-section of TSV and FS metal is shown below.
The leakage between four TSVs with connection pad to silicon substrate (measured TSV good dies after C-V characterization) is less than 1 pA for a voltage range 0-100 V, suggesting satisfactory isolation between the TSV and the silicon substrate.
The yield of the front side M1-TSV-BS RDL chain and front side M2-via-M1-TSV-BS RDL chain were 90 percent and 85 percent, respectively.
Resistance of the TSV and backside RDL (line/space 10/10 µm) are shown below:

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.
They further report that Samsung, which produces APs for the existing iPhones, will still manufacture chips for the upcoming model scheduled to be released in the second half of 2013.
As shown below ASE remains No. 1, with revenue of $4.4B with packaging accounting for about 80 percent of the company’s total assembly/test/materials revenue.
Powertech Technology (PTI) at $1.4B is differentiated from the others in that the majority of its revenue comes from servicing the memory segment of the semiconductor market.
As shown below Taiwan currently controls nearly 50 percent of this market, with he next largest players, USA, Japan and Singapore far behind at about 10 percent each.
"Volta is going to solve one of the biggest challenges facing GPUs today, which is access to memory bandwidth," Huang told the attendees.
Personnel Changes in Taiwan
Yole Developpement’s Amandine Pizzagalli has just issued a report "Glass Substrates for Semiconductor manufacturing," where she has examined the potential applications for glass in wafer level packaging and reported on the current and projected market size. A sample of the report can be found here [link]. The functions that were examined include: carriers for thinning in 2.5/3D; capping layers for CMOS image sensors, wafer level optics, structural substrates and wafer level capping.
Twenty-five years after Ronald Regan made his famous demand in Berlin "Tear down this wall," Micron, Samsung and early hybrid memory cube consortium members promised to tear down the memory wall [ see IFTLE 38, "IFTLE 38 of Memory Cubes and IvyBridges – more 3D and TSV"], which was viewed as holding up the progress of future microelectronic products.
Since recent IFTLE reports have indicated that delays in 2.5/3D commercialization have been due to a lack of TSV memory stacks (or at least TSV memory stacks at the right cost point) [see IFTLE 140 "Important Apple Rumors; Xilinx not Deserting 2.5D;Book to Bill Improving"], we thought it was appropriate to take a look at the current status of HMC. Updates on their progress can be found here [link].
ARM, HP, and SK Hynix joined former members including Micron, Samsung, Altera, IBM, Microsoft, AMD, Fujitsu, ST Micro, Marvell and Xilinx in June 2012.
2012 Top 10 Semiconductor Vendors
2012 Materials Market
Semi just reported that the global semiconductor materials market decreased 2 percent in 2012 to $47.11B the first decline in three years. Packaging materials exceeded wafer fabrication materials for the first time ever $23.74B vs $23.38B.
For the third year in a row, Taiwan is the largest consumer of semiconductor materials due to its large foundry and advanced packaging base. Materials markets in China and South Korea also experienced increases. The materials market in Japan contracted 7 percent, with markets also contracting in Europe and North America.
For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.