ST Ericsson / CEA Leti / Cadence
One of the best received presentations of the conference was “A Three-Layers 3D-IC Stack including Wide IO and a 3D NoC – a Practical Design Perspective –“ by Pascal Vivet, and Vincent Guérin. Going well past their allotted time during the scheduled presentation, they were brought back ( by yours truly) after the session ended to answer questions for a further 45 minutes. While some of the presentation was beyond the capability of the management and process development audience, the importance of the contribution was crystal clear to everyone.


 “Wioming” is the first application processor SOC integrated with a Wide I/O memory interface which should enable superior graphics and CPU performance in smartphones and tablets. It  is a high speed CMOS, TSV middle process with:
– multicore CPU backbone
– 4 wide IO memory controllers. Belived to be the first implementation of the JEDEC wide IO standard.
– 3D asynchronous network on chip (NoC) for logic on logic stacking


Scheduled for build are:

Research Triangle Institutes 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the “3D conference circuit” for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7^th 3D ASIP in Burlingame CA a few weeks ago, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.

Much of the “buzz” at this years meeting certainly centered around the presentation by TSMCs Doug Yu a regular attendee of this meeting. Yu repeated the case he had made earlier at  the  Georgia Tech Interposer Conference [see IFTLE 80, “GIT @ GIT” ], for the pure foundry model for 2.5 and 3DIC,

Certainly with their customer Xilinx being first to enter the market with their 2.5D based Virtex 2000T FPGA, TSMC appears ahead of the rest of the foundries in this regard. Currently, TSMC is manufacturing the Xilinx chips and manufacturing and bumping the Xilinx interposer. Xilinx is using Amkor to assemble the FPGA chips on the interposer and the interposer onto a BGA package.  Since the interposers are using 65 nm dual damascene processing for the multiple layers of RDL, in reality this is something that  the assembly houses currently aren’t equipped to handle. More on that below.

Well, all the ballots have been cast. The winner of our contest was determined by who could correctly identify the most  faces that they had seen previously in the pages of  PFTLE/IFTLE â??¦and the winner is…… Dr. Beth Kesser of Qualcomm who correctly identified 38 .

Dr Kesser was shipped MRS volume 970 "Enabling Technologies for 3D Integration" edited by Bower, Garrou, Ramm and Takahashi. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s interests include developing materials and packaging technologies for the semiconductor industry, which has resulted in 7 patents, 5 patents pending, and over 33 publications in this area. Currently, Beth is the Wafer Level Packaging Product and Technology Manager at Qualcomm in San Diego. Also, Beth is the Assistant Program Chair of the 62nd ECTC to be held in San Diego, CA in May 2012 and was just elected to the IEEE CPMT Board of Governors. 

 The correct names and affiliations are shown below:

In early December the Orange County chapter of IEEE CPMT held a 1 day workshop entitled "3D Integrated Circuits: Technologies Enabling the Revolution," which included presentations by Xilinx, IMEC, Mentor Graphics, FCI, Microelectronic Consultants of NC, STATSChipPAC, Henkel, EPWorks and Apache (Ansys). The General Chair was Larry Williams from Ansys and the technical chairs were Don Frye from Henkel, Bob Warren from Conexent and Sam Karikalan from Broadcom. In the true spirit of information sharing, the intentionally low fee of $40 drew over 200 attendees for the event.

Eric Beyne of IMEC took a look at 3D challenges and progress. The standard IMEC TSV are 5 x 50um for 3D stacking moving in the future to 3 x 50 and for 10 x 100 for 2.5D interposers.

Beyne notes that nearly all options for debonding from carrier wafers are moving to RT solutions. The previously well accepted slide debonding has a small process window and is difficult with bumps on the glued interface. Brewer Science in conjunction with EVG and Suss Microtech are now promoting the Zonebond process which uses a RT release process.

As a cost reduction option, IMEC is studying the elimination of the CMP process for wafer thinning to 2um TTV on 300mm wafer down to 50um thickness. Beyne favors laminated WUF (wafer level underfilling) vs NUF (no flow underfill pre applied to the substrate) commenting that "Probably lamination is the way to go since it covers the fragile ubumps with UF before the assembly process so it’s better to handle." In addition one achieves lower surface topography using WUF.
Ted Tessier, CTO of Flip Chip Int (FCI) addressed their embedded die packaging JV with Fujikura. Fujikura’s “WABE” technology (Wafer And Board Level Device Embedded technology) involves stacking and lamination of multiple layers of Cu/PI printed circuit layers around embedded, thinned die and passive components and via filling with conductive paste. Packages can be fabricated in either a face up or face down orientation with backside thermal via options available for improved thermal performance. Multiple die and passive components can be integrated at die spacing as tight as 100um. Passive components can be embedded as well. Processing panel size is currently 250 x 350mm.

Low Temperature (175C deposition ) SiN Barrier is in 300mm production on CMOS image sensor. It is reportedly a dense film with <100MPa residual stress and excellent adhesion and electrical properties. Low Temperature PE-TEOS SiO2 is deposited at 175C with low leakage and high breakdown voltage. Etch and deposition are available on one or multiple platforms.

Coming up next — an extensive review of the RTI 3D ASIP Conference………

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………….

My Christmas and New Years time off was great; hope yours was too. Hannah and Madeline got their letters of to Santa and I had a great Texas Christmas with the grandaughters.

…and now back to 2011 conference coverage…

2011 IEDM

3DIC presentations at the recent IEEE IEDM Conference focused on potential reliability concerns.

ST Micro / Leti reported on two potential reliability issues for direct bond copper — namely stress induced voiding and electromigration. Electromigration (EM) and stress-induced voiding (SIV) testing was performed on bonded daisy chains to investigate the reliability of the structures. Test vehicles were wafers bonded at room temperature, atmospheric pressure, and ambient air and then annealed at 200°C or 400°C to strengthen the bonding.

In some NIST-type devices, they observed voids at the cathode side and copper extrusion next to the anode pads after 200°C post-bonding anneal and exposure to 325°-350°C and 3-3.5 MA/cm². Time-to-failure (TTF) is defined as a 10% resistance variation. They make arguments to support the conclusion that the Cu-TiN interface appears to be the dominant pathway for EM — not the Cu-Cu bonded interface as might be expected. On some tested die they observed voids and copper extrusion on both opposite sides of the daisy chain showing that the structure acts as one continuous interconnect without interface separation between copper lines on the two bonded levels. In standard copper interconnects and vias chains, each copper line is separated by the metallic barrier between the line and the vias.

SIV testing of the daisy chains interconnected by direct copper bonding process after 400°C anneal and thermal stressing at 175°C-200°C and a current of 1mA for 2000hrs showed no degradation, i.e. less than 5% resistance change for all the tested samples.

They conclude that: "Direct copper bonding does not impact on the failure mechanisms concerning Cu interconnect reliability."

Koyanagi-san and his group at Tohoku University reported on their studies on W / Cu hybrid TSVs. They propose that high-density 3D-LSI die requires more than 104-105 μbumps and TSVs per chip and die thickness of <10μm with near zero remnant stress. Due to this, W TSVs may outperform Cu TSVs not only due to their ability to form sub-micron vias, but also since W does not diffuse in silicon the way Cu does, and leaves very minimum stress in active Si owing to smaller difference in CTE between W and Si. Therefore, W-TSV is preferable for high-density and high-speed TSVs with small diameter and small capacitance for signal lines.

However, W-TSV is not as suitable for power/ground (GND) lines because of its higher resistance. Cu-TSV with larger diameter and lower resistance should be employed for TSVs for power/GND lines. Cu-TSVs with larger diameter are also more preferable to suppress Cu diffusion since a barrier metal such as Ta can be conformally and uniformly formed into deep trench for TSV which effectively suppresses Cu diffusion. One can also suppress the influences of Cu diffusion on device characteristics by placing Cu-TSVs for power/GND lines apart from the active areas. Thus, the Tohoku group proposes a high-density 3D-LSI using W/Cu hybrid TSVs.

μ-Raman spectroscopy revealed that mechanical stresses increase with an increase in TSV diameter for both Cu- and W-TSV. They conclude that Cu-TSV with the size of <10μm and W-TSV with the size of <1μm leave only compressive stress in the TSV spacing region when the TSV pitch was smaller than twice of TSV size. It is important to increase the TSV pitch to larger than 2�? the TSV size to avoid peeling (inside the via), extrusion of the via metals, and cracking of the LSI die. Residual stress in thinned die changes from compressive stress for the die/wafer thickness of >100μm to tensile for thicknesses <30μm. They warn that "tensile stress leads to die-cracking due to weakening of Si-Si bond, which is a threatening issue in 3D-LSIs."

Farooq of IBM detailed their reliability studies (thermal cycling >500 cycles) and thermal stress (>275°C for 1500 hr) on 3D modules built by integrating Cu TSVs with high-k/metal gate and embedded DRAM.

They found no degradation of TSV or BEOL structures, and show that there is no significant impact on device characteristics from TSV processing and/or proximity.

TSVs were integrated at fatwire (upper metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD), built on SOI and bulk Si wafers. TSV of <100μm depth were etched with near vertical sidewalls at a minimum pitch of 50μm. An example of this is shown below.

TSV and BEOL structures did not degrade after 500 thermal cycles (-65°C-150°C), and no change in either the leakage or the wiring resistance was observed. Structures consisting of wiring and via chains above and near the TSV also showed no degradation after thermal cycling. Wafers baked at 175°C-275°C for 1500hrs showed no voiding or delamination occurred near TSVs. Frontside and backside wiring levels on a thinned wafer were connected with TSVs to create chains of 3000 links; the chains showed no change in resistance after 500 thermal cycles.

TSV insulator breakdown voltages of 250V-300V were observed.

They observed that significant shifts in device characteristics were possible for some processing conditions, in particular "FET Vt was shifted under certain etch conditions" but optimizing the etch process minimized this impact. In general, they concluded: "With optimized design and processing, stress fields associated with TSVs are significantly lower than those required for strain engineering of the devices, and are not expected to shift device characteristics."

More detail is available here [link].

Honeywell and Tezzaron to build rad hard 3D-ICs

Honeywell Microelectronics and Tezzaron Semiconductor have announced that they will be working together to produce radiation-hardened 3D integrated circuits. Honeywell’s S150 process will use Tezzaron’s 3D stacking to greatly increase circuit density without migrating to a smaller node. The resulting three-dimensional integrated circuits (3D-ICs) are also expected to use much less power than their 2D counterparts. Tezzaron CTO Bob Patti commented: "Memory can now be integrated vertically rather than embedded in the logic die. The current practical limit is around 32 Megabits, but 3D could put as much as 4 Gigabits of high-quality DRAM onto a single rad hard chip."

Tezzaron also announced a research collaboration agreement with the A*STAR Institute of Microelectronics (IME). The two organizations will improve and refine the design and manufacture of silicon interposers and work to standardize the process, flows, and process design kits (PDKs). Initial early production devices are already in development, based on IME’s TSI (through silicon interposer) technology and incorporating 3D-ICs from Tezzaron. Fabrication will be completed in IME’s state-of-the-art 300mm R&D fab. The resulting TSI technology from the collaboration will form the foundation for the TSI Consortium driven by IME, to be launched in early 2012.

IME and Tezzaron have a history of cooperation dating back to 2001, when IME provided its copper line technologies to Tezzaron for their wafer stacking endeavors.

LED testing update

We are now 4+ months into our lightbulb testing and I am happy to report that both bulbs (LED and CFL) continue to burn bright — as well they should, since you will recall the average life of an incandescent is ~1 year. [ see IFTLE 63, "Bidding adieu to Lester Lightbulb."

I have come across an interesting article which tries to explain the new light bulb test protocols and adds to what I tried to explain [link].

The winner of the contest will be announced next week — along with the answers to who all those people were!

For all the latest in 3DIC technology and advanced packaging stay linked to IFTLE……….

Continuing our coverage of the 2011 Global Interposer Conference at Georgia Tech:

Jerome Baron — Yole Développment

Baron reviewed the status of interposer applications, markets, players and costs. Several of the following speakers would tout the potential of glass as an interposer substrate material due to its perceived lower cost position, outstanding Rf performance, and its ability to be fabricated in large format. Baron compared and contrasted glass and silicon based interposers in the chart below. Henry Utsunomiya, president of Interconnect Technologies Inc., later predicted that glass interposers would be used for FC — CPU and GPU starting in 2013.

Glass producers in the audience such as Corning Glass and Asahi Glass indicated that they were actively pursuing glass interposer technology as part of the GaTech consortium program. Christian Nopper, R&D director of ST Micro-Tours, indicated that glass substrates are already being used for their Rf IPADS technology [Integrated Passive and Active Devices].

Yole concluded that panel size processing will be mandatory for 2.5D interposers to be broadly adopted in the packaging landscape.

Rao Tummala — GaTech

Rao Tummala, founding director of the GIT Packaging Research Center, laid out the case for the GIT Interposer consortium. They are studying both silicon and glass interposers and view their low-cost large-panel size solutions as eventual replacements for the BGA packages currently supporting the interposer and chips. Their low-cost silicon solution is linked to the use of polysilicon vs. crystalline Si wafers.

In his presentation on the electrical issues of interposers, GIT’s Madhaven Swaminathan pointed out that glass has lower insertion loss and a higher level of insulation than CMOS grade silicon, but glass has return path discontinuities so the insertion loss can be much higher than silicon. Looking at eye diagrams for glass and silicon, they actually concluded that silicon is the best.

Swaminathan concludes:

Si interposer
– Insertion loss is higher, but there are workarounds;
– Crosstalk can be a killer;
– Better thermal performance spreads the heat and reduces cross talk;
– Better power delivery

Glass interposer
– Insertion loss is low;
– Crosstalk is low;
– Localized heating is a problem;
– Power delivery could be challenging

Nanhoom Kim of Xilinx pointed out that there are several physical limitations imposed on the interposer due to cost, manufacturability, and reliability.

Kim also showed that when it comes to electrical performance, thicker oxide, shorter TSV, and smaller diameter are better.

Choon Lee, head of corporate technology for Amkor, reminded us that all DRAM is not equal. 4Gb DRAM DIMM for servers costs ~$250 whereas 4Gb DRAM for a PC is ~$20 — quite a difference. It’s clear why stacked memory is first headed for server applications!

Kai Zoschchke from Fraunhofer IZM provided this convenient plot of TSV resistance vs. aspect ratio:

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……….

Last week to enter the IFTLE contest! See IFTLE #78 for details.

Next week: Update on 3D activities at the 2011 IEEE IEDM.

The inaugural Global Interposer Technology Workshop (GIT) was recently held on the campus of GIT (Georgia Institute of Technology). While we usually report on conferences based on numbers of attendees and presentations, Karen May, GaTech coordinator of the conference, had a much more interesting measuring stick — reporting that the 138 attendees consumed 106 gallons of coffee, 83 pounds of pasta, and 12 dozen ice cream sandwiches. Over the next few blogs I will try to update you on what was presented and what was said. Several of the presenters (it will be obvious which ones) did not want their slides released, so in those instances I will be going from my handwritten notes.

While every conference even remotely linked to microelectronics feels pressure to have at least one session dealing with 3D integration, this workshop was started, and appears to be unique, in that it’s focus is solely on 2.5D i.e. interposers.

Row 2 (L-R): Swaminathan (GIT), Nopper (ST Micro), Sukumaran (GIT), Franzon (NC State), Huemoeller (Amkor), Matthias (EVG), Salmon (Semi), Kumbhat (GIT), Dunne (TI) ; Row 1 (L-R): Kitaoka (AGC), Ramalingam (Xilinx), Garrou (Assist Chair), Tummala (Chair), Dunne (TI)

Suresh Ramalingam — Xilinx

Certainly the highlight of the conference was Xilinx due to their highly publicized announcements on their Virtex 7 2000T FPGA, which uses a 21mm x 26 mm TSV interposer, which they have been sampling since September, and will have in full production in 2012. For details on the previous Xilinx announcements see [IFTLE 73, "Xilinx shows 2.5D Virtex 7 at IMAPS 2011" and IFTLE 23, "Xilinx 28nm multidie FPGA…"]. TSMC is fabricating the chip and the interposer, Amkor is bumping the chip and assembling the FPGA slices on the interposer, and Ibiden is fabricating the package substrate. Ramalingam emphasized that the interposer solution was necessary (vs. full 3D stacking) to insure proper thermal performance.

Increasing demand for FPGA capacity is reportedly coming from:

– Wired communications
– Image and video processing
– ASIC prototyping, emulation and replacement

All applications are constrained by the devices overall power budget and thermal concerns.

Full reliability qualifications are almost complete.

Future products are expected to be heterogeneous combinations such as the FPGA slices + SERDES chips shown below.

Doug Yu — TSMC

If the highlight was Xilinx, then the headline was TSMC, which concerning 3D and 2.5D has been very careful about what they say and how they are saying it — thus the comments made by Yu at this meeting drew great attention. Yu, Sr Director of Integrated Interconnects and Packaging at TSMC had some significant comments on 2.5D interposer supply chain developments. While there have been many recent proposals for how module fabrication tasks would be divided between foundries, IDMs, OSATs, and possible 3rd-party interposer suppliers, Yu proposed that for now, the interposers should be built completely by one party to define clear ownership and an efficient route to cost and yield improvements. Yu proposes that the foundries which can leverage their Cu processing capability, offer no customer competition (vs. IDMs), and have the design support capabilities would be the natural source for interposers. Furthermore, at several points during the two-day meeting, Yu reiterated that this is TSMC’s plan. However, you should also know that rumors in the audience indicate that TSMC is currently only engaging selected 1st-tier customers with their interposer technology, which should be no surprise. When asked when TSMC would be releasing their 2.5D ground rules, Yu indicated that TSMC does not release their ground rules for any of their processes except to their partner/customers.

While everyone knows that TSMC is engaged with Xilinx on bringing their FPGA product to commercialization, it was of great interest to see Yu commenting that they were also working on mixed-chip solutions (like the memory + logic depicted below ) using interposers with 10um x 100um TSV).

Bryan Black — AMD

Byran Black, CTO of AMD, indicated that AMD is taking a "very broad view of TSV and stacking" and that the industry "will stagnate if we don’t get 3D." While Black claims that AMD has been involved in 3D for more than five years, he added that they are "intentionally not talking about what we’re doing."

Most of us remember Black from his days at Intel. In the early 2000’s he was already publishing seminal 3D papers including "3D Processing Technology and Its Impact on iA32 Microprocessors" [Proc. IEEE Int. Conf. on Computer Design, pages 316-318, 2004]

IFTLE should note that a similar "stealth" approach was taken by Micron until its recent announcements concerning its memory cube technology — see IFTLE 74, "HMC — TheMemory Cube consortium."

The audience certainly took notice when Black stated that the "Southbridge" was probably the last AMD chip that would be impacted by scaling. He envisions that in the future chip companies will be focusing process node development on specific application functionalities. He contends this will reduce mask layers and run time and increase yield, while improving performance and reducing power requirements, area, and cost for each individual functionality. These separately fabricated functionalities would then be combined vertically and/or horizontally on an interposer to form the final circuit function.

Paul Franzon — NC State

Paul Franzon, Professor of EE at NC State and long time 3D practitioner, compared the capabilities of SoC vs. 2.5D vs. 3D, agreeing that thermal performance was the outstanding feature of 2.5D as shown below. He reiterated, as many others have, that performance is often limited by memory capacity and bandwidth.

Franzon detailed the concept of "dark silicon" where most of the chip must be in "off mode" at any given time to meet predetermined power budgets. Low-power 2.5 and 3D solutions are expected to alleviate this situation.

Franzon also concluded that stacking processor on memory would allow the processor temperature to be better controlled by attachment to the capping heat sink, but would not offer enough temperature differential to the memory underneath the processor which is in intimate contact. This differential is much better when using an interposer. [See a similar discussion by LSI in IFTLE 77, "MEPTEC 2.5, 3D and beyond."]

We’ll finish up GIT @ GIT next week and then cover IEEE IEDM and RTI ASIP — plenty of important 3D news is coming your way in the next few weeks!

Also don’t forget to enter our IFTLE contest — see IFTLE 78 for details!

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……….

When I first started writing PFTLE and now IFTLE, I never thought I would be using Bill Maher to make a point in these technology-based blogs, since he and I are as diametrically opposed as two people can get when it comes to most political positions. But, as they say, "never say never." For those of you not familiar with him, Maher is what is known in the US as a TV celebrity, which means that he has done absolutely nothing other than express his opinions. Anyway, one segment of his show that I sometimes do agree with is called "New Rules" where he shows you something being done in everyday life that makes no sense and then proposes a new rule to fix the situation.

One of my long-time peeves is the announcement of some new "breakthrough technological advance" that does not tell me what they intend on doing or how they are intending to do it. So I am proposing an IFTLE "NEW RULE": If you’re not going to tell me how you are going to do it (for whatever reason), please contain the hype.

Recent headlines concerning a startup beginning operation included: "Disruptive Approach & IP Will Revolutionize Electronic Interconnect;" "Charting a new course for the future of electronic systems, Deca has launched a breakthrough approach to creating advanced electronic interconnect solutions;" and "We can take products from design to manufacturing in minutes rather than days." While others were content to copy these headlines and pass them on to you without question, IFTLE expects significant technical backup data to justify such statements — and thus we give our "Where’s the Beef" "award" [see IFTLE 3: Finding the beef and addressing 3DIC"] to the WLP startup Deca Technologies.

Going to their Web page for further information provides little help. The tab "Find out about Deca technologies" leads to this statement: "Deca’s vision of how technology and processes can be improved addresses many of the key challenges associated with advanced packaging technology, driven by a single goal of providing breakthrough products and services. Deca delivers tangible benefits through excellence in innovation, responsiveness, and production performance, resulting in: – Rapid new product introduction, – Industry leading cycle time, – Optimized ROI." Hummmmm…where’s the beef?

The site’s "How are we changing the game" tab leads to this: "The Deca ethos strives for exponential improvements across the board through a philosophy called ’10x thinking. Through Deca, traditional wafer fab batch-based processes are giving way to a novel high speed approach. Put simply, our ’10x thinking’ ethos delivers flexible technology that saves money, reduces cycle time, and expedites the introduction of new products to market." Double-hummmm…

So what do we know for sure?

1. Deca is entering the WLP market. That would have been news in the mid 1990’s, but this is now a maturing, although admittedly still-growing industry segment.

2. Deca believes that by using "non traditional equipment" they can lower the pricing on these products. Of course, with no further explaination of what that "nontraditional equipment" is or its unique use.

3. Deca is convinced that their turnaround time will be significantly less that that currently offered. I read that as ASE, Amkor and the other OSATs. IFTLE contends that one should not brag about this until they have developed a track record for doing it.

4. IFTLE likes factual, low-hype announcements with deep technical backup. But as Dennis Miller (another US TV celebrity) says "That’s just my opinion; I could be wrong."

IFTLE wishes Deca nothing but good fortune and looks forward to reporting on what their technology is and how it is progressing in the future, when that information is eventually made public. Until then: A little less hype and a little more information, please.

$1.5M Intel grant to NC State to design low-power processors

A $1.5 million grant from the Intel Corp. will be used by Paul Franzon, lead researcher and Professor of EE and Computer Engineering at NC State University, to develop a 3D CPU with 15% to 25% better energy utilization. In addition to Franzon, the research team includes Eric Rotenberg and Rhett Davis of NC State, and Krishnendu Chakrabarty PhD. of Duke University.

One problem the participants plan to address is "how to reconcile chips that are designed and manufactured in different places to different specifications so that they can work together in three dimensions. […] We will also address questions concerning heat dissipation." Franzon added that the goal is "at least a 15% improvement in performance per unit of power, through architectural and circuit advances."

They plan to have a prototype developed by 2014, and will also be addressing "test and yield" challenges — such as how manufacturers can test individual CPU components to ensure they are functional.

PFTLE/IFTLE Contest still underway

The contest involving naming key players in 3DIC and advanced packaging that have been discussed in the last several years by PFTLE/IFTLE is still ongoing and will be open to your guesses till December 31st.

See IFTLE 78 for rules and regulations and remember to send your guesses to pgarrou/[email protected] if you want to win the MRS 3DIC book prize. Good luck to all of you!

As I said a few weeks ago, we have now entered Year 5 of Perspectives from the Leading Edge (PFTLE [link], in the now deceased Semiconductor International) plus Insights from the Leading Edge (IFTLE) that you find here every week in Solid State Technology. Both of these are due to the trust that Pete Singer, editor-in-chief, showed in me five years ago.

When I started many said it would be impossible to get enough fresh material for a weekly technical blog in 3DIC and advanced packaging. I think we have proved the naysayers wrong! I have tried to fill these blogs with the data, because we are scientists and we want to see the data. I have not made an exact count, but I would bet that there have been more than 1000 figures that have come to you in the more than 200 blogs as we enter Year 5.

I said IFTLE 78 would be something special — and I am a man of my word. First, I will review two of the most entertaining stories of the year, stories that hopefully made you laugh and will yet again. Then we will have a contest: the winner of the contest will win a copy of MRS volume 970: "Enabling Technologies for 3D Integration" edited by Bower, Garrou, Ramm and Takahashi, still in shrink wrap (photo at left). The winner will be determined by whomever can identify the largest number of people (name and current affiliation) that you have seen previously on the pages of PFTLE/IFTLE.

This is a take-home quiz so you can go back to the old blogs and check — but do it quickly! The winner will be determined as whomever sends in their email response the soonest, based on arrival date and time, at the following email address: pgarrou/[email protected]. The contest officially ends on Dec. 31st, 2011. Only responses to that email will count — responses sent to my other email accounts will be disqualified. Employees of Pennwell, Microelectronics Consultants of NC, TechSearch International, Yole Développment, or Research Triangle Institute are disqualified (but can send in their guesses if they want to). The winner will be announced in early January 2012 along with a picture and short bio. Good luck to everyone!

Now for the two most entertaining stories of 2011…

The second most entertaining story can be found in IFTLE 47, "IBM 3D Cooling, TSMC Pkging, UMC 3D Equipment, the CIS Mkt Grows." This past spring at the Hanover Fair Germany, IBM CEO Sam Palmisano presented German Chancellor Merkel with a prototype of the IBM liquid cooling 3D chip stacking project developed at IBM Research-Zurich (see below). In front of the assembled audience and press, Merkel asked Palmisano: "Did you take this from Intel?" Quick on his feet, CEO Palmisano replied, "No, ours are better."

The Number One most entertaining story was reported in IFTLE 62 "Whats in a Name?" An EE Times article reporting on information released by the Taiwan External Trade Council quoted an "anonymous source" saying that "TSMC’s projected delivery of 3-D chips matches that of Intel, the world’s biggest chip maker". Only problem is that TSMC was talking about stacked 3D chips and Intel was talking about trigate transistors (i.e., finFETs). Nothing in the story made much sense since they were trying to compare apples to oranges — as many of the subsequent commenters pointed out.

Responses to this story by the EE Times readers were harsh:

– "TSMC is referring to 3D interconnect structures using through silicon vias. This has been in existence for quite some time, at least in R&D. What intel has built is a 3d transistor. There is a lot of difference between the two. Kindly refrain from misleading people. This is wrong information. Please correct…"
– "FINFET and TSV 3D are two completely different technologies. The report is confusion and misleading by comparing these 2 technologies…"
– "I agree that this article is terribly misleading and really doesn’t make a lot of sense as it mixes apples with oranges. I don’t think the author is technically very well informed on this subject…"
– " It’s a BS article – trying to make a connection to Intel Tri Gate is nonesense and misleading…"
– "Dumb article. As others have said, Tri-Gate transistor technology is a totally different thing than TSV interconnect technology…"
– "Beating Intel to 3D" by comparing TriGate to TSV is nonsensical…"
– "Is eetimes becoming a tabloid? I am wondering about the credentials of the article writer!"
– "I agree, what a pathetic article. I’m not an EE or even close to one, but even I know exactly how wrong and stupid this article is…"

WOW. We should note that EE Times offered an apology and correction shortly thereafter.

So, time for the contest… Below you will find the faces of 49 people whose stories have filled the pages of PFTLE/IFTLE over the years. Send in your guesses as to who they are and where they are employed — and you could win the prize! Good luck everyone, and thanks for your continued readership!

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……….

Last week in Silicon Valley MEPTEC and Semi held the "2.5D, 3D and Beyond Bringing 3D Integration to the Packaging Mainstream" Conference.

Zeki Celik, principal engineer in the package design and characterization group at LSI, looked at the thermal characterization of various 2.5 and 3D package configurations. Option 3, where the logic die is not heat sinked to the lid, results in the overall highest T_{J, max}. Option 2, where the silicon interposer is between the memory and the logic die, can be heat sinked to the lid lowers the overall temperature, but equilibrates the temperature of the memory to the temp of the logic. Option 1, which is the silicon MCM-D option, is the overall best solution with the lowest memory temperature.

Marnie Mattei, senior director of TSV product development at Amkor Technology, examined assembly strategies for interposed products. Primary drivers for interposers, which are now pretty much stansdardized at 100μm thick, are shown below.

Product challenges include:

Die-die / Die-substrate joining
– Micro bump uniformity; method of join; materials

Die-die X-Y spacing
– Fillet sizes and pad metallurgy
– Process assy sequence; micro-join method & materials

Thermal / power management
– Use of lids, stiffeners & passives
– Underfill/resin bleed, adhesive compatibility
– Process assy sequence; micro-join method & materials

Warpage control
– Interposer warpage; substrate warpage
– Top die warpage — top die area density/distribution

Intermediate e-test points
– Process assembly sequence

Available assembly flows in Amkor include:

[tc=thermocompression, NCP=non conductive paste (preapplied underfill); CUF capillary underfill]

Sunil Patel, director of GlobalFoundries’ customer package technology group, looked at backside integration and global supply chain challenges for 2.5 and 3D. He sees some application segregation as follows:

GF’s perspective on supply chain options mimics many others, namely foundry-centric, OSAT-centric, and 3rd party-centric.

Although GF pointed towards many collaborations with customers, OSATs and institutes, no indication was given as to when and how to expect GF to begin volume manufacturing of 2.5 or 3D products. While others have recently proposed that GF manufacturing is imminent, IFTLE does not see this happening just yet; they are probably still a year or two away.

Subramanian S. Iyer is an IBM Fellow and chief technologist at the microelectronics division within IBM Systems & Technology Group, responsible for technology strategy and competitiveness, and functionally for embedded memory and three-dimensional integration. His presentation focused on prospects for 2.5 & 3D integration. Among his main messages:

– Scaling is getting more difficult and expensive and yielding less;
– Bandwidth and latency are at a premium;
– Power management, delivery, distribution, and dissipation are significant;
– Integrating large amounts of low latency memory is a major challenge for modern multi-core processor design;
– 3D achieves high performance and low power (AC); and
– Supply chain management will be the toughest nut to crack

Repeating a theme that Subu has shared at previous conferences, he showed the cross-section of an 11-level-metal, 32nm chip (below) to make the point that due to size miss match, sometimes vias-middle TSV must be connected at upper levels of metal and not at the lowest level as we usually draw them in our cartoons.

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