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IFTLE 56 Electromigration at the 2011 ECTC

[apologies for the formatting issues in IFTLE 55. With the move of SST to the "new platform" issues appeared when loading and editing IFTLE. Hopefully those issues are now resolved, and will never be seen again !]

We continue with our look at the major themes presented at this years ECTC Conference. This week we will look at presentations concerning Electromigration (EM).

Electromigration continues to be a topic of intense study. Several papers have reached the conclusion that copper pillar bumps are more EM resistant that normal UBM/ bump structures. Many groups are also concluding that the smaller micro bumps are also more resistant to EM.

ASE has released data from their studies on the effect of EM on RDL traces in wafer-level whip-scale packages. The first RDL structure was sputtered Ti/Al/Ti (0.2um/1.5um/0.2um) combined with a sputtered UBM: Al/Ni(V)/Cu (0.4um /0.325um /0.8um). The second RDL structure consisted of Ti/Cu/Cu (0.1um /0.2um /4, 6, or 7.5um electroplated Cu) combined with Ti/Cu/Cu UBM (0.1um /0.2um /8um electroplated Cu).

Based on Weibull characteristic lifetime plots derived from their data, ASE indicates that the maximum allowable electric currents for 100,000 h (11.4 years) continuous operation without electromigration damage for Ti/Al/Ti and Ti/Cu/Cu RDL with 25um wide RDL traces. The results indicate that Ti/Cu/Cu RDL performs better than Ti/Al/Ti RDL at low operating temperatures while features relatively shorter lifetime at high operating temperatures.

In a similar study on their eWLB package, Infineon finds that the most critical spots susceptible to EM voiding at high current loads turned out to be the terminations of RDLs with transition to the chip pad or the solder ball, respectively. The critical electron flow at the RDL/chip pad interface is the downstream direction since the current densities in the thin aluminum line are much higher compared to those in the thicker Cu RDL. The voiding occurs in the aluminum pad underneath the RDL via followed by liner punch-through. The interface between SAC solder ball and RDL shows a distinct bimodal failure behavior of which the root cause could not be identified. The upstream stress direction turned out to be the critical electron flow direction. The voiding is driven by copper migration and occurs at the very transition between RDL feeding line and solder ball, which is the location of the highest current density, defined Cu/Cu3Sn IMC boundaries and pre-existing Kirkendall voids. A significant boost in lifetime can be achieved by changing the ball pad construction (e.g. thick Cu UBM) or by means of layout optimization (RDL via size, RDL shape).

Amkor fabricated a special test vehicle to get a direct comparison of Cu Pillar EM with that of various solder bump compositions.  For solder bumps a TiW(1000A)/Cu(1500A)/Ni(2um) UBM stack was used. For Cu pillars, 55um of Cu was plated up on sputtered TiW/Cu. The Cu pillars were then plated with 20 and 40um SnAg solder to form solder caps. More than 8000 hours of testing on flip chip solder bump and Cu Pillar, revealed that Cu Pillars have the best reliability amongst the four bump metallurgies ( vs high Pb ,eutectic SnPb and SnAg ). 5 combinations of current and temperature were used to estimate the current carrying capacity of Cu-SnAg-Cu μ-bumps of 25um diameter. The Cu-SnAg-Cu micro bump structure was tested for 5500+ hours without any failures.

The EM results for the tested structures is shown below. The data shows lower EM performance for high Pb bumps compared to other bump compositions. High Pb bumps usually considered resistant to electromigration. Published data shows high Pb bump to be better performing than eutectic SnPb bumps. In this Amkor study, the failure analysis showed that the failures occurred on the substrate side with cracks occurring between the Cu-Sn intermetallics and substrate Cu pad. This study used a Cu SOP substrate finish and TiW/Cu/Ni UBM whereas previous data was based on ENIG finish on the substrate and Ti/Ni(V)/Cu UBM. The surface finish turned out to be the main reason for lower EM performance.

Cu pillar height was varied from 5 to 50um and current density distribution was determined under the pillar. Current crowding is highest with 5um thick pillar with maximum current density on the left side of bump (the side current flows in from). As the pillar height was increased, the current crowding ratio continued to reduce until the pillar height of 35um. A further increase in pillar height, however, started to increase the current crowding ratio slightly. Since lower pillar height is preferred for reducing stresses, Amkor concludes that a 35um pillar height might be optimum for both EM and mechanical reliability.

IMEC reported on their studies to compare standard NiAu/SAC  (SAC=SnAgCu) solder bumps with Cu pillar bumps in terms of their electromigration behavior. Both bump configurations were flip chipped onto package substrates with a thick Cu finish. The Cu pillar bumps, which are soldered with a thin SnAg cap do not show any significant electromigration damage and do not fail within reasonable testing times and test conditions. IMEC concludes that the rapid formation of a full intermetallic phase is believed to be the main course of the outstanding electromigration performance of the Cu pillar bumps. Standard solder bumps with Ni/Au UBM show a constant failure mechanism of micro-structural degradation through void formation at the interface of the solder and the intermetallics. This occurs for all test conditions used (150-170°C and 300-500 mA).

TSMC in two separate studies first compared the EM performance of C4 and micro bumps and then examined the EM effects of micro bumps in a 3DIC package.

1Ã??3 sq mm silicon test chips were populated with the 75-95um diameter SnAg solder bumps which are then mounted on a 12Ã??12 sq mm organic substrate. Surface finishes of both Cu SOP and ENEPIG were studied. For the micro bump EM samples, both  2Ã??3 sq mm and 3Ã??4 sq mm Si on Si stacked packages were used.

The resistance profiles of the stressed C4 bumps are distinctively different from those of the micro bumps. The early failure commonly observed in the C4 joint is not observed in the micro bump joint. The steady resistance increase in the micro bumps is dominated by IMC formation, which has much higher resistivity than that of Sn [The electrical resistance of Cu-Sn IMC is about 1.5 times more than that of pure Sn, 2.5 times more than that of pure Ni, and 10 times more than that of pure Cu.] There is no obvious void formation from EM stressing even though it has been stressed for a prolonged time with up to 6 times the current density of the C4 bumps.

TSMC concludes, however "this does not imply that the micro bump joints are immortal for EM. The failure can still occur by Cu consumption when disproportional amount of solder volume and UBM thickness is selected."

In their second paper EM effects of micro bumps in 3DIC package configurations were examined. Two structures were designed and fabricated: (1) joining of Sn-capped Cu post to ENEPIG (electroless-nickel-electroless-palladium-immersion-gold) UBM pad on silicon substrate and (2) joining of top Cu post to bottom Cu post that forms a symmetrical joint structure (shown below).

Resistance changes compared to a C4 bump are shown below.

The resistance shift profiles for both the post-on-post and the post-on-ENEPIG schemes are found to have rapid increase in the beginning and then steadily increment for the long run. TSMC correlates this to the solder wetting on Cu that allows for rapid Cu-Sn IMC formation upon EM stressing, and results in Cu continuing to diffuse for the long stressing period. The resistance change is controlled by the contact area of Cu-Sn interface. Since the solder wetting on Cu enlarges the Cu-Sn contact area, rapid IMC formation occurs. They conclude that "it is very crucial for precise control on the Ni fabricating process as Cu diffusion barrier between Cu and solder to limit the contact of Cu and Sn."

For all the latest on 3D IC Integration and Advanced Packaging stay linked to IFTLE………

IFTLE 55 ECTC Discussions on 3D Processing

Before we get started in this weeks ECTC topic, I wanted to mention that old friend John Lau from ITRI pulled me aside at the ITRI booth to show me a functional example of the interposer test vehicle that we discussed in IFTLE 52 ("3D and Adv Pkging at ICEP 2011). ITRI had several 3D IC focused presentations at this years conference (see below).
3D integration continues to receive considerable attention due to its envisioned potential to alleviate or reduce performance limitations in continued CMOS scaling
Details on 3D Processing Issues
 Effect of Etch Rate on Scalloping During Bosch Etching – ITRI
ITRI discussed their Bosch Etching process in detail. In general, the higher the etch rates the larger the scallops; for 1μm-dia TSVs, the effect of etch rate on the scallop is very small and the scalloping ranges from 57 nm to 83 nm (etch rate 1.7μm/min – 2.13μm/min); for 10μm-dia TSVs, the scalloping ranges from 107 nm to 278 nm (etch rate 3.5μm/min – 5.8μm/min), for 20μm-dia TSVs, scalloping is sizable ranging from 93 nm to 225 nm (for etch rate 4.2μm/min – 8.8μm/min); for 30μm-dia TSVs scalloping is significant, ranging from 97 nm to 258 nm (etch rate 4.6μm/min – 9.5μm/min); and for 50μm dia TSVs scallop is large ranging from 99 nm to 235 nm (etch rate 5.2μm/min – 11μm/min).
ITRI lists the following issues to be considered for high quality etching:
Impact of Slurry in Cu CMP – ITRI
ITRI discusses the minimization of dishing during the removal of thick Cu plating overburden due to filling TSVs and backside isolation oxide CMP for TSV Cu exposure. In order to obtain a minimum Cu dishing on the TSV region, proper selection of Cu slurries and a  two-step Cu polishing process was developed. The bulk of Cu is removed with the slurry of high Cu removal rate and then the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300 mm wafer. They reached the following conclusions:
1. For Cu slurry selections for the wafer front side Cu CMP for TSVs and RDLs, the slurries of high removal rate should go along with that of high passivation capability to reduce the metal dishing. Using the slurry with high Cu removal rate to remove the thick Cu overburden on the field and changing to the slurry with high Cu passivation capability to clean the remaining Cu tends to have a much less metal dishing.
2. The Cu plating performance affects the metal/oxide dishing/erosion after CMP. Minimizing metal recess or dimple right on the patterns after Cu plating is an important indicator for reducing dishing/erosion after CMP. For TSV plating, transferring from Cu recess to Cu protrusion will lead to a much smaller post-CMP metal dishing.
3. Wafer edge trimming procedure before temporary bonding and backside grinding reduces edge chipping for the subsequent processes. 0.5 mm edge trimming can eliminate the edge chipping issue for a thinned wafer.
4. For backside oxide CMP for TSV Cu exposure, low pressure  should be used to reduce edge chipping during processing.
Selection of Adhesive Materials for Temporary Bonding – ITRI
Most thin-wafer handling solutions are wafer-support-systems: the wafer to be thinned is temporarily bonded on a supporting wafer with an adhesive and thinned down to the required thickness to expose the through silicon vias TSVs. Thin-wafer handling systems can be classified by the five material solutions [Brewer Science(BSI), 3M, TOK, DuPont and Thin Materials (T-MAT),] available through equipment vendors such as EVG, Suss and TOK.
The different material vendors provide various temporary bonding and de-bonding methods which significantly influence the material selection, equipment in demand and choice of silicon vs glass carrier. De-bonding processes involve various release methods including : (a) mechanical (TMAT), (b) thermal (BSI), (c) solvent (BSI, TOK), and (d) laser (3M, DuPont). A transparent glass wafer is required to serve as the carrier for UV cure and laser release which costs more than a normal Si carrier.
ITRI has shared the following conclusions:
1. Wafer thinning and PECVD-SiO2 deposition are the most critical steps for backside processes in thin-wafer handling making it only necessary to qualify an adhesive for these two conditions.
2. Backside polymer isolation is suggested to replace the backside PECVD SiO2 step (where possible) to alleviate thin-wafer processing issues.
3. /span>No obvious change or de-lamination occurred in all the chemical resistance tests for the different adhesive options.
4. The TTV performance of composite wafers with thinner adhesive has been found to be much better than that with thicker adhesive (100μm. Good TTV control for thicker adhesive still has to be developed.
Wafer thinning and back side processing  – IMEC
 The temporary bonding approach followed by IMEC is based on Brewer Science WaferBond  HT-10.10. After the HT 10.10 layer shows an average thickness of 16.2μm and a thickness variation of about 1μm across a 300 mm wafer. The wafer is thinned down by back grinding to a thickness typically leaving 57μm Si remaining for a TSV depth of 50μm. The total thickness variation (TTV) of the thin wafer after grinding is in the range of 1.6μm across a 300 mm wafer.
After thinning, an isotropic dry recess etch process reveals the TSVs while keeping the Cu protected in the oxide liner. The presence of the oxide liner prevents Cu oxidation that could occur during subsequent steps of the process flow. Without any CMP step during nail reveal, the TSV depth variation of about 1μm across the device wafers is measured by high resolution profilometry.
After nail reveal, a thermally compatible low temperature nitride passivation layer is deposited below 200°C. This passivation layer prevents Cu diffusion through the thin wafer to the FEOL active layers when redistribution layers or microbumps are processed on the backside prior to stacking. A nitride layer was been selected over an oxide layer based on the barrier properties of the 2 materials.
Metrology and Inspection During Bonding and Thinning – IMEC
For the in-line monitoring of the 3D wafers in the bonding and thinning module IMEC has examined the SPARK platform from NandaTech which has both brightfield and darkfield inspection capabilities.
There are several key metrology and inspection (M and I) challenges that need to be solved for successful 3D stacking of dies. The most critical steps have been identified to be TSV depth control, glue layer defects and control of the grinding process.
In the TSV module the critical metrology needs are measurements of via depth during etch and also detection of voids after via fill. If there are any depth variations over the wafer it translates to TSV height variations and this can become important during the grinding procedure. This depth variation should be feed-forwarded to the grinder so that the grinding can stop at a safe distance from the TSVs.
During the bonding of the device wafer to the carrier, glue layer defects larger than a few microns become critical. If these glue layer defects are not detected pre-thinning they propagate to the device wafer. Therefore, it is equally important to have the right in-line metrology to detect defects after  bonding which would indicate the presence of glue layer defects.
 During grinding it is absolutely vital to the residual Si thickness above the TSVs so that the TSVs are not prematurely exposed. The basic idea is to use a certain wavelength which will only partially penetrate the Si layer (i.e. lambda= 650 to 750 nm penetrates 1.5μm to 3.5μm) and then scan the wafer. If there is a TSV buried deeper than 3.5μm it won’t be scattering light. A map of residual Si thickness above the TSV can be generated from the image.
A proper feed-forward and a feedback system is necessary between the TSV, Bonding  and Thinning modules to compensate for process  variations.
Wafer Level Molding for 3D Components – Samsung
Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage.
Samsung has studied material issues  optimized the wafer molding process to reduce warpage.  CTE mismatch between 50um thinned wafer and mold compounds is the primary challenge.  Test vehicles (bottom wafers, top chips) were fabricated on 300 mm wafers. A top chip of 8×8 mm2 size was designed and the bottom chip (including TSVs) was designed to a 12×12 mm2 size with 50um thickness. Before wafer molding, a supporting carrier was attached to the backside of the bottom wafer for wafer processing, backside via exposure and pad finishing. The top chips were then stacked on the wafer. After molding, the carrier wafer was detached and diced. The molded unit device’s warpage after dicing was measured by shadow moiré from room temperature to 240°C.
Molding material modulus, CTE, mold thickness and top chip thickness appear to be the parameters that drive the results. The size of the top chip was the dominant factor for warpage.  Warpage variation was mainly found at the overhang area where no top chip is present, which meant that the mold CTE mismatch was worse than inside the top chip area. Thus, a narrow overhang design is important for wafer molding.
Mold compound composition also had a strong influence on warpage as shown in the table below.
Conclusions include:
1.       Warpage decreased with increasing bottom chip thickness, and smaller chip size. This was directly related to the stresses encountered by the CTE mismatch between the mold material and silicon chip.
2.       Warpage decreased by decreasing the CTE and modulus of the mold material. Low modulus levels decreased the overall stiffness of the package, which is not desirable given that thin wafers need to be manufactured for the TSVs (usually manufactured to under 100μm depth). The minimum modulus values vary according to the packaging process and infrastructure, which is why careful selection of this value is required.
3.       Warpage levels can vary for the same mold material type depending on the filler content and resin type. By studying the effects of changing the filler content, it was found that decreasing this quantity improved warpage, as well as affecting the package reliability. The amount of shrinkage during curing of the resin also affected the stress levels in the mold material, and hence the warpage levels as well.
4.       Additional research is required to reduce warpage levels at room and high temperature to 40μm and achieve the required reliability levels. Package materials needs more investigation.
For all the latest on 3D IC and advanced packaging stay linked to IFTLE…..
We are trying the address the typo errors in this blog. Please be patient while we try to locate the cause of these errors ! 

IFTLE 54 2011 ECTC and Glass Interposers

Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.

Glass Interposers

Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:

– the ability to form ultrafine pitch TSV at high speed
– thermo-mechanical reliability of copper filled TSVs in glass
– thermal conductivity of glass (Si>glass>PWB)

Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.

TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 â???? 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a â????thin film materialâ???? (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.
 ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.
A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or â????high CTEâ???? [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦

IFTLE 54 2011 ECTC and Glass Interposers

Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.

Glass Interposers

Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:

– the ability to form ultrafine pitch TSV at high speed
– thermo-mechanical reliability of copper filled TSVs in glass
– thermal conductivity of glass (Si>glass>PWB)

Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.

TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 – 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a “thin film material” (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.
 ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.
A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or “high CTE” [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦

IFTLE 53 One Year Later?. Amkor / TI High Density Copper Pillar Bump Technology

In late June 2010 Amkor and TI announced that they had qualified and begun production of the industry’s first fine pitch copper pillar flip chip packages – shrinking bump pitch up to 300 percent compared to then current solder bump flip chip technology [see IFTLE 23, “Xilinx 28 nm Multidie FPGA, Copper Pillar Advances at Amkor â??¦”]


Very little technical detail was released at that time, presumably because of the rumored exclusivity TI was given as part of the joint development program. Full technical details were to be withheld a year till the 2011 ECTC conference, which just occurred this past week. We’ll be covering the overall ECTC technical content over the next few weeks, but I first wanted to focus on the Amkor / TI paper “Next Generation Fine Pitch Cu Pillar Technology – Enabling next generation Silicon Nodes” since we have all been waiting a year for the details which were presented by Curtis Zwenger (Amkor) and Mark Gerber (TI).

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being the primary drivers for mobile phone applications. Traditional solder or Cu Pillar interconnect pitches have been 150um to 200um for both low and high end flip chip applications. Today wafers are routinely bumped at 140 – 180 um pitch with 90 um solder balls in area array. Advanced silicon nodes create challenges to fine pitch (less than 100 um) flip chip interconnects and the corresponding substrate technology. Use of low-k dielectrics, thinner ICs, and package warpage are challenges.

Migrating from wire bond interconnects to area array flip chip requires a redistribution layer be added to the device to provide the required interconnection pattern. Fine pitch flip chip is compatible with existing in-line and staggered wire bond pad patterns, avoiding the cost for redistribution of the circuit on the die. Amkor claims that 80 percent of their internal studies on converting existing area array flip chip designs to fine pitch designs resulted in a lower cost substrate due to metal layer count reduction and/or body size reduction.

Fine Pitch Cu Pillar Test Vehicle
The qualification vehicle was a 559 bump chip on 50 um pitch and a 0.4 mm BGA array coming off the substrate ( 12 – 14 mm PoP body size).

Qualified design dimensions are shown in the figure below. Composition of the solder cap and the Pb free solder were not identified.

The primary process development challenge centered on the flip chip attach and bonding processes. For Cu Pillar flip chip with pitches less than 100um, the placement accuracy of the die to substrate is critical to help ensure a high yielding manufacturing process. Amkor found that thermal compression bonding was best suited for fine pitch copper pillar products. Thermal compression bonding, used in conjunction with a pre applied underfill (NCP = non conductive paste). The process flow is shown in the figure below.

It is important to control the height of the die in relation to the substrate. Pillar height, substrate capture pad height, and die thickness must be controlled to help ensure a stable process. For an over bonded Cu pillar die the solder cap can be squeezed out the sides of the joint causing solder shorts between the pillars.

The new fine pitch packages were put through standard JEDEC MSL L3 260 ºC un-biased package reliability tests including temperature and humidity, unbiased HAST, temperature cycle level B and high temperature storage tests as well as board-level reliability (BLR) testing (drop and temperature cycle) and biased component-level (CLR) reliability testing.


Rumors are that Amkor is adding additional fine pitch Cu Pillar capacity for TI and that the process is being transferred to TI who will be putting additional capacity in place for some of their own products. TI has indicated that they are open to licensing the fine pitch Cu pillar technology to others.


For all the latest on 3D IC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦..

IFTLE 52 3D and Adv Pkging at ICEP 2011 and reschedule of 2011 3DIC (Japan)

ICEP
The ICEP [ Int Conf on Electronic Packaging] is put on by JIEP (Japan Institute for Electronic Packaging) It is usually held in April every year during cherry blossom time in Japan. I recall that in 1998,when the meeting was known as IMC/IEMT Rao Tummala and I were in attendance. At the “gala reception” we were coerced into joining the entertainment on stage and then I, as the junior member, was further coerced to dress up in a “happy coat” which my granddaughters now know as grandpa’s samuri outfit. (see below).

At this years conference, John Lau of ITRI gave an excellent invited review on the origins, status and future prospects for 3D IC which includes a must have list of 140 references in the field including his observation that Shockley, inventor of the transistor, actually patented TSV in 1958.
Lau astutely observes “â??¦ using a passive interposer to integrate a few “bullet proofed” chips together (like a MCM) want and are used to doing. The passive interposer becomes the most effective 3D IC integrator. It could be very low cost because we don’t have to dig and fill the holes on the active die. Also we don’t have to thin and metallize the active die. Furthermore we don’t have to temporarily bond and debond a supporting wafer to the active wafer.”
In another paper Lau and his ITRI colleagues discuss the feasibility of 3D IC for system in package structures. In their test vehicle a assive interposer supports a 4 memory chip TSV stack, an electrical test chip, a thermal test chip and a mechanical test chip to measure stress and warpage . The interposer is 12.3 x 12.2 mm and 100 um thick. The TSV diameter are 10 and 15 um on 40 And 50 um pitches.
TC Chang from IRTI detailed the use of thermocompression bonding for the joining of Pb free microbumps on 20 um pitch. Solvent and plasma are used to remove the flux residue between he microgaps and a capillary underfill with 0.3 um filler (Namics) is used to fill the gaps.
NEC, Univ Tokyo and ASET reported on the formation of power regulators (buck converters) which consists of a CMOS LSI including active components and an output filter embedded in the Si interposer.
Koyanagi and co-workers at Tohoku University described their development of 5 um diameter backside TSV technology. Tohoku is located very close to the site of the Tsunami devastation so I’m sure we all wish them well as they bring their University and their 3D activities back up to speed.
To develop 5 um backside TSV the chip was supported on a glass or silicon support substrate and thinned down to 15 um by grind and CMP. ~ 1 micron SiO2 was deposited as an isolation layer / hard mask . The TSV were created with Bosch process and then lined with SiO2 (500 nm) . Etching parameters (shown below) were used to control the scallop. The bottom of the insulated TSV were opened by SiO2 etching using the thicker backside oxide layer as partially sacrificial mask for the etching.
2011 IEEE 3DIC
The IEEE 3DIC meeting which was scheduled for Tokyo this fall has been moved to Osaka in Jan 2012 due to the tsunami / nuclear disaster that Japan has been recently dealing with. The submission deadline for abstract is September 30, 2011.
For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦.

IFTLE 51 2011 IEEE IITC 3D Highlights, and IEEE ECTC OSAT Preview

The annual IITC, sponsored by the IEEE Electron Devices Society was held a few weeks ago in Dresden. Ehrenfried Zschech of the Fraunhofer , John Iacoponi of GLOBALFOUNDRIES and Takeshi Furusawa, of Renesas lled the program committee.
The conference which was instituted in the mid 1990’s was the premier show dealing with issues of on chip interconnect, especially low K. In recent years it has shifted some focus to 3D integration [ see PFTLE 37, “IITC on the 3D Integration Bandwagon” and IFTLE 10 IFTLE 10 “3D at the IEEE IITC”.

In this years conference Yann Civale from IMEC shared technical details on the “Thermal Stability of Copper Through Silicon Via Barriers during IC Processing”. The IMEC via-middle process flow results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. As you may recall this was introduced to reduce the impact of copper extrusion [ see PFTLE 125, “ 3-D IC at Ft McDowell” and IFTLE 34 “ 3D IC at the 2010 IEDM”] Thus, it is essential to determine the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. IMEC reports that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.

Paul Marchal of IMEC presented a “Technology Roadmap and Status” for 3D IC. Marchal indicates that 3DIC technology is now becoming available, that co-optimization of design and procfess technology are required and that one of the remaining hurdles remains mechanical and thermal stress.

The thermo and Thermomechanical challenges for DRAM on Logic are shown below.

Interestingly scaling of the TSV diameter will strongly reduce the KOZ (keep out zone) as shown below.

The combination of microbump and underfill has been identified as the major contributor for stress on thinned die as the shrinking underfill bends the thin die around the microbump. Agreement salso needed on exchange formats and models are required.
Projections for 2015 include:
– Silicon wafer thickness : preferably 50 um and holding due to stress and thermal issues.
– Microbump pitch : 20 um and decreasing for improved electrical specs
– SV dia / pitch : 5-3 um / 20/10 um and decreasing dia scaling to decrease KOZ, results in AR ~ 20
Armin Klumpp Peter Ramm and co workers at Fraunhofer EMFT presented their information on  “Reliability testing and Failure Analysis of 3D Integrated Systems“. Their 3D-integrated reliability test chip is a 3-level-stack with a modular layout so several types of stacked devices can be realized, numbered type 1 – 4 with basic functions of the “Bottom”, “Middle” and “Top” layers in the figure below. The larger size of the Bottom chip allows access to the measurement pads, independent of the number of stacked layers. The medium chip having TSV’s and can be tested already in the stage of thinned silicon with the appropriate metal layers on front and back side (type 1). In combination with the bottom chip daisy chains can be realized that include TSVs and assembly pads (type 3). Medium chips with no TSVs, can be tested (type 2), to be able to distinguish between TSV and assembly pad parameters. Type 2 and type 3 are available in parallel as soon as the medium chip is assembled on the bottom one. Adding the top chip forms a three level stack (type 4) with daisy chains including TSVs and two levels of assembly pads. The medium chip serves in this case as feed through for electrical signals. The top chip shortens the electrical path to form a daisy chain consisting of at least two TSVs. The chip lay-out contains several elements including Kelvin structures, DC and RF test structures, daisy chains and TSV’s with dimensions varying from 3-50 um. 3D-integrated test chips were fabricated by application of Fraunhofer EMFT´s TSV SLID technology. The applied 3D TSV process is based on inter-metallic compound (IMC) bonding and TSV formation before stacking. For reliability testing, termal cycling (-55 C° to +150 °C) was performed and additional analysis was done by cross sectioning and plasma-FIB.
ECTC Preview
Remember when we all rushed to ECTC anticipating the latest advanced packaging presentations of IBM, Intel, Bell Labs and NEC, Hitachi and Fujitsu ? Well times have changed, and over the last two decades the pendulum has swung towards the OSATS and I think it’s fair to say that Amkor, STATSChipPAC and ASE are now producing more than their share of outstanding papers at every ECTC conference.
As an example, here is the list of papers that Akor is scheduled to present next week in Orlando.
"Cu Pillar and µ-bump Electromigration Reliability Comparison with High Pb, SnPb, and SnAg Bumps" presented by Ahmer Syed

"Advanced Coreless fcBGA Package with Embedded High-Dk Thin Film Decoupling Capacitor" presented by GaWon Kim

"Next Generation Fine Pitch Cu Pillar Technology – Enabling Next Generation Silicon Nodes" presented by Curtis Zwenger and Mark Gerber of TI

"Issues in Fatigue Life Prediction Model for Underfilled Flip Chip Bump" presented by Ahmer Syed

"Crack Initiation and Growth in WLCSP Solder Joints" presented by C.J. Berry

"A Study on an Ultra Thin PoP using Through Mold Via (TMV) Technology" presented by Akito Yoshida

"Characterization of Intermetallic Compound (IMC) Growth in Cu Wire Ball Bonding on Al Pad Metallization" by SeokHo Na

Hope to see some of you next week in Orlando. For all the latest in 3D integration and advanced packaging stay linked to Insights from the Leading Edgeâ??¦â??¦..

IFTLE 50 Words of Wisdom

50 is a big round number that means IFTLE is nearly a year old here on the SST website. From the data I’ve been shown recently, we have steadily built up readership since last spring to the point that we are now getting ~10,000 readers /month to this site. â??¦â??¦.A sincere thank you for your interest.

As you know the Insights From the Leading Edge, or IFTLE as I like to call it, focuses on 3D integration and other advanced packaging technologies. We try to keep you abreast of where and when they are introduced and what kind of impact they will have on this field of Microelectronics that we have chosen to be a part of.

I just spent my 62nd birthday with my granddaughters in Houston. This gives me the opportunity to slip in another picture of the girls which I have already explained I get to do because this is my blog.

Miss Hanna (left) and Miss Madeline (right) informed me that 62 meant I was an old man. I told them that with age came experience and with experience came wisdom so they should listen to their old grandpa. They both just giggled not having a clue what I was talking about. Certainly we all get older, but do we all get wiser ? I’ll leave that as something for you to think about.
 
On my birthday I noticed that Dr Morris Chang had a few words to say in the China Post. Chang, Chairman and founder of TSMC and winner of the 2011 IEEE medal of honor, announced that TSMC is now capable of 28 nm and is focusing on 20 nm. He also announced that Moores Law would meet its demise by 2020 at which point we simply would not be shrinking transistors any more. These were strong words from a man who runs the worlds number one IC foundry. [Link] He pointed out that in the future, more attention will be paid on packaging solutions and printed wring boards which had not yet met their physical limits. For TSMC he pointed specifically to MEMS, image sensors, photovoltaics and LEDs.
At a TSMC forum April 5th in Santa Clara Chang indicated that the PC and cell phones have been the big drivers for the IC industry but that now “ a third ‘killer app. – mobile products (smart phones and tablets)” was ruling things.

Addressing 3D, Chang indicated that TSMC has poured "significant R and D" into 3-D chips using through-silicon vias (TSVs). The company calls it as a paradigm shift called "systems-level scaling," .

Looking at the 450 mm waer question he noted that "There are still a lot of challenges for 450-mm," and that TSMC “ would build a 450-mm pilot line in the 2013-2014 time frame, followed by production in 2015-2016” with “the intercept point is 20-nm”

Some might think that these concepts were put together by his underlings who are assigned to stay on top of technology, but maybe not. Chang has always been keenly interested in both the technology and the business aspects of our semiconductor industry since his early days at MIT.
My own experience with Dr Chang came about 12 years ago when I was in Taiwan introducing BCB for redistribution and bumping. We were visiting TSMC when our host informed us that the Chairman would be joining our meeting because he wanted to understand what all the of the interest in bumping and redistribution of chips was about. He personally took us out to lunch in order to have more time to absorb technical. He explained that he knew that bumping technology was being used by the mainframe players but had recently been hearing that it was moving into consumer products. A few years later, TSMC became the first foundry to put bumping capacity in place (2001). â??¦â??¦Morris Chang – without question is a wise, old man.
Intels new “3D technology”
As if we didn’t have enough trouble explaining that 3D IC technology has nothing to do with wearing glasses to watch your new TV, some reporters in the industry are now calling the Intel;tri gate transistor a “3D chip” [link] . Actually this is not something new, Intel first announced their tri-gate structure in September 2002 and indicated that they were readying it for introduction at 32 or 22 nm, which is exactly what they are doing.
This concept here is explained very nicely by Greg Crowe [link]. “Here’s the basic idea. A transistor has power flowing through it from the source end to the drain end. The presence or absence of a current is determined by the voltage level of the gate that bridges the two. The major problem with the traditional setup involves signal loss resulting from the fact that the gate only contacts the source and drain on one surface. A tri-gate transistor has three gates that make contact on three sides at once, effectively tripling the amount of surface through which electrons can travel. This produces less data leakage and uses less power than the older design.”
Intel has indicated that this will deliver a third more processing speed, and about half as much power consumption. This means that at 22 nm Intel can pack in twice as many transistors in about the same-sized chip for the same power usage, which operate a third faster – effectively giving us about 2.5X the processing power for the same power consumption.
There are those asking how this will affect the introduction of 3D IC. Only Intel knows for sure, but I can tell you that these faster ICs will be looking to access memory even faster than they do now so my guess would be that memory on logic will be needed even more.

My previous thoughts were that TSV would show up in the 22 nm Intel "ivy bridge" [see IFTLE 38, "..of Memory CUbes and Ivy Bridges…"] with both stacked memory and interposer. We will see whether that is still true.
So thanks for your continued readership and if you continue to be interesred in 3D IC integration and other advanced packaging, stay linked to IFTLE !

IFTLE 49 Mentor 3D-IC Test Strategy; GSA Memory Conf

Before we start this weeks topic, we have some corrections to offer up from IFTLE 48:

Semi and SEMATECH Lets Get it Straight

A SEMI representative got in touch to let me know that, while SEMI and some people from SEMATECH work together on 3D-IC standards, the two organizations do not have an alliance on TSV. “Both SEMI and SEMATECH are taking key leadership roles in the discussion and promotion of standards for 3D-IC technology. SEMATECH is working with SEMI on assembling standards committees and task forces. Working with SEMI, SEMATECH’s goal is to leverage standards to head-off potential show-stoppers.”

“SEMI International Standards is very involved in 3D-IC manufacturing standards. The SEMI 3DS-IC Committee was created in late 2010, and has several activities underway in three task forces. The Inspection and Metrology Task Force is measuring the properties of TSVs, the Bonded Wafer Task Force is working on parameters for bonded wafer stacks, and the Thin Wafer Handling Task Force is developing standards for transport and storage. In addition, a new task force to address trimming of device wafers and carrier wafer dimensions is expected to start work at the 3DS-IC Committee’s next meeting on Tuesday, July 12, 2011 at SEMICON West 2011. The committee is currently chaired by Applied Materials, Qualcomm, Semilab, and SEMATECH. [link][link] and [link]

They also correctly noted that “3D Interconnect Wiki: Stress Management for TSVs” (http://wiki.sematech.org/ ) and the Wiki site (http://www.semiwiki.com/forum/f2/ ) are SEMATECH not SEMI sites.

Glad you all are paying attention, thanks for the corrections and I hope that straightens it all out.

Mentor Graphics 3D-IC Test Solution

Mentor Graphics Corporation recently announced their complete Mentor test solution for 3D-IC, Tessent® v9.4 which will be released May 2011 [link].

The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.

The Tessent test solution reportedly addresses the three main challenges of 3D-IC testing:
– the need for higher KGD test quality to ensure acceptable package yield
– the ability to enable comprehensive testing of all die within a packaged stack
– the ability to test all die interconnects after packaging

KGD is addressed by:

– Support for advanced fault models, including at speed testing in addition to normal “stuck-at” and bridge testing.
– Test pattern compression, which enables higher test coverage while lowering the cost of test by reducing tester memory requirements and test time.
– Hierarchical test capability, which simplifies test development and debugging, reduces test time, and allows high coverage even for complex chips, limited by I/O pin count, routing congestion, or, in the case of 3D-ICs, inter die test paths
– Integration of automatic test pattern generation (ATPG) and built in self test (BIST) techniques to achieve highest coverage at the lowest cost.

3D-IC Test Challenges After Packaging
In 3D-IC stacks, each of the die must be re-tested after the die have been packaged to make sure they remain fully functional. Post-package test is the first opportunity to test all the TSV or interposer connections between die for proper connectivity and at-speed performance. For processor and memory stacks, the memory bus interface logic must also be tested at full speed.
Test point access is a problem because the bottom die is the only one with direct access pins. IMEC has proposed extensions to IEEE 1149.1 (which defines standard test access points0 to allow application of tests in multi-die stacks Their TSV-based 3D test architecture requires supporting methods for routing test data through the stack, and methods to re-sequence test patterns as appropriate for the extended scan chain paths. The Tessent tool suite provides support for implementing the IMEC extensions.
Tessent ATPG and BIST test products reportedly work together to minimize test development effort and to enable parallel testing to increase test throughput.
RAMBUS
At the GSA Memory Conference last month, Sharon Holt, Sr VP at Rambus reiterated the well known position that smartphone and tablet use is increasing and will overtake standard mobile phone use in 2015.

When looking at the options for mobile memory moving forward Holt proposes that the industry could continue to evolve todays technology based on low-power DDR2; switch to the newly announced wide I/O memory interface or use the Rambus designed XDR mobile memory solution.
 JEDEC has defined a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8- gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions. While Samsung and others have proposed commercialization in 2012 [see IFTLE 36, “RTI ASIP 2010 Part 2” ] and Nokia has indicated that they will see wide IO memory in production in 2013 [ see IFTLE 19, “Semicon Taiwan 3D Forum Part 2” ] Holt indicated that due to the complexity and costs, TSV-based wide I/O DRAM will probably not arrive until ”the second half of the decade’’.
SanDisk
Yoram Cedar, CTO of SanDisk took a look at flash memory.
Cedar expects to see a 5X increase in flash usage in the next 3 years :
Cedar concludes that NAND scaling will need new technologies in ~ 2014 and that “3D Read/Write Memory Will Likely Be the Successor to Floating Gate NAND Flash Over The Long Term” Note 3D here does not refer to TSV technology but rather as shown below.
Penn State
Yuan Xie, long time 3D practitioner from Penn State showed that 3D should have significant cost advantages over scaling at the 32 and 22 nodes.
What are the novel architectural designs enabled by 3D integration ?
– Latency (fast interlayer interconnect)
– Bandwidth (high number of connections bw layers)
– Heterogeneous integration
– Cost benefit
What “Killer” applications could benefit from the unique features 3D can bring ?
– High-capacity memory
– Multi/many-core ?
– Exascale computing ?
Kyowin Jin – Hynix Semiconductor
Kyowin Jin, VP of Product Planning for Hynix Semiconductor looked at the use of 3d technology in the DRAM industry. 3D TSV technology offers something to the computing, the graphics and the mobile segments of the memory industry.
Jin showed a Hynix 3D roadmap that shows prototype development for 3DS-RDIMM and for 3DS-DDR3 in 2-11 and ultra wide IO development in 2013 as shown below:
For all the latest in 3D IC and advanced packaging developments stay linked to Insights From the Leading Edgeâ??¦â??¦â??¦â??¦â??¦..

IFTLE 48 SEMATECH Addresses the Reliability Impact of Stress on 3DIC

The latest SEMATECH workshop “Design for Reliability Workshop – Stress Management for 3D ICs Using Through Silicon Vias”, in collaboration with Fraunhofer IZFP, and chaired by SEMATECHS Larry Smith, was held in March in Santa Clara. The keynote by Prof Paul Ho, U Texas,“Reliability Challenges for 3D Interconnects” served as a tutorial that outlined some of the basic incremental reliability challenges associated with the 3D technology. A presentation “Cu TSV Reliability: Modeling, Test Structures and Measurement Techniques” given by Victor Moroz of Synopsys, summarized some of the experimental work done at IMEC and presented data relating the electrical effects and stress in specific 3D structures. A paper “Thermo-Mechanical Reliability of TSV Packages”, presented by Xi Liu and Suresh Sitaraman of Georgia Tech provided an overview of the 3D state of the art work at package level. Three presentations “Design For Reliability of BEoL and 3-D TSV Structures—A Joint Effort of FEA and Innovative Experimental Techniques” presented by Juergen Auersperg of Fraunhofer, “Role of Thermo-Mechanical Modeling in 3D TSV Reliability Evaluations” by Kamal Karimanal of GLOBALFOUNDRIES, and “3D IC Reliability: A New Frontier” by Raymond Wang of ASE, demonstrated the use of various FEA approaches for modeling 3D structures. The workshop goals was to examine the mechanical stress-driven failure mechanisms, associated test vehicles, and characterization and modeling methodologies which pertain to the via- middle through-silicon-via (TSV) 3D stacking technologies.

Before I take a look at some of what was presented,  I’ll reiterate that I think readers of this blog come here for 3DIC and advanced packaging insight and part of that insight is knowing the latest spots to retrieve useful information.

We have previously discussed the SEMI/ SEMATECH alliance that is in place [ see IFTLE 33 “Micron 3D Response, SEMATECH Stds, Leti 300 mmLine” ] Semi has also been developing a Wiki site where important areas in microelectronics are to be discussed [link ] From this page you can access the 3DIC tab which leads to discussions about 3DIC. In addition SEMI /SEMATECH has now started a page [link] which covers “3D Interconnect Wiki: Stress Management for TSVs”. If you get nothing else from this blog, go to these two sites and acquaint yourself with what’s available.

Paul Ho – U Texas

Ho has examined the effect of TSV scaling on keep out zone (KOZ) and concluded that the near surface stresses degrade the carrier mobility and thus define the KOZ through the piezoresistivity effect. Defining KOZ as no more than 10% decrease in mobility :

• KOZ scales with the square of TSV diameter.

• KOZ minimized at a TSV aspect ratio less than 3
• KOZ is larger for analog devices than digital devices.

• The KOZ can be significantly reduced by using annular TSV.

Victor Moroz – Synopsys / IMEC

Synopsys / IMEC made a presentation on the characterization and modeling of 3D IC with via-middle TSV. Their studies on copper fill chemistries showed that chemistry “C” had 3X the stress of two other comparable materials. This copper had a finer grain structure and showed little to no grain growth after temp cycling.

They found no significant change in TSV C-V behavior before and after thermal cycling. When measuring the minority carrier lifetime from he transient response of a MOS capacitor they saw no significant change in TSV C-V behavior before and after thermal cycling.
After proper thermal treatment to minimize “copper pumping” (copper protrusion) they found no damage to M1 or M2 above the TSV . Examining the impact of TSV generated stress on the transistor performance they found good agreement between modeling and obtained data.

When examining the impact of Cu/Sn microbumps on N-FET logic devices of dies thinned to 25 um , they found a 40% impact on NMOS current due to he underfill that was being used to reinforce the interconnect bumps. Without underfill, no impact on current was observed. The zero stress temp was found to be ~ 160 C , i.e the curing tem of the underfill (as expected). The explanation is that the shrinking underfill bends the thin die around the Cu/Sn bump generating the observed stress.
For all the latest on 3D integration and advanced packaging stay linked to Insights From the Leading Edgeâ??¦â??¦