3D Integration

3D INTEGRATION ARTICLES



Thailand flood update from key semiconductor assembly and test companies

11/04/2011  Numerous global semiconductor suppliers maintain assembly and test operations in Thailand. Many of these facilities have been affected by the disaster. IHS iSuppli pulled together a list of those affected, and those that have thus-far escaped damage.

MEMS alternatives for miniature auto-focus cameras

11/02/2011 

Dr. Giles Humpston, Tessera, presents the free, on-demand webcast Lens Tilt in Small Auto-Focus Cameras. Dr. Humpston covers the dominant auto-focus miniature camera technology today -- VCM -- and an improved technology based on MEMS, which is being commercialized now.

Silex MEMS TSV tech licensed to Nanoshift

11/02/2011 

Silex Microsystems licensed its Silex Sil-Via through-silicon-via (TSV) packaging platform to Nanoshift for use in early development of complex MEMS products.

Invensas, Allvia ink 3D IC tie-up

11/01/2011 

Invensas has "acquired" dozens of 3D IC packaging patents from Allvia, and the two have agreed to further collaboration in the area.

3D packaging enters the mainstream: Attend the conference

11/01/2011 

2.5D, 3D and Beyond - Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D and 2.5D packaging moving from roadmap to factory production.

Xilinx FPGA boasts 6.8B transistors

10/25/2011 

Xilinx Inc. (Nasdaq:XLNX) began shipping its Virtex-7 2000T field programmable gate array (FPGA), a programmable logic device with 6.8 billion transistors: 2 million logic cells, a die-stack architecture, low power consumption, and a more flexible design than large ASICS and monolithic FPGAs.

Present at VLSI Technology and Circuits

10/24/2011 

The 2012 Symposia on VLSI Technology & Circuits, to be held in Hawaii, June 12-14 (Technology) and 13-15 (Circuits), will accept innovative, original work on microelectronics, ranging from gate stacks and advanced lithography to 3D packaging.

TSV electroplating dev team unites SVTC, Amerimade Technology, Shanghai Sinyang Semiconductor Materials

10/19/2011 

Nanotech accelerator SVTC Technologies, wet chem equipment maker Amerimade Technology, and chemicals company Shanghai Sinyang Semiconductor Materials will collaborate on electroplating processes for TSV that are production-ready for advanced packages and MEMS.

SUSS MicroTec wins thin-wafer temporary bonder order

10/18/2011 

SUSS MicroTec, in partnership with temporary bonding adhesive maker TMAT, will deliver SUSS MicroTec's new-generation high-volume temporary wafer bond tool clusters to a leading IDM.

Fraunhofer, EVG develop temporary wafer bonding for thicker die

10/11/2011 

EV Group (EVG) will work with Fraunhofer IZM's ASSID research center to develop temporary bonding/debonding technologies for thicker die structures, some as large as 600

STMicroelectronics uses TSV in high-volume MEMS devices

10/11/2011 

STMicroelectronics (NYSE:STM) has implemented through-silicon vias (TSV) in high-volume micro electro mechanical system (MEMS) devices. ST is using TSV in its smart sensors and multi-axis inertial modules.

Fraunhofer IZM's packaging center installs Altatech CVD

10/11/2011 

All Silicon System Integration Dresden (ASSID) installed an Altatech 300mm CVD tool for dielectric film deposition on advanced through silicon vias (TSV), with diameters as small as 10

Thin wafers win majority in electronics by 2016

10/06/2011 

Thanks to MEMS, 3D packaging, LEDs, power devices, and other applications, thinned wafers will be the majority of wafers in the market by 2016, according to Yole D

SEMATECH's Bryan Rice: Why it's time for a "refresh"

10/04/2011 

Bryan Rice, SEMATECH's newly appointed director of strategic initiatives, tells SST what his new job entails: what he sees as his biggest challenges, which areas will keep SEMATECH's main attention (hint: the "once and future king" of resources), and what new areas are being explored.

Rudolph wins TSV inspection systems order

10/03/2011 

Rudolph Technologies Inc. (NASDAQ:RTEC) shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) structures.

Samsung embedded memory fits 8 die in 1.4mm stack

09/29/2011 

Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.

Present on interposer technology

09/20/2011 

The first annual Global Interposer Technology Workshop at Georgia Tech will convene students, academics, researchers, and industry to share information on silicon and glass interposers for semiconductor packaging.

Xilinx, Elpida highlight SEMICON Taiwan's SiP Global Summit

09/19/2011 

Dr. Phil Garrou takes a closer look at highlights from a SiP summit at the recent SEMICON Taiwan: Xilinx FPGAs and Elpida's low-power DDR3 memory.

Advanced semiconductor package test emphasized at new BiTS Workshop

09/16/2011 

The Burn-in & Test Socket Workshop (BiTS Workshop) is changing its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs."

Multi-die face-down packaging suits existing wire bond lines

09/08/2011 

Invensas Corporation, a Tessera subsidiary, will demonstrate dual-face down implementation of its new multi-die face-down packaging technology at the Intel Developer's Forum. The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

Sponsored By:

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