09/07/2011 

Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.

09/06/2011 

Alchimer's AquiVia film-deposition technology promises to cut fill deposition times and cost even with complex through-silicon via (TSV) 3D packaging structures. The product targets TSV ramp-up at production levels, according to the company.

08/30/2011 

SEMICON Taiwan (Sept. 7-9) approaches, the island's most celebrated event for microelectronics manufacturing, coorganized by SEMI and the Taiwan External Trade Development Council (TAITRA), offers more than 60 programs and sessions and 550 exhibitors spanning the entire semiconductor value chain and related high-growth industries.

08/29/2011 

GLOBALFOUNDRIES entered into a strategic partnership with Amkor (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab-bump-probe-assembly-test steps that can be commercialized across multiple customers and end-market applications.

08/24/2011 

The SMTA will host conference events with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.

08/17/2011 

The annual Known Good Die (KGD) conference, taking place Nov. 10 in Santa Clara, CA, will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration."

08/16/2011 

The 2011 iNEMI Roadmap, published by the International Electronics Manufacturing Initiative (iNEMI), includes a new chapter on MEMS and sensors, and an expanded chapter on packaging to include substrates discussions.

08/12/2011 

SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.

08/12/2011 

Laurent Malier, CEO of Leti, described the research group's work and the outlook on fully depleted silicon on insulator (FDSOI), 3D packaging technologies, and integrated photonics on silicon.

08/10/2011 

Amkor's Ron Huemoeller shares his thoughts about two panels from SEMICON West, on 2.5D silicon interposer packaging technologies and its supply chain, and 3D packaging technology and its ecosystem.

08/04/2011 

Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC's major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.

07/28/2011 

Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.

07/26/2011 

3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.

07/26/2011 

Dr. Phil Garrou summarizes the significant commercial strides made over the past 12 months in 3D IC integration -- as defined vs. other "3D" technologies -- thanks to the promised combination of low cost and high performance.

07/25/2011 

At SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

07/21/2011 

Steve Lerner, CEO of Alchimer, discusses the company's latest suite of through silicon via (TSV) technologies, focusing on how the platform reduces costs for advanced packaging processes.

07/19/2011 

Speakers at a SEMATECH/Fraunhofer-hosted workshop at SEMICON West looked at stress management for 3D ICS using TSVs: the state of reliability testing, failure analysis techniques, and why an engineering paradigm shift is needed.

07/15/2011 

Jonathan Davis, SEMI, chats about standards development in 450mm and 3D IC, as well as the importance of collaboration, and how it is happening at SEMICON West.

07/14/2011 

Sitaram Arkalgud, director of interconnect at SEMATECH, discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. Standards are also covered.

07/13/2011  Mitsubishi Heavy Industries Ltd. (MHI) developed a fully automated 8" wafer bonding machine that bonds large-scale integration (LSI) circuits at room temperature, creating 3D ICs.