09/01/2010 

KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.

08/31/2010 

Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.

08/13/2010 

In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.

08/12/2010 

Tutorials at the October event will cover 3D packaging, future interconnects, WLP, flip chip, and more.

08/10/2010 

Yole asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on apps and timing for adoption, says TSI in its forecast for Si interposers. Both analyst forecasts are summarized.

08/03/2010 

In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real engineering world. Especially for 300mm, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV.

08/02/2010 

Henkel has extended its Wafer Backside Coating (WBC) portfolio to also include a solution for stacked-die packages. Ablestik WBC-8901UV has been designed to address the demanding requirements of multiple die stack applications for the memory market segment.

08/01/2010  Unit processes, integration schemes, and equipment are in place to enable development and pilot production of TSV technologies and all parts of the value chain do exist today at 300mm to enable integration technology qualification, end-product samples, and limited pilot production. Sesh Ramaswami, Applied Materials, Santa Clara, CA USA

08/01/2010  The potential benefits of 3D integration -- where chips are thinned, stacked and electrically connected with through-silicon vias (TSVs)

08/01/2010  As the need to integrate MEMS devices and advanced memory for sensor applications expands, work is underway to develop modules merging both mechanical and electrical devices into single, highly compact modules. Navjot Chhabra, Freescale Semiconductor, Austin, Texas, USA

08/01/2010  It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA

07/30/2010 

Package on package (PoP) stacking makes use of the vertical space available on electronics printed circuit boards (PCBs). It increases density, fitting more silicon into the same footprint. However, package stacking can be difficult, as fine pitches require placement accuracy, and taller stacks generally face reliability issues, especially if the stack is reflowed improperly. So where should PoP stacking take place?

07/30/2010 

In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.

07/28/2010 

In this video interview, Philip Garrou, microelectronics consultant and Advanced Packaging blogger, offers information on his blog, Insights from the leading edge, and summarizes reasonable roadmaps for 3D technology and TSV in particular. 2012 mainstream adoption seems too aggressive to Garrou.

07/26/2010 

Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 3: Everything about 3D & packaging was hot, with suppliers jostling to get into this next high-growth market. But are they really prepared for what awaits them?

07/23/2010 

In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.

07/23/2010 

Mark Privett, Brewer Science, says that new technologies allow use of higher temperatures as well as room-temperature processes, such as wafer de-bonding. The 3D industry is nearly ready for high-volume, yet still without industry standards.

07/22/2010 

The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. Synopsys remains a strong number one.

07/20/2010 

In this video interview from SEMICON West 2010, Walden Rhines, Mentor Graphics, discusses 3D technologies. EDA tools need to be extended to meet the needs of 3D -- parasitic extraction and timing, place-and-route, and other steps are different with 3D. The tools are evolving for the various 3D technologies. He also touches on lithography evolution.

07/13/2010 

The integration line includes lithography, metallization, deep etching, dielectric deposition, wet etching and packaging tools.