Category Archives: 3D Integration

July 31, 2006 – In the latest big move to consolidate power in the memory sector, flash memory giant SanDisk Corp., Milpitas, CA, has agreed to acquire Msystems Ltd., Kfar Saba, Israel, in an all-stock deal valued at up to $1.55 billion, including stock options and convertible debt.

In the near term, the merger strengthens SanDisk’s position in handsets and mobile networks, according to Eli Harari, chairman and CEO of SanDisk, while longer-term the combination will help spark development of next-generation flash-enabled consumer applications. “This strategic acquisition will give us the critical mass and complementary products, customers, channels, technology and manufacturing base to take our shared vision to the next level,” stated Harari, adding that the NAND flash market is still in its early stages and is “largely untapped.”

For Msystems, the deal gives it access to SanDisk’s fab capacity, which is busily expanding with partner Toshiba — through their JV, the two companies are planning to bring online three 300mm, 100,000 wafers/month capacity fabs in the next two years. “SanDisk’s extensive silicon expertise will prove itself as a strong catalyst to productizing our revolutionary x4 technology as well as other future innovations,” added Dov Moran, president and CEO of Msystems.

Under terms of the deal, each Msystems share will be converted into 0.76368 of SanDisk common stock, representing a 26% premium over the average closing price of Msystems’ shares for the last 30 days. The transaction, pending approval from shareholders, regulators, and the Israeli courts, is expected to close in 4Q06.

The deal represents the latest big consolidation move in the memory sector. Earlier this year SanDisk closed its $250 million cash-and-stock acquisition of Matrix Semiconductor Inc., expanding its technology portfolio to include 3D IC technology, which will be used with its thumbnail-sized Gruvi memory cards. Last month Micron Technology Inc. closed its $850 million purchase of memory-card maker Lexar Media Inc.

Msystems earlier this month announced it would restate financial results due to improper calculation of option grants, and would postpone a public offering of 8.7 million shares (worth roughly $294 million). The result was a reduction of net income by a total of $18.8 million from 1999-2005, including nearly $8 million restated from 2004-2005, and approximately $1.4 million in 1Q06.

In mid-May, Msystems announced its x4 technology, designed to enable utilization of 4-bit/cell NAND flash, with mass production projected by 2007. In April Msystems terminated an agreement with Samsung Electronics Co. Ltd., citing the memory giant’s “failure to abide by its supply commitments,” namely secured capacity of NAND flash memory.

July 27, 2006 – ICOS Vision Systems Corp. NV and European R&D center IMEC have agreed to collaborate on development of metrology methods targeting 3D packaging processes for ICs, including wafer-level packaging, flip-chip, systems-in-package, and microelectromechanical systems (MEMS).

The two-year Joint Exploration and Development Program will be closely linked to IMEC’s industrial affiliation program on 3D stacked ICs, which spans work with many leading industry IC suppliers. Research will be conducted at IMEC labs, with ICOS providing inspection and metrology technology and equipment.

“Packaging is becoming an increasingly important part of semiconductor manufacturing and we are expanding our research efforts in the packaging field, including a large research program on 3D packaging,” said Gilbert Declerck, CEO of IMEC. “We are delighted to work with ICOS on the advancements of the 3D packaging processes and the metrology tools that are needed.”

July 6, 2006 – Cookson Electronics Semiconductor Products and Microbonds Inc. have formed a codevelopment project to combine Microbonds’ X-Wire insulated wire bonding technology with Cookson’s Plaskon family of mold compounds.

“The ongoing need to cost effectively mold ever smaller package sizes and types, while maintaining or increasing electrical and yield performance, is beginning to push the limits of molding bare bonding wires,” stated Scott Craig, SVP and GM of the Cookson division.

“The integration of X-Wire Technology with the Plaskon leading molding compounds will provide customers new flexibility in the development and assembly of high performance-to-cost packaged ICs,” added Microbonds CEO John Scott.

Microbonds’ X-Wire Technology insulates gold and copper bonding wires used to connect the silicon die with the package device, addressing limitations of bare bonding wires which short out the device when they touch. Target applications include incorporating thinner diameter gold wires, longer wires, stacked die for wireless applications, and other 3D packaging requirements.

Destined for Growth

BY FLYNN CARSON AND MOSHE BUNYAN, STATS ChipPAC Inc.

The stacked-die approach to vertical integration has encountered some problems as the integration of different device technologies, such as digital processor with DRAM memory, becomes a requirement. Known good die (KGD) issues related to memory, final test-yield considerations, ability to access and test the final package on a common platform, and business issues surrounding ownership and liability compensation of the integrated package product are concerns. Package-on-Package (PoP) has come to the fore as a 3-D package solution that addresses the myriad problems associated with integrating varying device types.

PoP Drivers and Market Trends

PoP offers better time-to-market, flexibility for product upgrades, low non-recurring engineering (NRE) and development costs, and the ability to use existing, high-yielding silicon die, which avoids development of a new chip, shortening the design cycle.

While a typical stacked-die package provides the technology needed to integrate multiple ICs in a single package – reducing the complexity of the motherboard and shrinking the overall size and cost of the portable handheld device – the real power of PoP lies in the flexibility it provides by minimizing liabilities and improving logistics.


Figure 1. Package-on-Package stack.
Click here to enlarge image

PoP provides original equipment manufacturers (OEMs) the flexibility to change silicon technologies’ combinations integrated on the board up to the final moment of final assembly. For example, a cell phone manufacturer can plan on integrating a differential signal processing (DSP) chip package with a high-memory chip package. However, if market conditions change and demand shifts to a low-memory chip package, the OEM can change the bill of materials (BOM) at board assembly and replace the high-memory chip package with the low-memory chip package without requiring a new design or board layout.


Figure 2. PoP business model.
Click here to enlarge image

Integration of several ICs in one package requires logistics management of commercial die acquisition. In a typical stacked-die package, one IC manufacturer must take ownership of all the dice to be integrated into the package. This puts the financial and logistical burden on the owner. PoP eliminates the need for the IC manufacturer to manage the supply chain. Instead, the OEM takes ownership of all the dice to be integrated, and will manage the respective suppliers according to their market demands.

As supply chain issues ease, more integrated device manufacturers (IDMs) and fabless companies are adopting this technology. This has accelerated the growth of this package, and is expected to replace some of the typical 2-die stacked packages and outpace the growth of high-end (>3 die) stack packages.

PoP Technology Requirements and Trends

PoP is leveraging many enabling technologies developed and implemented in production for stacked-die packages. Figure 3 compares the technology required to produce a stacked-die package integrating a digital processor with a memory stack vs. a PoP version. The top PoP is an advanced stacked-die package. The need to minimize the overall stacked package mounted height requires this top PoP to be as thin as possible. Die-thinning down to 75 µm and below, and the use of die-attach films is required. The PoP uses the same wire-bond and low-loop technologies developed and implemented for stacked die. In the bottom PoP, control of wire loop is more critical than stacked-die applications because the thinnest possible mold cap and overall stacked package height is required. Aggressive bond finger pitch is required (down to 80-µm bond finger pitch has been developed) to allow for the smallest mold-cap size and package footprint for a given die size. To achieve such bond finger pitch and route all signals from the top PoP to the device(s) packaged in the bottom PoP, the substrate complexity and technology required for the bottom package is usually higher than for an equivalent stacked-die package. Because of overall package height constraints, the thinnest possible substrates are being used for the bottom and top PoP. Encapsulate molding is a key area that differentiates the PoP package from other stacked-die packages. The bottom PoP requires top center mold gate (TCMG) technology to produce a mold cap without interfering with the peripheral lands on the top of the bottom PoP. The top PoP needs the thinnest possible mold body, which requires advanced molding technology (such as vacuum mold) and molding compounds.


Figure 3. Stacked-die vs. PoP assembly technology.
Click here to enlarge image

Typical mobile phone requirement for package height is less than 1.4 mm, which is difficult to achieve with PoP compared to stacked-die packages. Some allowance can be made to accommodate 1.6-mm maximum height packages, but this is not desirable. The need to minimize the substrate, die, and mold cap thickness, and package-to-package gap for the PoP, leads to other concerns and issues such as package warpage. The top and bottom PoP must be placed on top of each other and reflowed simultaneously on the PCB. The use of lead-free solder balls requires reflow profiles up to a peak temperature of 260°C. Excessive package warpage during the reflow process can lead to solder ball bridging, or no connection between solder joints. Surface mount yields related to PoP are a concern that impacts the adoption and success of this package. Focus has been placed on characterizing and optimizing warpage of the PoP, and developing and optimizing the surface mount process. PoP warpage can be controlled by proper materials selection, particularly mold compounds and die-attach materials, as well as optimizing substrate and package design (Figure 4). Collaborative efforts between package assemblers, device manufacturers, surface mount houses, and end customers are underway to validate board mount yields and reliability.


Figure 4. Material impact on bottom PoP warpage trend during reflow.
Click here to enlarge image

Requirements for higher performance and functional density, and smaller footprint, is the future trend. Flip chip interconnect technology is being integrated to address this, especially into the bottom PoP. A bottom PoP with two devices stacked within has been introduced to enable functional integration and performance of bottom PoP. In addition, different types of bottom PoP configurations are being developed to allow for more device integration in the bottom PoP. PoP is expected to evolve into stackable tested system building blocks. Three-tier or layer-stacked packages are being designed to combine RF, digital, and memory devices. The success and adoption of such future packages will hinge on meeting overall cost, thickness, performance, and thermal requirements.

Conclusion

Leveraging many of the enabling technologies developed and implemented in production for stacked-die packages, PoP technology provides flexible, quick time-to-market, no-supply-chain-headache solutions while meeting the performance, size, and cost requirements of the next-generation devices.

FLYNN CARSON, director of advanced packaging technology, and MOSHE BUNYAN, director of business management, Laminate Products, may be contacted at STATS ChipPAC Inc., 47400 Kato Road, Fremont, CA 94538; 510/979-8338 and 510/979-8346; E-mail: [email protected] and [email protected].

June 26, 2006 – In a move to slough off low-end business and focus on leading-edge technologies, STATS ChipPAC Ltd., a provider of semiconductor test and packaging services, and China Resources Logic Ltd. have agreed to set up a JV for assembly and test services in Wuxi, China. Under the deal, CR Logic’s local subsidiary, Wuxi CR Micro-Assembly Technology Ltd., will purchase $35 million worth of equipment from STATS ChipPAC over four years. STATS ChipPAC also will receive a commission on the aggregate amount of revenues generated from such orders on a quarterly basis in 2007, 2008 and 2009, as well as a 25% ownership stake in the CR Logic subsidiary for $10 million.

Essentially, the company is farming out work for several of its lower-end leadframe package families to the mainland firm, to focus on more leading-edge products such as system-in-package, flip-chip, and 3D technologies, as well as higher pin-count mature technologies including PBGA, QFP, and stacked die TSOP packages. “The joint venture will provide the best overall solution for our customers and allow our factories to focus on what we do best — expanding our full turnkey solutions for leading edge products,” stated Tan Lay Koon, president and CEO.

Under the deal, STATS ChipPAC will transition customers of its low lead count products, including small outline integrated circuit (SOIC), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), mini small-outline package (MSOP), small shrink outline package (SSOP), and thin-shrink small outline package (TSSOP). STATS ChipPAC will continue provide sales and technical support to customers on specific low lead count packages until the end of 2009.

May 26, 2006 – FlipChip International LLC and Engent Inc. are partnering to develop 3D wafer-level CSP (WLCSP) technologies, seen as a low-cost alternative to system-on-chip for highly integrated stacked die packaging applications.

The partnership will combine FlipChip’s ultrafine pitch wafer bumping capabilities and 2D wafer-level CSP package offerings with Engent’s advance surface mount and flip-chip assembly technologies. The platform to emerge from their efforts will support a range of ultrahigh volume IC packaging applications, including silicon-on-silicon, GaAs-on-silicon, and SiGe-on-silicon, as well as 3D integration of integrated passive device technologies and MEMS devices for system-in-a-stack offerings.

“We are excited about our alliance with Engent since it enables our customers to realize the cost and miniaturization benefits of 3D stacking over traditional 2D packaging,” stated Bob Forcier, CEO of FlipChip International.

(May 15, 2006) Herndon, VA &#8212 The International Electronics Manufacturing Initiative (iNEMI) will hold a 2007 Roadmap workshop in Shanghai, China, in tandem with the High-density Microsystem Design and Packaging and Component Failure Analysis in Electronics Manufacturing (HDP) 2006 conference. Co-sponsored by HDP 2006, the Sino-Swedish Microsystem Integration Tech (SMIT) Center, and the IEEE Components, Packaging, and Manufacturing Technology Society (CPMT), the half-day workshop will take place June 27, 2006, on the Yan Chang Campus of Shanghai University.

(May 15, 2006) Research Triangle Park, NC &#8212 The third annual “3D Architectures for Semiconductor Integration and Packaging” conference, held by RTI International, will convene in San Francisco, CA, on October 31–November 2, 2006.

February 9, 2006 – SEMATECH has launched a new project to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry. Work will initially focus on developing a cost model for 3D migration and a list of infrastructure needs for SEMATECH member companies, as well as building consensus on 3D technology standards. Future activities will involve proving feasibility of the technology for materials, unit processes, integration, and reliability.

The industry has pursued copper and low-k interconnect materials, which are now moving into real products, but decreasing k effective by changing dielectrics and assist layers presents the challenge of continuously developing and requalifying new metals, explained Sitaram Arkalgud, director of SEMATECH’s interconnect division. “The ITRS shows that low-k technology alone will not be sufficient to meet the needs of microdevices in 2010. Of the available options, 3D may offer the least disruptive path to the next interconnect paradigm.” He added that the new 3D interconnect project will augment SEMATECH’s low-k development program emphasizing chemical vapor deposition (CVD) films.

The program will focus on wafer-on-wafer and die-on-wafer structures, seeking answers for both high-performance and low-cost products, Arkalgud stated. A working group of about 20 SEMATECH member companies has been formed to assess key challenges of 3D interconnect and available options, and will develop a 3D roadmap with the ultimate goal of transferring the process to the ITRS.

3D interconnect involves the physical and electrical bonding of semiconductor wafers and dies, using deep through-silicon vias, to produce multilevel microchips with advanced processing capabilities. At volume production levels, it promises more cost-effective integrated chips that are easier to engineer.

Ziptronix reports first 3D SoC


September 26, 2005

September 26, 2005 – Ziptronix, Morrisville, NC, has made good on its efforts at creating a three-dimensional IC device to serve as an alternative to system-in-package (SiP) technology, according to a company statement. Since January, when the 3D IC developer’s plans to produce first silicon within 1Q05 were announced by Solid State Technology, the company has realized what it claims is the first 3D system-on-a-chip (SoC) device — employing proprietary ZiROC and ZiCON technologies — to combine memory, microprocessor, and programmable-logic die into a single, multilevel silicon die measuring 280mm2 and the second level measuring just 0.03mm in height.

A spin-off from the Research Triangle Institute, Ziptronix exercised its experience in dielectric covalent bonding and die thinning by means of an adhesive-free method (ZiROC) that forms covalent bonds directly between silicon oxide-coated die using available manufacturing equipment and techniques. Off-the-shelf components and die-scale integration have helped reduce the time-to-market design cycle to six months vs. the typical 12-14 months. Phil Nyborg, president and CEO, believes that this 3D integration technology will enable “devices with 2 billion-plus transistors in the smallest possible footprint” for communications, embedded systems, and consumer electronics applications.

Aug. 11, 2005 — RoseStreet Labs announced the opening of its 3D R&D lab for next generation semiconductor packaging and also announced an alliance with SUSS MicroTec. SUSS’s lithography and 3D packaging equipment was selected for RoseStreet’s laboratory.

RoseStreet, headquartered in Phoenix, Ariz., offers contract R&D services in addition to its internal R&D work to support its subsidiary FlipChip International’s flip chip and wafer level packaging product lines. RoseStreet and Flip Chip develop new materials and processes for packaging utilized in wireless products.