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Nakamura Co-Wins Nobel for Blue LEDs

The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources”. In the late 1980s red and green LEDs had been around for decades, but despite large programs in both academia and industry there had been almost no R&D progress in blue LEDs (this editor did process R&D in an LED fab in that era). Then Akasaki and Amano at the University of Nagoya showed work on improved p-doping in GaN due to electron irradiance, leading to p-n junctions to make diodes.

Structure of a blue LED with a InGaN/AlGaN double heterojunction [Source: S. Nakamura, T. Mukai & M. Senoh, Appl. Phys. Lett. 64, 1687 (1994)].

Structure of a blue LED with a InGaN/AlGaN double heterojunction (Source: S. Nakamura, T. Mukai & M. Senoh, Appl. Phys. Lett. 64, V1687, 1994).

From 1989 to 1994, Shuji Nakamura worked at Nichia Chemicals in Tokushima, Japan where he led a small team of co-workers to achieve a quantum efficiency of 2.7% using a double heterojunction InGaN/AlGaN (see Figure). With these important first steps, the path was cleared towards the development of efficient blue LEDs and solid-state white lighting. Nakamura-sensei is now a Professor of Physics at the University of California, Santa Barbara, and co-founder of Soora Corp. where GaN-on-GaN technology is used to increase efficiency through the elimination of the buffer-layers needed with saphhire substrates. The “Tales of Nakamura” article at IEEE Spectrum provides an excellent summary of this extraordinary man’s life story, including the US$600M payout from Nichia that was reduced to US$8M by a higher court.
Incandescent light bulbs lit the 20th century; the 21st century will be lit by LED lamps with high lm/W efficiency. The most recent record is just over 300 lm/W, which can be compared to 16 for regular light bulbs and close to 70 for fluorescent lamps. As about one fourth of world electricity consumption is used for lighting purposes, the LEDs contribute to saving the Earth’s resources.
Shine on!
—E.K.

IBM Shows Graphene as Epi Template

Chasing IC Yield when Every Atom Counts

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Increasing fab costs coming for inspection and metrology
At SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices (Figure source is the ITRS 2013 Yield Chapter). Due to the sensitive nature of the topic, recording was not allowed and copies of the presentations could not be shared.
Qualcomm – Geoffrey Yu
Double-patterning will be needed for metal and via layers as we go before 90nm pitch for the next generations of ICs. Qualcomm is committed to designing IC with smaller features, but not all companies may need to do so. Fab costs keep going up for atomic-scale devices…and there are tough trade-offs that must be made, including possibly relaxing reliability requirements. “Depending on the region. If you’re in an emerging region maybe the reliability requirements won’t be as high,” said Yu. Through-Silicon Vias (TSV) will eventually be used to stack IC layers, but they add cost and will only be used when performance cannot be met with cheaper solutions. “An early idea was to use TSV for logic:memory,” reminded Yu, “but then there was innovation to LPDDR4 allowing it deliver the same bandwidth with one-half the power of LPDDR3, which delayed TSV.”
GlobalFoundries – Harry Levenson
“A more expensive part could provide a better value proposition for a customer,” reminded Levenson as he discussed the challenges of inspecting next-generation commercial ICs in high-volume manufacturing (HVM). “We still have clear demand for products to run in HVM at the leading edge, but we are now in the world of double-patterning and this applies to optical inspection as well as imaging.” Requirements for inspection and imaging are different, but he same physics applies. In imaging Depth of Focus (DoF) of ~140nm is generally preferred, while the same used for inspection of a <140nm thin film would to induce noise from lower-levels. We can’t do e-beam inspections due to too much energy concentration needed to get acceptable throughput (and the challenge gets worse as the pixel area is reduced, inherently slowing down throughput). However, e-beams are helpful because they can detect open contracts/vias in metal levels due to the conductivity of electrons providing additional contrast compared to any possible optical inspection.
Applied Materials – Sanjiv Mittal
Mittal discussed how the CMOS transistor gate formation process has increased in complexity over the last few device generations: 8x more unit-process steps, 3x higher fab cost, 50x lower defects needed for yield. “The challenges are immense,” admitted Mittal. “What happens when you try to work on yield improvement when you’re ramping volume? At the same time you’re trying to improve yield by making changes, you’re trying to increase the volume by not making changes.”
Entegris – Jim O’Neill
O’Neill is CTO of the combined Entegris post-merger with ATMI, and was recently director of advanced process R&D for IBM. Since Entegris provides materials and sub-systems, in the simplest cases the company works to improve IC fab yield by minimizing defects. “However, the role of the materials-supplier should change,” averred O’Neill. “The industry needs bottle-to-nozzle wet chemistry solutions, and applications-based clean gas delivery.” In an exclusive interview with SST/SemiMD, O’Neill provided as example of a ‘wetted process solution’ a post-CMP-clean optimized through tuning of the brush polymer composition with the cleaning chemistry.
ITRS Difficult Challenges for Yield 2013-2020

Existing techniques trade-off throughput for sensitivity, but at expected defect levels, both throughput and sensitivity are necessary for statistical validity.
Reduction of inspection costs and increase of throughput is crucial in view of CoO.
Detection of line roughness due to process variation.
Electrical and physical failure analysis for killer defects at high capture rate, high throughput and high precision.
Reduction of background noise from detection units and samples to improve the sensitivity of systems.
Improvement of signal to noise ratio to delineate defect from process variation.
Where does process variation stop and defect start?

—E.K.

Moore’s Law is Dead – (Part 4) Why?

Moore’s Law is Dead – (Part 3) Where?

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…we reach the atomic limits of device scaling.

At ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Lead bongo player of physics Richard Feynman famously said, “There’s plenty of room at the bottom,” and in 1959 when the IC was invented a semiconductor device was composed of billions of atoms so it seemed that it would always be so. Today, however, we can see the atomic limits of miniaturization on the horizon, and we can start to imagine the smallest possible functioning electronic device.

Today’s leading edge ICs are made using “22nm node” fab technology where the smallest lithographically defined structure—likely a transistor gate—is just 22nm across. However, the pitch between such transistors is ~120nm, because we are already dealing with the resolution limits of lithography using water-immersion 193nm with off-axis-illumination through phase-shift masks. Even if a “next-generation” lithography (NGL) technology were proven cost-effective in manufacturing— perhaps EbDW for guidelines combined with DSA for feature fill and EUV for trim—we still must control individual atoms.

We may have confidence in shrinking to 62nm pitch for a 4x increase in density. We may even be optimistic that we can shrink further to a 41nm pitch for a ~10x increase in density…but that’s nearing the atomic limits of variability. There are many hypothesized nanoscale devices which could succeed silicon CMOS in IC, but one commonality of all devices is that they will have to be electrically connected. Therefore, we can simplify our consideration of the atomic limits of device scaling by focusing on the smallest possible interconnect.

So what is the smallest possible electrical interconnect? So far it would be a Single-Walled Carbon NanoTube (SWCNT) doped with metals to be conducting. The minimum diameter of a SWCNT happens to be 0.4nm, but that was found inside another CNT and the minimum repeatable diameter for a stand-alone SWCNT is ~1nm. So if we need three contacts to a device then the smallest device we can build with atoms would be a 3nm diameter quantum dot. As shown in the figure at right, if we examine a plan-view of such a device we can just fit three 1nm diameter contacts within the area.

Our magical device will have to be electrically isolated and so some manner of dielectric will be needed with some minimal number of atoms. Atomic Layer Deposition (ALD) of alumina has been proven in very tight geometries, and 3 atomic layers of alumina takes up ~1nm so we can assume that spacing between devices. A rectangular array would then result in ~16nm2 as the smallest possible 3-terminal device that can be built on the surface of planet Earth.

Note that a SWCNT of ~1 nm diameter theoretically could carry ~25 microAmps across an estimated 5kOhm internal resistance [(ECS Transactions, 3 (2) 441-448 (2006)]. I will leave it to someone with a stronger device physics background to comment as to the suitability of such contacts for useful circuitry. However, from a manufacturing perspective, to ensure electrical contacts to billions of nanoscale devices we generally use redundant structures, and doubling the number of SWCNT contacts to a 3-terminal device would call for ~8 nm pitch.

However, before we reach the 4-8nm pitch theoretical limits of device scaling, we will reach relative economic limits of scaling just one device feature such as a transistor gate. Recall that there are just 22 silicon atoms (assuming silicon crystal lattice spacing of ~0.3nm) across a ~7nm line, and every atom counts in controlling device parameters. Imec’s Aaron Thean recently provided an excellent overview of scaled finFET technologies, and though the work does not look at packing density we can draw some general trends. If we assume 41nm pitch and double fins with 20nm gate length then each device would use ~1,600 nm2.

Where are we now? Let us consider traditional 6-transistor (6T) SRAM cells built using “22nm node” logic process flows to have minimal area of ~100,000 nm2 or ~16,000 nm2 per transistor. At IEDM2013 (9.1), TSMC announced a “16nm node” 6T SRAM with ~70,000 nm2 area or ~10,000 nm2 per transistor.

IBM recently announced that 6 parallel 30nm long SWCNT spaced 8nm apart will be developed as transistors for ICs by the year 2020. Such an array would use up ~1440 nm2 of area. Again, this is at best another 10x in density compared to today’s “22nm node” ICs.

Imec held another Technology Forum at SEMICON/West this year, in which Wilfried Vandervorst presented an overview of innovations in metrology needed to continue shrinking device dimensions. His work with Scanning Spreading Resistance Microscopy (SSRM) is extraordinary, showing ability to resolve 1-2nm conductivity variations in memory cell material. Working with Resistive RAM (ReRAM) material using a 2nm diameter probe tip as the top contact, researchers were able to show switching of the material only underneath the contact…thus proving that a stable ReRAM cell can be made with that diameter. If we use cross-bar architectures of that material we’d be at a 4nm pitch for memory, coincidentally the same pitch needed for the densest array of 3-terminal logic components.

IC SCALING LIMITATION	Pitch / “Node”	Transistor nm2	Scale from 22nm
193nm lithography double-patterning	124nm / “22nm”	16000	1
Atomic variability (economics)	41nm / “7nm”	1600	10
Perfect atoms (physics)	4nm	16	1000

The refreshing aspect of this interconnect analysis is that it just doesn’t matter what magical switch you imagine replacing CMOS. No matter whether you imagine quantum-dots or molecular memories as circuit elements, you have to somehow connect them together.

Note also that moving to 3D IC designs does not fundamentally change the economic limits of scaling, nor does it alter the interconnect challenge. 3D ICs will certainly allow for greater number of devices to be packed into a given volume, so mobile applications will likely continue to pull for 3D integration. However, the cost/transistor is limited by 2D process technologies that have evolved over 60 years to provide maximum efficiency. Stacking IC layers will allow for faster and smaller devices, though generally only with greater costs.

Atoms don’t scale.

Past posts in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end, and

Moore’s Law is Dead – (Part 2) When we reach economic limits.

The final post in this blog series (but not the blog) will discuss:

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.

Moore’s Law is Dead – (Part 2) When?

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…economics of lithography slow scaling.

Moore’s Law had been on life support ever since the industry started needing Double-Patterning (DP) at 1/4-pitch of 193nm optical lithography. EUV lithography shows slow and steady progress in source and resist technologies, and ASML folks tell me that they now have a pellicle to protect the reflective masks, yet it remains in R&D. All other lithographic technologies under consideration—e-beam direct write, nano-imprint, directed self-assembly—can help with patterning certain layers for certain chips, but lack the broad applicability and economic advantages of 193nm.

At this year’s SPIE Advanced Lithography event, renowned lithographer and gentleman scientist Chris Mack led an extended toast (https://www.youtube.com/watch?v=IBrEx-FINEI) that ended with, “Moore’s Law is over, long live Moore’s Law.” While Wednesday, February 26, 2014 may seem like a rather arbitrary moment, we seem to have the informal consensus of the world’s leading lithographers.

The 4^th blog in this series will discuss the “Why” of Moore’s Law continuing as a marketing term…with each company in the industry using the term as well as “More than Moore” to mean slightly different technology advances. Henceforth, “Moore’s Law” may mean that the next IC will be smaller, or faster, or cheaper…but we are past the era when new chips will be simultaneously smaller and faster and cheaper.

The adjacent figure from SEMI shows the rate of scaling since we hit 90nm half-pitch…the last time that the term “node” directly correlated to the lithographic half-pitch. The clear inflection-point at the “32nm node” (which was really 45nm half-pitch) was the moment that DP was needed for patterning critical layers. In a panel discussion at the 2014 imec Technology Forum in San Francisco during SEMICON/West, John Chen, vice president of technology and foundry management, NVIDIA clearly declared, “Double-patterning is a technological and economic discontinuity.”

I should note that, as the EUV developer for the world, ASML strongly feels that the technology will enable future cost-effective scaling.

Meanwhile, 193nm lithography currently provides the economic limits to scaling, so we can easily understand recent and future phases of the industry in terms of fractions of this wavelength:

½ of 193nm = 90nm half-pitch as the end of simple scaling,

¼ of 193nm = 45nm half-pitch (~32nm “node”) begins Double Patterning,

1/8 of 193nm = 22nm half-pitch begins Quadruple Patterning, and

1/16^th of 193nm = 11nm half-pitch which would need Octuple Patterning.

Note that the half-pitch limits shown above are approximations, and the lithography community has been using every trick in the book to lower the resolution limit of 193nm lithography. Water immersion for higher-NA, ‘inverse lithography’ to optimize phase-shifting masks, and off-axis illumination have all been deployed to allow 45nm half-pitch patterning.

Quartz lenses become opaque below 193nm, and thereby limit use of any lower wavelengths. Thus, 193nm has become an economic limit on affordable IC production, just as 1234 km/h has been proven as the economic limit on commercial aircraft speed. The “Concorde analogy” explains that physical world constraints combine with economics to create real limits on exponential progress.

Since the air-travel industry hit the economic limit of the speed-of-sound, air-travel innovation has continued but not in raw speed. Quiet airplane cabins and huge improvement in in-flight entertainment and food, when combined with refreshments and entertainment in airports improves the overall experience. Wireless computer networks on airplanes and in airports allow travelers with mobile computers (including smart-phones and tablets) to work and play throughout the travel day.

Innovation in the semiconductor industry will certainly continue after we can no longer afford to shrink digital switches. We already have billions of logic elements with which to form circuitry, and we can combine logic with embedded-memory and with sensors and actuators into 3D nanoscale systems. We can do this today. The truth is, when we run out of room at the 2D bottom we have plenty of room to play at the 3D top…remembering that the cost of chip stacking is set by 2D processing economics.

Past post in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end.

Imminent posts in this blog series will discuss:

Moore’s Law is Dead – (Part 3) Where we reach atomic limits,

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.

Moore’s Law is Dead – (Part 1) What?

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…twice the number of components won’t appear on the next IC chip (Part 1 of 4)

Gordon Moore always calls it “so-called Moore’s Law” when discussing his eponymous observation about IC scaling trends, and he has always acknowledged that it’s no more and no less than a marketing tool used to inform an ecosystem of downstream chip-users of price:performance improvements planned. The original observation published in 1965 and updated in 1975 established that the number of functional circuit components—including transistors, diodes, and any passive components—on a single IC chip doubled periodically.

When Moore updated this in 1975 (Moore, Gordon. “Progress in Digital Integrated Electronics” IEEE, IEDM Tech Digest (1975) pp.11-13.) he decomposed the sources of increasing component count as follows:

Die size increase,
Dimension decrease (a.k.a. “shrink”),
Device and Circuit design (a.k.a. “cleverness”).

Note that Moore never said anything about cost, speed, power-consumption, or reliability. It was left to the IC sales guys to inform that lithographic R&D meant that the next generation chips would actually be smaller and cost less, and most importantly the ability to maintain Dennard Scaling with power-reduction/transistor rules meant that each chip reliably consumed less power. This was the glory era when each new chip generation provided it all: more components, faster speed, and cheaper price.

Five years ago, Gordon Moore and Jay Last provided an insightful review of the founding of the IC industry at the Computer History Museum, which I covered in an independent blog posting (http://www.betasights.net/wordpress/?p=758). As well summarized in the “Transistor Count” entry at Wikipedia (https://en.wikipedia.org/wiki/Transistor_count) by 1975 the industry was working on designs with 10k transistors, and 100k by 1982, and 1 million by 1989. Incredibly, the trend continued to 1 billion transistors on a chip in production in 2010.

In my interview with Gordon Moore published in the July 1997 issue of Solid State Technology, he emphasized two points: the atomic limits of IC manufacturing, and the fact that when we start to reach atomic limits we’ll be able to put 1 billion circuit elements into a square centimeter of silicon. However, henceforth we will no longer get it all with the next generation chips, and will only be able to choose one from the glory list that used to be a package deal (pun intended): more, faster, cheaper. IC innovation will certainly continue, but it will not come through smaller and faster and cheaper circuit elements. Moore’s accurate prediction of gigascale circuitry on cheap chips explicitly sets the stage for the next 50 years of innovation in IC manufacturing…we’ve only begun to play with billions of transistors.

Make no mistake, everyone wishes that Moore’s Law was still alive and well. IC fabs most of all, but everyone from economists and politicians promising exponential growth (http://www.foreignpolicy.com/articles/2010/10/11/opening_gambit_moores_flaw) to futurists selling absurd fantasies of benevolent nanobots (http://www.singularity.org) deeply wish that Moore’s Law would continue. Sadly, no exponential in the real world can go on forever, and we make mistakes when we blindly ignore changing conditions behind an exponential trend.

More than ever before, people with little understanding of what Gordon Moore said let alone what he meant try to discuss the ramifications of an eventual end to Moore’s Law. In particular, people who have never worked in a semiconductor fab nor designed a commercial IC love extrapolating prior trend-lines forward without an understanding of how we got here nor a clue about the real atomic and economic limits of IC production.

Some analyses ignore the realities of manufacturing process control (http://www.mooreslaw.org/) while others revel in extrapolations based on mathematical abstractions and economic theories (http://www.ebnonline.com/author.asp?section_id=3315&doc_id=273652), and such work can be so bad that it is “not even wrong”.

Imminent posts in this blog series will discuss:

Moore’s Law is Dead – (Part 2) When we reach economic limits,

Moore’s Law is Dead – (Part 3) Where we reach atomic limits,

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.