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IFTLE 113 An Exclusive Interview with Mr Lester Lightbulb

As readers of IFTLE might imagine, the recent headline "3M Claims new LED Lightbulb designed to burn for 25 years" caught my eye. The article went on to say that the bulb, which looks like a traditional incandescent, has a 25-year lifespan (at three hours of use per day) and a $25 price tag. 3M is betting the price won’t be a huge hurdle for consumers because competing LED bulbs "are priced closer to $45." They then repeated the infamous refrain: "LED light costs $1.63 per year to operate — a quarter of the cost of a traditional bulb. So even at $25, given its longevity, it still comes out where you save money over the life of the bulb."

The bulb uses 3M’s multilayer optical film, adhesives, and heat-management technology. They indicate that their marketing has determined that "prospective buyers are likely to be environmentally conscious and more affluent — similar to those who bought a Toyota Prius hybrid in 2006." IFTLE certainly agrees 100% with the last statement.

IFTLE has gone into great detail to show that it is the bulb that matters, not the expected life of the LED chip. If any of the components of the bulb are not rated for a 25-year lifetime the bulb should not be rated for this period of time. I checked the IFTLE BS meter for the merit of LED lightbulb ads and sure enough they rate just short of outright fraud.

As I shook my head in disbelief that this scam of the American public was continuing unabated, with no corrective information coming from the DOE or any other Government agency [yes that was said tongue in cheek], I got a collect call from old friend Lester Lightbulb. As you know Lester is sitting on death row in San Quentin [isn’t it fitting that California is the state that incarcerated him]. As he awaits the electric chair [pun intended] Lester reached out to admonish me for calling my recently failed CFL his "cousin" [see IFTLE 109: "2012 IEEE VLSI Conference ; Lester’s cousin CFLDies Prematurely"].

While I had him on the phone I thought you, the readers of IFTLE, would appreciate a direct interview with Lester.

IFTLE: Lester, of course we know that CFL and you are not related, we were just trying to link you, CFL and LED as part of the interior lighting family.

Lester: I’d like to thank IFTLE and its like-minded readers for supporting me as I await eradication from the face of the earth, but that dirtbag "quicksilver" is no family member of mine. Do you see a tungsten filament? NO. So he is certainly not related to me.

IFTLE: Quicksilver… is that his nickname?

Lester: Yes, that’s what all us incandescents call him — quicksilver is mercury and all the CFLs contain that highly toxic element. They are the least environmentally friendly source of light that we can use, which makes it quite ironic that those who claim they are trying to save the environment are about to eradicate me and use him. I guess you haven’t seen the latest headlines from Sweden have you?

IFTLE: No, please share them with us, Lester.

Lester: "CFLs creating ‘acute crisis’ in Sweden." In a series of articles the Swedish newspaper Svenska Dagbladet has reported on the large scale ongoing dumping of fluorescent bulbs (CFLs), and the dangers of released mercury that goes with it [link].

Mina Gillberg, former advisor to EU environment commisioner Margot Wallström is now regretting the consequences of their decision to switch to CFLs. "The motive for replacing incandescent bulbs with CFLs was to save electricity and thereby save the environment," but Gillberg now condemns the drive for CFLs as "absurd."

Sweden estimates that 200,000 CFLs are thrown into glass recycling bins per year. "‘This is a health risk for those who work with recycling and a risk that the environmental toxin spreads in the natural environment"…" Especially when the recycling bins are indoors, since mercury vaporizes at room temperature and contaminates the surrounding area."

IFTLE: So mercury or quicksilver is really that big a problem, Lester?

Lester: Mercury has long been recognized worldwide as a health hazard because its accumulation in the body can damage the nervous system, lungs, and kidneys, posing a particular threat to babies in the womb and young children. No one I have ever heard of, of any political persuasion, defends mercury.

The British government instructs households that "…if a compact fluorescent lightbulb is broken in the home, the room should be cleared for 15 minutes because of the danger of inhaling mercury vapour." Similar warnings are on US packaging where, as we have already discussed, the consumer is directed to contact the EPA for proper disposal procedures.

In 2009, timesonline [UK] reported extensively on the production of CFL in China, where "a heavy environmental price is being paid for the production of ‘green’ lightbulbs."

Tests on hundreds of Chinese employees found dangerously high levels of mercury in their bodies and many have required hospital treatment, according to local health officials in the cities of Foshan and Guangzhou. At the Nanhai Feiyang lighting factory in Foshan tests found 68 out of 72 workers were so badly poisoned they required hospitalization. In Jinzhou, 121 out of 123 employees had excessive mercury levels."

In 2008 Maine banned the disposal of CFL bulbs. In their tests CFLs were broken in a small/ moderate sized room and mercury concentrations in the room were continuously monitored. "Mercury concentration in the room air often exceeded the Maine Ambient Air Guideline of 300 ng/m3 for some period of time, with short excursions over 25,000 ng/m3, sometimes over 50,000 ng/m3, and possibly over 100,000 ng/m3 from the breakage of a single compact fluorescent lamp…. All types of flooring surfaces tested can retain mercury sources even when visibly clean….. Residual mercury in the carpeting has particular significance for children rolling around on a floor, babies crawling, or non mobile infants placed on the floor…. Vacuuming up the smaller debris particles in an un-vented room can elevate mercury concentrations over the MAAG in the room and it can linger at these levels for hours. And the vacuum can become contaminated by mercury such that it cannot be easily decontaminated." They indicated that the homeowner would have a decision on whether or not to "replace the carpet in the area where the bulb was broken."

Is anyone who is buying a previously owned home thinking about whether the carpet has been contaminated with mercury? And what that means to their small children?

So IFTLE, can you tell me why the world’s governments and the world’s self-described "environmentalists" are trying to eradicate the incandescant bulb and replace them with CFLs?

IFTLE: Lester, I think it’s all tied to the EPA. In 1990, EPA was given authority to control mercury and other hazardous air pollutants from major sources of emissions to the air. For fossil fuel-fired power plants, the amendments required EPA to conduct a study of hazardous air pollutant emissions. In 1999, EPA estimated that approximately 75 tons of mercury were found in the coal delivered to power plants each year and about two-thirds of this mercury was emitted to the air annually. In 2000, the EPA found that regulation of hazardous air pollutants, including mercury, from coal and oil-fired power plants was appropriate and necessary. Lester, don’t you think that this is a good thing? You can’t be for supporting mercury pouring into the atmosphere from our electric utilities, can you?

Lester: No, none of us are, but the electric utilities are taking steps to reduce mercury emissions from power plants as part of ongoing pollution prevention programs. In fact, existing control technologies for sulfur dioxide (SO2), nitrogen oxides (NOx), and particulate matter have reduced power plant mercury emissions by roughly 40 percent already. All of those nasty materials need to be scrubbed as does mercury, but notice I do not include CO2…and don’t get me started on that, because CO2 has gotten a worse bum rap than I have by the same ignorant environmentalists and corrupt scientists.

IFTLE: SOX, NOX and particuate reductions are all good things, Lester. I’m with you on the C02 emissions too, Lester. CO2 rates a 5+ on my BS meter, but we shall discuss that scientific fraud another day.

Lester: Anyway, my point is that instead of justifying toxic quicksilver light bulbs by pointing a finger at how toxic power generation is, why not continue to use safe, non-toxic, incandescent light bulbs and work on cleaning up the effluent from our power plants?

IFTLE: Once again you make sense, Lester. Let’s take a few minutes to discuss one of my pet peeves: CFL longevity. It’s claimed that a CFL will last ten times longer than an incandescent [It says so right on the packaging]. When my CFL bulb recently burned out faster than my incandescent bulbs [see IFTLE 109, "2012 IEEE VLSI Conference; Lester’s cousin CFL Dies Prematurely"], several readers reported that they too had experienced less than 1 year lifetime from their CFL bulbs. Hmmmm…

Lester: The basic problem is that quicksilver bulb lifetime is impacted by how often the bulbs are turned on and off and their use temperature. Optimal use for a fluorescent light is to be left on all the time at temperatures between 50-80°F. Wikipedia indicates that "In the case of a 5-minute on/off cycle the lifespan of a CFL can be reduced to close to that of incandescent light bulbs" — which is exactly the result that you got!

Since a lot of light use in the home is less than five minutes (i.e., a trip to the bathroom; looking in a closet; quick night time trip to the kitchen; get tool out of the garage, etc.), a much more accurate statement for CFL packaging would be: "Lifetime is estimated at 250-10,000 hours depending on use."

The picture below is of a CFL that failed after 200 hours [link]. The electrolytic capacitor is bulging at the end, and it had ruptured its safety seal and leaked electrolyte; the heatshrink tubing around the inductor got so hot that it split; and the capacitors are all seriously discolored.

The only way to get the maximum life from any CFL is to keep the electronics as cool as possible — preferably well under the manufacturers’ recommendation of 50°F.

Homeowners will also be faced with the expensive requirement to replace all non-ventilated light fittings with new ones that have sufficient airflow to maintain a safe temperature for CFL use. Because such fittings must be installed by a licensed electrician (in most countries), this is another expense that is usually ignored.

Any potential saving in energy bills is gone … for quite a few years, until the cost of the fittings and their installation is amortized. There is also the enormous waste of replacing perfectly good light fixtures with new ones, so the environmental impact is also negative — probably by a large margin.

By the way, IFTLE, I saw that you threw your CFL bulb away with the garbage. Hope you won’t be doing that anymore after our little discussion on mercury!

IFTLE: Wow, Lester, that’s a lot to think about. Anything else you want to share with our readers?

Lester: Yes, I’d like them to read the 2009 NY Times "green blog" interview with Howard Brandston. He is the award-winning lighting designer who helped develop the nation’s first standards for energy-efficient building design.

Mr. Brandston accuses "energy zealots" of using "faulty science" to determine the efficiency of light bulbs. To quote Mr Branston: "The calculations used by the government and others promulgating or promoting use of CFLs is strictly mathematical conjecture and has nothing to do with reality."

When asked whether we shouldn’t be doing all we can to cut down the amount of power usage, he responded: "But hoping that lighting is going to make a major contribution [to the reduction of power usage] borders on ridiculous. The real areas that should be looked at that would make big gains are in all commercial office buildings. If they raised the temperature in the summer that they would cool to and lowered the temperature that they would heat to […] we would save more energy in a few months than all the lighting watts per square foot baloney that’s going on now."

Basically, IFTLE, his conclusions are the same as yours when you looked at how much lighting contributed to the overall power usage in your house: "If you’re trying to save energy, that isn’t the place to start." [see IFTLE 98: Lester the Lightbulb vs. CFL and LED: The saga continues]

IFTLE: Lester, as always it has been a pleasure. I sincerely hope we can turn things around and get you a pardon, for your good and the good of the country.


For all the latest on 3DIC, advanced packaging and the exploits of Lester the Lightbulb stay linked to IFTLE…………………………

IFTLE 112 TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards; Sony shows off 3D stacked Image Sensors

The Latest from TSMC

Ken Liu of Taiwan Economic News reports that TSMC is aggressively hiring for their 2.5/3D packaging and test unit and will have a team of over 400 specialists ready for this business area [link]. Reports are that they have hired experts away from ASE, Siliconware and Powertech to fill these vacancies.

In the past IFTLE  has insinuated that TSMC was working with a half dozen primary customers in the 2.5D area. Liu now names them as Xilinx, AMD, Nvidia, Qualcomm, TI, Marvell and Altera Corp.

Reports in Taiwan are that TSMC lost the chance for making Apple A3 processors to Samsung because of its lack of the capability to package and test the chips. TSMC management reportedly now feels confident of securing Apple’s foundry contracts for next-generation processors. The A6 ??
Per Steve Liebson here is a close up of the TSMC / Alterra  2.5D (which TSMC is now calling their chip-on-wafer-on-substrate CoWoS technology) test vehicle which we have previously described [ link]. It was evidently was on display at the Cadence booth at the recent design automation conference. TSMC describes the 2.5D circuit  as being composed of 65 nm GPS, 45 nm DRAM and 28 nm SoC.

(Click on any of the images below to enlarge them.)



3DIC SEMI Standards

The Inspection and Metrology Task Force  of  the Semi 3D standards group, recently approved its first Standard ,SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology. SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs). Although different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter, it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry.

Other standards under development by the  Inspection & Metrology Task Force include SEMI Draft Document 5270, Guide for Measuring Voids in Bonded Wafer Stacks, SEMI Draft Document 5409, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks, SEMI Draft Document 5410, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures, and SEMI Draft Document 5447, Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures.

The Thin Wafer Handling Task Force is focused defining thin wafer handling requirements including physical interfaces used in 3D-IC manufacturing. Current standards for shipping are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3D-IC manufacturing. Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. SEMI Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers.

The Bonded Wafer Stacks Task Force is near completion of its SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack and SEMI Draft Document 5174, Specification for Identification and Marking for Bonded Wafer Stacks.

Current wafer standards do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits. In each step of a 3D-IC process, the incoming material must be specified in terms of wafer dimension and materials present. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters change when wafer stacks are bonded, debonded, and when wafers incorporated into stacks are thinned. Further, these parameters will change for a single wafer stack during process. This Document will provide the required properties of both silicon ("device") wafers and glass ("carrier") wafers to be used in 3D-IC applications. Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well.

The Middle-End Task Force is focused on the middle-end processes on wafers with or without TSVs, including post-final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line formation and carrier de-bond. The task force’s first two proposals are SEMI Draft Document 5473, Guide for Alignment Mark for 3DS-IC Process, and SEMI Draft Document 5474, Guide for CMP and Micro-bump Processes for Frontside TSV Integration.

Further details on the Semi standard efforts can be found here [link]. 

Sony Stacked Image Sensor

CMOS image sensors are used in a wide range of Sony products, including digital cameras, digital camcorders, DSLR cameras and Android based smartphones. Sony has focused on key traditional parameters such as increased pixel counts, improved resolution and higher speed. January 2012, Sony announced that it had successfully developed a 3D stacked CMOS image sensor complete with TSV. In place of the supporting substrate used in conventional back-illuminated CMOS image sensors, this image sensor stacks  the back-illuminated pixels layer onto chips containing the circuit section for signal processing which facilitates greater functionality and compactness. The new structure is positioned to become the next generation of back-illuminated CMOS image sensors.

 In the figure below Sony compares their new stacker CMOS image sensor to previous advancements such as Exmor (on chip column parallel A/D conversion) and Exmor R (backside illuminated). The size gains are obvious.
For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………………

IFTLE 111 New Temporary Bonding Technologies Introduced at Suss 3D Workshop

At the recent Semicon West, Suss, which supports all commercially available temporary bonding solutions, held their annual 3D workshop.

(Click on any of the images below to enlarge them.)

IMEC
Eric Beyne of IMEC reported on 3D technology status. He sees:
– a clear industry convergence on Cu-TSV, vias middle with TSV dimensions 5 x 50 um. 
– a significant challenge is still a  wafer carrier system for wafer thinning with high precision and compatible with further backside processing
– as the technology matures they see a stronger emphasis on fine pitch die-to-die stacking : 40 µm Ã?? 20 µm Ã?? 10 µm
Beyne sees current application focus areas as:

When looking at all the studies performed on TSVs the literature offers the following conclusions:

IMEC is moving their standard process from 5 um in 50 um thick silicon to 3 um in 50 um thick silicon. They see this soon moving to 2 um TSV in 30 um silicon which is an AR of 15. They see the standard interposer as 10 um TSV in 100 um thick silicon.

Ga Tech

Venky Sundaram of GaTech updated the audience on "Glass as an Ideal Material for Interposers, Packages and System Integration." The two interposer programs at GATech are focused on Low Cost Silicon Interposers and Packages (LSIP); (a) wafer based; (b) panel based and Low Cost Glass Interposers; (a) wafer based and (b) panel based
According to Sundaram glass has the following attributes:



Although glass does have its challenges:

They see two commercialization paths for glass. They eventually see glass wafers as 2X less cost and panel based glass as 10X based glass. 

AMKOR
Ron Huemoeller of Amkor looked at the migration of SoC to 2.5D. This can occur by breaking up large pieces of logic into smaller chips and mating on an interposer or breaking up a large monolithic die into functions and mounting on an interposer.



The former is exemplified by the now infamous Xilinx FPGA interposer development which Amkor is in the process of assembly scaling up.

Amkor sees 2.5D assembly challenges as:

          Die-Die X-Y Spacing
       –      Fillet sizes and pad metallurgy and materials

        Process assembly sequence ; Micro-join method

          Die-Die / Die-Substrate Joining
       –        Micro bump uniformity ; Method of Join ; Materials
          Thermal and Power Management
       –        Use of Lids, Stiffeners and Passives
       –        Underfill/Resin bleed, adhesive compatibility
       –       Process assembly sequence and materials
          Warpage Control
      –        Interposer warpage ; Substrate warpage
      –        Top die warpage – area density/distribution
          Intermediate e-Test Points
      –        Process assembly sequence

Assembly options include chip on substrate, chip on wafer and chip on chip all of which have pros and cons.
This was followed by the introduction to tree new temporary bonding solutions that Suss is working on with Dow Corning, Dow Chemical and 3M.
Jim Rosson of Dow Corning introduced a bi-layer, temporary bonding solution with a  room temperature de-bond. This silicone solution consists of a WL-30XX Release layer and a  WL-40XX Adhesive layer.
De-bonding consists automated mechanical de-bonding at room temperature on Suss de-bonders
The wafer is solvent cleaned on flex frame with compatible solvents and the carrier wafer is cleaned by standard processes.
Dow Corning is currently expanding their beta test program of this temporary bonding system.
Jeff Calvert introduced Dow Chemicals new BCB based temporary bonding solution XP-BCB.
AP-3000 adhesion promoter is spun onto the carrier wafer followed by  XP-BCB onto active die wafer.
The temp adhesive is cured at 210-230C for 10-30 min. De bonding is done mechanically at RT due to the lower adhesion of BCB to the device wafer.
Blake Dronen of 3M described their next generation Wafer Support System (WSS).
Gen II WSS uses conventional WSS materials but adds a high temperature thermoplastic primer layer to the substrate surface as a surface for the UV curable adhesive to bond, independent of the wafer surface passivation material.  Upon laser degradation the LTHC layer and removal of the glass , the WSS adhesive joining layer can be peeled off the primer surface in a conventional manner.  The  thermoplastic primer is solvent rinsed, eliminating any opportunities for residue or imparting bump damage by the peel step.  This process reportedly will be ready for release in 4Q.
An LTHC free process is also being developed to simplify glass recycle and reduce overall process cost by eliminating the debonder laser. It uses the conventional WSS materials but replaces the LTHC layer with a 100% solids UV curable "release layer" that is tuned to enable mechanical separation of the carrier at the interface.   The adhesive joining layer, when cured, becomes a single component with the release layer, peeled as one during debond. The LTHC free process is currently being developed and optimized.

Chris Rosenthal of Suss reported on their  high throughput modular equipment platform for temporary bonding and debonding. Adhesive thickness requirements depend on the application:
Suss has concluded that room temperature lift-off debonding is fundamentally less risky than thermal slide debonding.
Suss introduced the XBC300 Gen2 for Room Temperature Debonding and Cleaning.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…………………………….



IFTLE 110 Samsung Breaks Wall of Silence at DAC 2012

Design Automation Conference  2012

At the design automation conference in June Samsung, who has been on absolute lockdown when it comes to 3DIC materials leaking out of the company, opened the door…just a little bit with Samsung foundry indicating that they will be  ready to release 3D TSV Technology and Wide IO Memory Solutions "in early 2013."

Samsung’s message as to the major attributes of 3DIC vs a package on package solution (PoP) are summarized in the slide below:

(Click on any of the images below to enlarge them.)

In terms of wide IO memory solutions they report that they will have wide IO DRAM (Non-JEDEC type ball interface) ready for customer sample in early 2013 and will also have JEDEC standard wide IO DRAM2 .

 They claim that TSV PDK and Design Methodology has been proven for  32nm node:

Not a lot of info, but at least an official indication that Samsung foundry is getting ready and we should be seeing products in les than a year.

Larger Silicon Interposers are Coming

Up to now, silicon interposers have been limited in x,y dimension to the field size of the steppers being used or 35 mm sq. It is no coincidence that the size of the Xilinx FPGA interposer is 35 mm.

At the recent Semicon West, USHIO (link) introduced a large-field stepper lithography tool targeting interposer fabrication for 2.5D/3D semiconductor packaging applications.

Using a 70 mm projection lens the new litho tool is capable of a  50 x 50 mm field size. They are also indicating that by 2013 they will be introducing  100 mm projection lens, which will increase the field size to 70 x 70mm.  Overlay accuracy is reportedly less than 500nm. Alignment is IR transmission based.

 EVG Wafer Bonding System first to Pass Equipment Maturity Assessment at Sematech
EVG announced that its GEMINI Automated Wafer Bonding System has become the first product to pass a systematic, rigorous Equipment Maturity Assessment (EMA) implemented within SEMATECH’s 3D Interconnect program. The Sematech assessments are designed to determine equipment readiness for high-volume manufacturing (HVM).

The  EVG GEMINI exceeded Level 3 equipment maturity requirements — the highest assessment rating awarded before transfer of new manufacturing processes into pilot lines or HVM.  Temporary adhesive bonding, silicon fusion bonding, and metal thermocompression bonding processes have been investigated on 300-mm wafer bonding system installed at CNSE in Albany, New York.

SEMATECH qualified wafer bonding alignment accuracy of less than 500 nm exceeding the wafer alignment specs of the ITRS for 2018.  Sitaram Arkalgud, director of SEMATECH’s 3D Interconnect program indicated that EVG is the first company to pass ISMI’s Equipment Maturity Assessment methodology.

 For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………….

IFTLE 109 2012 IEEE VLSI Conference ; Lester’s cousin CFL Dies Prematurely

The  IEEE Symposium on VLSI Technology  is sponsored by the Electron Devices Society — ED and the  Solid-State Circuits Society — SSC. At this year’s conference, Micron gave further details on their hybrid memory Cube and TI detailed their studies on TSV induced stress on 28nm CMOS and Chuo Univ described a hybrid NAND + ReRAM SSD stack with better power consumption and product lifetime.

Hybrid SSD memory stack with ReRAM and TSV

Perofessor Takeuchi of Chuo Univ described a hybrid SSD architecture using ReRAM and high capacity NAND flash memory.

When SSDs are used for servers in financial institutions, performance is hindered and power consumption increased because random access is dominant. This causes data to get split up if the size of the data packets are not of the appropriate size (minimum for NAND is 16Kb). Takeuchi’s memory stack combines a NAND flash memory and ReRAM. ReRAM is used as both cache and storage memories. To overwrite a small amount of data in the NAND flash memory, software transfers the page of data to the ReRAM so that data is not fragmented in the NAND flash memory.

(Click on any of the images below to enlarge.)

A prototype, tested on an emulator, showed that compared with existing SSDs which only use NAND, the hybrid memory stack achieves an 11X higher data writing performance, 93% lower power consumption and 6.9 times longer product life. This assumed that the controller, ReRAM and NAND flash memory were connected by TSV. Although this has been hyped up by several reporters, we should note that it is possible to achieve almost the same results without using TSV. The major gain of using the TSV appears to be a 14% decrease in energy required to write as shown in the comparative table below.  

It is proposed that SSD in data centers would have to be changed out about 7 times less thus reducing expenses.

It should be noted that in order to use  the hybrid SSD architecture for different applications, it is necessary to change the controlling software algorithms.

Micron Hybrid Memory Cube (HMC)

We have previously discussed the fact that  Micron has created an industry group to collaborate on the implementation of an open interface specification for a new memory technology called the Hybrid Memory Cube (HMC). [http://www.hybridmemorycube.org/]

The HMC is a stack of multiple thinned memory die sitting atop a logic chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. The HMC requires about 10% of the volume of a DDR3 memory module. It is claimed that the technology provides 15X the performance of a DDR3 module, uses 70% less energy per bit than DDR3 and uses 90% less space than today’s RDIMMs. [see IFTLE 95 "3DIC – Time Flies When You’re Having Fun; Further Details on theMicron HMC…"; IFTLE 74 "The Micron Memory Cube consortium"]

The HMC device uses TSV technology and fine pitch copper pillar interconnect.  The DRAM logic, responsible for DRAM sequencing, refresh, data routing and error correction is placed in a  separate high performance logic die.  DRAM and logic are connected by thousands of TSV. The DRAM is a slave to the logic layer timing control.  The HMC was constructed with 1866 TSVs on a roughly 60um pitch. 

HMC electrical performance is are compared to other DRAM modules below.

TI Studies Impact of TSV Stress on Electrical Performance

They found that the impact of TSVs on surrounding Si is tensile but that a tensile etch stop layer (ESL) counters the impact of the TSVs on near-surface Si where devices are present. Also, insertion of compressive shallow trench isolation (STI) between the TSV and device will also act to buffer this impact.
They conclude that "…the electrical properties of N/PFETs between 4 and 16um of TSVs are negligibly impacted (less than 2.3%)…" and that For Wide-IO Memory-Logic interface applications employing a 40 x 50 um JEDEC TSV array, ESD and decoupling capacitors which do not contain N/PFETs can be placed immediately adjacent to TSVs such that CMOS logic circuitry does not require placement less than 4 um.
CFL Fails While Incandescent Lester Still Going Strong

When last we discussed our hero Lester the incandescent lightbulb [ see  IFTLE 98 "Lester the Lightbulb vs CFL and LED: the Saga Continues"] we found out that an actual calculation of the cost of various electrical functions in my household revealed that lighting was responsible for $4.31 per month (that’s for operating 30 bulbs) on your electric bill and that saving three-quarters of that by using Lester’s lighting cousins CFL or LED would therefore save you about $36/year (if you replaced all 30 bulbs), which is not enough to buy you 1 LED bulb. The CFLs whose price was now down to about $4 each (vs $0.25 for Lester)  promised 9.1 years of lifetime (at 3 hrs use per day). Our test bulbs (CFL and LED) were installed on 08/15/2011 [ see IFTLE 63 "Bidding Adieu to Lester Lightbulb"]. So…cousin CFL lasted less than 11 months (vs the promised 9.1 years). I guess you’d have to call this an "outlier"?
So cousin CFL operated 11 months saving me 1/30 of $4.31 or 14 cents / month or $ 1.54 in 11 months â??¦but remember the bulb cost me $3.97 . You can do the math. And remember since the CFL’s contain mercury, I’m now supposed to contact the EPA for proper disposal instructions (yeah right !) 
Cousin CFL and cousin LED promised me "hope and change"…  "to transform US power consumption as we know it today." So far, I’m down $2.43 and need to replace the bulb. Typical Govt BS !
I guess we can understand now why the Govt. got involved to ban poor Lester from the shores of the US. Would anyone actually buy these CFL or LED bulbs, unless they were forced to ?
Cousin LED is still burning bright as are all the incandescants that were started at the same time. Be assured we will keep you up to date on cousin LEDs health !
For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………………..

TI researchers have used NanoBeam Diffraction (NBD) to measure near-TSV Si strain in fully processed wafers. The electrical behavior of poly-SiON P/NFET transistors were characterized for full thickness wafers varying temperature, orientations and proximities to isolated and arrayed TSVs.
NanoBeam Diffraction measurements of Si strain within 5 um of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity greater than 1.5 um the impact of TSVs is negligible.

IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly

For those of you paying attention, you will have noticed that IFTLE has been stuck on 107 for nearly a month.

Has all progress stopped in 3DIC ?…..NO

Has all progress stopped in Advanced packaging ?……NO

Are there no new industry rumors  ?……NO

So whats up IFTLE where is our new information ???

It’s as simple as IT issues at the main SST server….boring ….but true.

Now that we are back up:

Lets catch up with technical highlights of the 2012 ECTC Conference.

Wafer Underfill processing (NCF)

Toray presented results of their study on suppressing wafer level underfill (WUF) material entrapment at copper pillar/Pad joints.  The NCF was laminated on the wafer and then the surface was planarized by the bit cutting technique.  Chips are then bonded to cu/Ni/Au pads.
(Click on any of the images below to enlarge them.)

When the top chip and lower chip are joined the temp must be raised slightly (sticking process) to get the NCF to flow together. This holds the two chips in place.
Factors Controlling NCF
Namics reported on the parameters controlling NCF performance. One of the main issues with NCF has been voiding. Namics reports that one of the causes of voids is captured air which is generated when an IC connects to NCF. This relates to the flow of resin. They could decrease the voids by optimizing the minimum melting viscosity. Another type of void comes from volatilization of gases may occur from organic materials in the structure such as the substrate. They found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. They also optimized the minimum melting viscosity, curability and flux-ability for good interconnection. When the minimum melting viscosity is too high, the connection is poor. When cure speed is too high, solder melting is blocked. They attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled.
Hitachi Chemical (HC) also reported on their attempts to optimize their NCF products. HC reports that The major requirements for processability are (1) NCF can be laminated to the bumped wafer without air trapping around the bumps and dicing lines; (2) In the process of back grinding, the wafer laminated with NCF can be grinded back side (opposite side of NCF) to thinner wafer without damage such as wafer crack and delamination of NCF; (3) the alignment mark or dicing pattern on the wafer can be recognized through NCF; (4) the NCF-laminated wafer can be diced without damage such as chip crack and delamination of NCF.
Issues and solutions are listed in the table below:

Compression Molding Compounds for Fan out WLP and MUF

Hitachi Chemical (HC) reported on their studies on using solid molding compounds for fan out WLP and molded underfill (MUF) . Currently, liquid molding compounds are mainly used for eWLB as encapsulant. Liquid molding compound issues include cost, warpage and high die stand-off caused by molding shrinkage.

HC shows that solid molding compounds has better wafer warpage results that liquid wafer warpage. Package warpage was almost flat over the temperature range tested.
High filler content is necessary for such molding compounds. Lower temp curing is also useful to lower warpage due to reduction in thermal shrinkage. Post mold cure is 150C for 1 hr.
Using solid molding compounds for MUF, flip chips can be molded/underfilled at 130 C / 250 sec.
Koyanagi-san and co-workers at Tohoku Univ have looked at the sue of NCF and compression molding for 3D integration using self assembling technology. They examined chips with 20 um pitch Cu-SnAg microbumps with bump height ~  6 um ( 3 um thick Cu and 3 um thick SnAg). The chips were self assembled face up on a carrier wafer. Then, the chips were transferred to the corresponding target wafer with microbump-to-microbump bonding through a NCF. The strength of temporary bonding was lower than the microbump bonding through the NCF, and thereby, the chips were removed from the carrier wafer and successfully transferred to the target wafer. After that, the target wafer having the chips bonded upside down on the wafer was packaged by a compression molding technique with a granular resin that covered all over the self-assembled chips to planarize the chip-on-wafer structure. Finally, the chips and the resin were simultaneously thinned from the backside of the chips.

For all the latest on 3DIC and advanced packaging (hopefully in a week or less) stay linked to IFTLE…………….

IFTLE 107 2012 ECTC Part 1 Committees and Awards

The 2012 IEEE ECTC conference was held, as it always is, over Memorial Day weekend this year in San Diego. Attendance was an outstanding 1200+.

The executive committee, which is responsible for all content,  is shown below. (Click on any images to enlarge them.)

[Back row: Steve Bezuk, Pat Thompson, Wolfgang Sauter, Beth Kesser (winner of the IFTLE  name the packaging experts contest !), Bill Moody, Sunil Peking, Alan Huffman, Tom Reynolds                          Front row: Eric Perfecto, Jean Trewhella, Kitty Pearsall, Dave McCann, Rajen Dias, Lisa Renzi]
The committee gave special thanks to two wives who have been helping with registration and anything else the conference needed for over a decade — Lynn Reynolds and Nadine Bezuk:
IEEE CPMT AWARDS
An important part of every ECTC is the IEEE CPMT awards ceremony. This year’s CPMT officers include : Ricky Lee (President); Jie Xue (Technical VP); Jean Trewhella (VP Conferences); Kitty Pearsall (VP Education); Wayne Johnson (VP Publications) .
The theme of this year’s meeting was "going on safari" (I assume tied to the San Diego Zoo) so that’s a safari hat on Ricky’s head in case you’re wondering.
This year’s award winners included:
 IEEE CPMT Field Award to Dr. Mauro Walker (Motorola – Retired)

As IFTLE has described previously, the Field award is the highest level award in IEEE for any given division, so this is the highest award available in the world for IC packaging. This year’s recipient Mauro Walker has had a long career of accomplishment in the advancement of electronic manufacturing and manufacturing technology in industry, academia and professional societies. His leadership in Motorola in the 1970s and 1980s drove the component packaging miniaturization that was necessary for portable communications such as cell phones pagers and two way radios. He established advanced manufacturing technology centers within Motorola which developed many innovations for high speed surface mount assembly.

He is the previous recipient of the IEEE’s Special Manufacturing Technology Award and the Society for Manufacturing Engineers’ "Total Excellence in Electronic Manufacturing Award." Walker is an IEEE fellow and founder of the IEEE International Electronic Manufacturing Technology Symposium (IEMT).
Having worked on technology introduction programs with Motorola during this time, I can tell you that this is a well deserved award. There was no one introducing technology like bumping and chip scale packaging into consumer products better or earlier than Motorola in those days.  Congrats Mauro!
IEEE CPMT Dave Feldman Award to Dr. Phil Garrou (Microelectronic Consultants of NC)

The Dave Feldman award is for extended and extraordinary leadership in the IEEE CPMT society. It is named after Dave Feldman who was a key player in Bell labs in the 1950 and 60s and started the ECC (the predecessor  to ECTC) in 1950. I am humbled to say that this year’s winner was yours truly. After the luncheon, a bright eyed 20 something engineer came up to me and asked exactly what you had to do to win an award like this, i.e what made me stand out from the other folks in a position of leadership in this large organization. He probably expected some quick cliche answer, but instead I bent his ear with some philosophy. But seriously, the two actions that I am most proud of during my Presidency have to be (1) installing 1 man one vote on a global basis. While Rao Tummala certainly drove the global expansion of the CPMT society during his 4 years, when I took over as President our board of Governors still had a European and an Asian representative which the rest of the US elected body "selected" to represent the non US members. After developing enough internal consensus,  I pushed to have non US members select only their own representatives and to have each region represented based on the number of members in those regions. Seems logical enough, but somebody had to actually push to get it done and that was me. FYI – it is no coincidence that our last president was from Germany and our current president is from Hong Kong – we are now truly a global society which was Rao and my original dream. PS – growth in both these areas continues – this year both Europe and Asia representation went up by one BOG member while the US went down by two. (2) the complete ownership of the ECTC. Since I started going to the ECTC in the mid 1980s, I was always confused by the co-ownership (IEEE CPMT and EIA) that existed. As I took over as President this did not clarify itself, but rather became more and more confounding. ECTC was, and is the flagship conference of the CPMT, but it was only partially controlled by our IEEE organization. So my second "quest" was to buy out the EIA. I was not able to conclude this during my term, but after convincing incoming President Bill Chen of the logic in this, we moved forward during his presidency to amicably conclude this transaction. That’s it, although it may seem trivial to you the reader, that’s what I think my lasting stamp on the organization will forever be. 

Sustained Technical Contribution Award – Tseung-Yuen Tseng (Chiao-Tung Univ Taiwan)

The sustained technical contribution award went to Tseung-Yuen Tseng of National Chiao-Tung Univ in Taiwan where he is University Chair Professor in the Department of Electronics Engineering and the Institute of Electronics. Dr. Tseng’s professional interests are electronic ceramics, nanoceramics, ceramic sensors, high-k dielectric films, ferroelectric thin films and their based devices, and resistive switching memory devices. He has published over 300 research papers in refereed international journals. He invented the base metal multilayer ceramic capacitors, which have become large scale commercial product. Dr. Tseng was elected a Fellow of the American Ceramic Society in 1998, IEEE Fellow in 2002 and MRS-T Fellow in 2009.

Exceptional Technical Achievement Award – Andrew Tay – National Univ of Singapore
Electronics Manufacturing Technology Award – Chin Lee – Univ of California
Outstanding Young Engineer Award – Mudasir Ahmad – Cisco
IEEE Fellows – Mao Jun Fa (china), Yogendra Joshi (USA), Pradeep Lall (USA), Mike Li (USA), Anthony Oates (Taiwan), William Palmer (USA), Enboa Wu (China)
For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………..

IFTLE 106 2012 Symp on Polymers for Microelectronics

This was the 15th year that polymer suppliers and users have met in Wilmington DE to discuss the latest advances in polymeric materials. All of the big boys were there including : HD MicroSystems , Dow, JSR, Asahi Kasei, Toray, Nippon Kayaku (MicroChem), AZ and Hitachi Chemical.

Certainly the most interesting bit of information that I learned about a materials supplier was that Alpha started its business in 1704 making cannon balls… cannon balls to solder balls — now that’s a roadmap for miniaturization!

Certainly the main theme, as you shall see below, was the development of low curing temperature polymers that could come close to matching epoxies curing temp (i.e ~175C) while maintaining improved thermal and mechanical properties.   

My plenary presentation was based on the new Yole report "PolymericMaterials for 3DIC & WLP Applications"

Basically over the last 50 years the industry has developed five  basic chemistries for the microelectronics industry. In chronological order they would be epoxies, siloxanes, polyimides, BCBs and PBOs.

(Click on any of the images below to enlarge them.)

If we look at the properties that are important to all or most functions / applications we find 4 broad categories including electrical, mechanical, thermal and misc. (other).

The half dozen key functions that we want these polymers to fill and the seven wafer level applications that we are looking to use them in are depicted below.


Yole projects a 26% CAGR for WL applications over the next few years which will expand the current market to near $1B with significant expansion of applications other than FC bumping.
Since new materials take decades and 10s of millions of dollars to develop, those in the business of wafer level packaging over the next 5-6 years will basically have products from these 5 chemistries to serve the functions for the listed applications.  

The theme for permanent dielectric suppliers at this meeting seemed to be positive tone aqueous developable dielectrics with sub 200C curing temperatures and resultant low stress. The newer packaging scheme such as eWLB require this evolution in dielectric materials because the wafer substrate is epoxy based and  cannot survive the processing temperatures needed to cure polyimides or most PBO and BCB materials. Also, ICs with embedded memory are very sensitive to process temperatures and survivability drops dramatically with increase in temperatures. Lastly, advanced technology nodes such as 32 and 22 nm use lower-k dielectric materials, which are sensitive to the high stresses generated by higher curing temperatures.
Toray is offering a LT series low-temperature curing,  positive-tone photosensitive PI coating with a 170- 200C curing temp and resultant 13 MPa thermal stress. With a tensile strength = 100 MPA, elongation of 30% and Modulus of 2.5 GPa . While the residual stress is reported as 13 MPa, the CTE is troubling at 70 ppm. Asahi Kasei is offering  BM series PIs which reportedly can cure as low as 200C with a Tg of 220C, a CTE of "50-60" and a stress of 19 MPa . HD Micro reported on a new PBO, 8850, with reported better chemical resistance, which can be cured at 250C. JSR reported on their WPR series dielectrics which for positive tone are cresol based with rubber reinforcement. While they can be cured at 200C and have low residual stress ( 20 MPa), their tensile strength (80 MPa) and elongation (7%) are low for permanent dielectrics.  Dow chemical reported on their aqueous developable P6505 BCB which cures as low as 180C (3 hrs) with a resultant stress of 25 MPa. Most of the properties look like the BCB 4000 series with a notable exception that water absorption has risen from 0.2% to 2% for the new version. 
Toray also introduced a siloxane product to replace acrylics for optical applications such as CMOS image sensors, LCD and OLED displays and solar modules. It is 99% transparent at 400 nm and is much more thermally stable than the typical acrylics.
As a general comment, all of these materials are beginning to look like one another which may or may not be a good thing for the industry. As IFTLE has said many times before, you must determine what properties are most important for your application and choose your dielectric accordingly. 
Next week we begin our coverage of the ECTC conference. For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………….


IFTLE 105 TSMC Tech Symp; UMC Investment; Latest rumors on IBM, Intel, Samsung and Apple

TSMC Tech Symp

At the 2012 TSMC Tech Symp in April they revealed Reference Flow 12 which shows 2.5/3D firmly entrenched in the TSMC roadmap.

Recent blogs have discussed TSMCs move into the 3D and advanced packaging area. [see IFTLE 94 “Experts discuss InterposerInfrastructure at IMAPS DPCand IFTLE 102 “3.5D interposer technology could somedayreplace PCBs" — TSMC’s Doug Yu” ]

Indeed TSMC isnow showing slides where only the memory and substrates are coming from external sources, making them a turnkey solution for what they are now calling 3.5D [link].

UMC stays in the game
In IFTLE 88 “Apple 2.5D Rumors; Betting the ranchâ??¦” we drew an analogy of putting new fab production in place to a poker game in the Wild West – or betting the ranch. Well, the recent announcement by UMC certainly had them tossing their chips into the center of the table matching the recent capacity announcements by TSMC and Global Foundries. The UMC 300mm Fab 12A Phase 5 & 6 in Tainan will extend 28nm production. P5 & P6 will provide advanced 28nm, 20nm, and 14nm capacity, and is scheduled for equipment move-in during the second half of 2013. Total cleanroom area is 53,000m2 and will be capable of 50K wafers per month, bringing total monthly design capacity for Fab 12A to 130K wafers. With the planned P7 & P8, the eight phase fab complex will have a total design capacity of 180K wafers per month.
Cumulative capex for UMC’s Fab 12A phases 1-4 is projected at $ 8 billion, with P5 & P6 to add nearly $ 8 billion more. There are further plans for P7 & P8. As we said earlier, only the big time players are sitting at this table. With such investments, UMC is certainly showing that they intend to stay in the game.
 They also announced continued activity in “â??¦ BSI CMOS image sensor, 2.5D interposer, and 3D IC TSV to provide a truly comprehensive, leading foundry technology platform”  
Rumors from the ECTC
The IEEE ECTC meeting was last week and for those of you who are unaware, it is the number one show for advanced packaging in the industry. 2.5/3D has grown steadily at this conference and it now appears to be nearing 50 % of the ECTC content [ 50% of 6 parallel sessions for 2.5 days] . There were no major announcements at the meeting, but there were some interesting rumors. My filtering criteria is that I must hear the rumor at least twice from separate sources before I report it on to you.  None of these could be substantiated by the parties involved, but that is not surprising.
 IBM Power8 processor
IFTLE has reported before that rumors were swirling that a future generation of the IBM power chip processor would be using a 2.5D interposer configuration. Very strong, multisourced rumors at ECTC persist that the Power8 is currently undergoing testing in IBM servers and we could be hearing about this major interposer announcement “soon” .
 Intel
If your like me, you have been waiting for 5+ years for the imminent 3D announcement from Intel. Recall that we have been told that the technology is ready but it would be up to the product departments as to when to introduce it. Well, not so good news here. The rumor going around is that we are probably looking at 2017 when 450 is introduced. (Don’t shoot me I’m just reporting the rumor. ) If anyone from Intel would like to deny this and give IFTLE better information please send me an email.
Apple / TSMC / Samsung
Back in IFTLE 88, “Apple 2.5D rumorsâ??¦â??¦” (which I’m told was the most read IFTLE blog of all time) we discussed the fact that TSMC and Samsung are in competition for the next generation , the A6, processor for the Apple iPod, iPad etc.. Although everything is hush, hush, it is clear that TSMC is at least developing prototypes based on their interposer technology. It is unknown whether Samsung is doing the same (but we can hope so).  Two opposing  rumors were making the rounds at ECTC. Rumor 1 had Samsung about to make a 2.5/3D announcement, but rumor 2 had Samsung developing an “unknown technology” that negated the need for TSV and leading them to the conclusion that 2.5/3D would not be needed in the future. The Samsung clamp down on the release on any information on 2.5/3D remains â??¦hermetic . Yes these could in fact be the same rumor, but I, for one, hope not.
Lots more from the ECTC over the next few weeksâ??¦â??¦â??¦â??¦â??¦..
For all the latest on 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦.

IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper

Continuing with key presentations from the 2012 IMAPS Device Packaging Conference in Ft McDowell AZ.

Tezzaron Process Technology
Bob Patti showed off two Centip3De, a 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM from the Univ of Michigan and the 3-D MAPS, a massively parallel processor using 64 custom cores stacked with a block 256 kilobytes of scratch pad memory from Ga Tech. For more details on these see IFTLE 93, "2.5/3D at the 2012 ISSCC".

(Click on any of the images below to enlarge them.)

Amkor Discusses 2.5/3DIC

Amkor’s Ron Huemoeller reported that 3D vertical stacking is:

memory and application processor driven
– today focused on 28 nm CMOS and moving to 22 nm
– application processors are near exclusively moving to OSAT finished wafer process flows
Whereas 2.5D Interposers are:

–  network, CPU and GPU driven
…….. mother boards reduced from 10 to 6 layers
…….. reduce chip mask layers
…….. smaller x, y dimensions
– focused on large package bodies (40 -90 mm , near retical sized Si)
  both foundry and OSAT wafer flow processes being used
 

He sees both dis-integration of large logic blocks and separation of functions

– allows focus of specific functions which require  leading process nodes
– improves wafer yield
– reduces time to market
– reduces mask layer count at advanced process nodes

Concerning the interposer supply chain:

– laminate (which can theoretically be delivered in large panel format (i.e. 500 x 500 mm ) are being investigated by several "elite substrate manufacturers" [ Unimicron, DNP, Shinko, Kyocera]. Limited to 8 um L/s and 40 um vias on 85 um pads today. 5 um l/s will require stepper and better resists which change the economics. 5 um L/S thought to be many years away. Latency issues will limit adoption as will limitations in va/pad design rules.

– glass can be delivered in large panel or wafer format. Several glass companies [Hoya, Corning, AGC] are investing in capability to support glass interposer technology. Glass faces challenges for CMP / damascene processing.

– silicon in 200 or 300 mm several companies supporting silicon interposers in idle foundry space on legacy node technologies. Amkor finds only 3 foundry players committed to delivering "fine featured" interposers [ TSMC, GF, UMC] with TSMC the only one currently delivering in any quantity.

According to Amkor several foundry sources are interested in manufacturing Si interposers and a couple are already delivering fully functional wafers. Currently design rules  "are aggressive" i.e. less than 2 um L/S and 5 um vias.

Amkor indicated that the predominant interposer designs are what IFTLE has been calling "fine featured" as follows:

When looking at TSV products expected to enter the market in the next few years, Huemoeller offered the following roadmap.

TI Promotes Cu WB

TI has recently announced that all 7 TI internal assembly and test sites are now converted to Cu WB. 6.5B devices have been shipped in Cu WB with conversions continuing. TI which started their Cu WB studies in 2003 are in HVM at the 65 node and have qualified down to the 45 node. 50% of all their interconnect wire is now Cu.
Analog, wireless and embedded products in BGA and leadframe packages are all qualified. Cu shows less wire sweep during package molding and since it has better inherent thermal conductivity it shows better battery life. Next TI will be looking at "high rel" applications such as automotive, military and down hole drilling with Cu wirebonding.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………….