IBM water cooled 3D IC At the recent CeBIT Fair in Hanover Germany, IBM CEO Sam Palmisano presented German Chancellor Merkel with a prototype of the IBM 3D Chip Stacking Project developed at IBM Research – Zurich. Merkel asked him, "Did you take that from Intel?" Palmisano reportedly reply, "No, ours are better”.

[Merkel gets points for pushing IBMs hot button (probably unknowingly) and Palmisano gets points for a sharp response under pressure !]

Their 3D chip stacks are cooled by 50 um micro channel cooling technology . Such liquid cooling reportedly reduces power consumption or the normal cooling fans. The cooling technology was developed by IBM together with the École Polytechnique Federale de Lausanne and the ETH Zurich within the scope of the European CMOS AIC project. Dr. Bruno Michel manages the Advanced Thermal Packaging group at IBM Research – Zurich. The group has pioneered energy-efficient hot-water-cooling and the concept of a zero-emission data center.


The first goal is reportedly to directly stack memory onto the processor. IBM’s 3D technology is reportedly scheduled to appear in its upcoming Power8 processor, planned for 2013, using 28 or 22nm process technology. While the technology is reportedly being transferred to iDataPlex servers, it is expected that it will be a few more years before it is fully ready for production.

We first started tracking TSMC’s San Jose spring technical symposium in 2008 when TSVs first appeared on their roadmap [ see PFTLE 30, “Foundry TSVs Are a Comin’ – TSMC Makes Their Play for a Bigger Portion of the Pie” In 2009 they reconfirmed their plans for fab based TSV . [ see PFTLE 73, “ TSMC Reconfirms Plans for Fab-Based TSV “]. At this years meeting, last week, Sr VP of R and D Shang-Yi Chiang indicated that they would initially offer silicon interposer technology, which they are currently sampling and plan to have in full production by late 2012.


Perhaps more interestingly, TSMC updated the audience on a theme they first brought up in 2008 when they suggested that they might “in the future” be after a bigger portion of the packaging pie. We recently reported that TSMC would enter the interposer technology and that in fact they were delivering the interposers to Amkor for assembly already bumped, rather than have Amkor do the bumping [ see IFTLE 43, “IMAPS Device Packaging Hilights – 3DIC”] TSMC first put in bumping capacity for 200 mm wafers in 2001 when they installed 15K wafers/mo capacity for business with Altera. They have had limited bumping and WLP capacity since then although they have mainly used their OSAT partners for such operations.


Now TSMC is expanding its bumping efforts. They will ramp up a new 200,000 to 250,000 wafers per month bumping facility in Tainan, are qualifying 100-micron bump pitch lead-free and new copper pillar bump technology at the 28-nm node and are ramping up 28 nm WLP qualification by December targeting the mobile market. Although claiming to still be a “front end company” it is clear to IFTLE that TSMC is making inroads into the packaging business.


UMC Announces 3D Equipment Aquisition


In mid 2010 UMC announced their 3DIC alliance program with Elpida and Powertech Technology (PTI). [see IFTLE 8, “3D Infrastructure Announcements and Rumors” ]At that time, UMCs CTO reported that they expected to be sampling 3D IC solutrions using their 28 nm technology “..in mid 2011) with production slated for 2012. In keeping with these previous announcements, UMC has just announced that they have acquired $19 MM worth of 3D TSV production equipment from Hong Bao Technology (a 73% owned subsidiary)


CMOS image sensors continue to overtake CCD

i-Supply reports that in 2011 CIS ( a key applications area for TSV and in the future 3D IC stacking) will surpasses CCD by > 10:1 in both units and revenue.

CMOS image sensors for digital cameras, the last bastion of CCD technology, are expected to exceed those of CCD devices in 2013. CMOS sensor advantages include lower power consumption, reduced cost and circuit integration. The lower power consumption of CMOS sensors yields longer battery life. CMOS sensors also allow for the possible inclusion of on-chip peripheral circuits, increasing the integration of electronics and reducing the size of DSCs. CMOS sensors also support backside illumination technology (BSI), enabling better quality imaging in low lighting conditions.


CMOS image sensors shipments for DCS are projected reach ~ 71 MM units, up from ~ 30MM in 2010. CCD shipments are expected to decline to ~ 67 million units in 2013, down from ~ 94MM in 2010. By 2014, more than 85MM CMOS are expected compared to 51MM for CCD.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦..






DATE (Design, Automation, Test – Europe) was held in Grenoble Fr March 14-18.


Penn State
Yuan Xie from Penn State and IBM collaborators from the System and Technology Group took a look at 3D IC thermally-aware bus optimization.
Given that :
– TSVs are clustered for both signal and power delivery
– TSVs are duplicated (redundancy as high as 20x) for higher reliability and higher yield
What is the impact of these TSV clusters on 3D thermal profile ?

The Tech Design Forum ( formerly EDA Tech Forum), has been restructured to focus on fast-growing technology markets in specific regions and has added panel discussions of industry and media experts, as well as technical sessions. They will hold the following meetings in 2011:


March 10 – Santa Clara; April 11 – Tel Avivl; July 20 – New Delhi; July 22 – Bangalore; August 25 – Tokyo; August 31 – Shanghai; September 6 – Beijing; September 8 – Hsin-Chu; September 8 – Santa Clara.


The March 10th Tech Design Forum "EDA Edition" focused on IC Design and Verification, exploring ecosystem networking and increasing competiveness in IC and system product development. The keynote by Dr. Mario Paniccia, Intel Fellow, titled "Bridging Photonics and Computing" discussed recent advances in silicon photonics, including the first silicon photonics optical link operating at 50 Gbps, the scalability of this technology and its potential applications.


Intel asks the question “With all the data that is moving and will need to be moved, how do we connect all these devices?

We have previously discussed what appears to be the planned move of Applied Materials into the IC packaging space [ see PFTLE 72, “Samsung 3-D ‘Roadmap’ That Isn’t”; PFTLE 41, “3D Integration Stays HOT at Semicon West” ]


Applied Materials has now signed an agreement with Singapore’s Institute of Microelectronics (IME) to set up a Center of Excellence in Advanced Packaging in Singapore. The Center, to be located at Singapore’s Science Park II, will focus on new capabilities in advanced packaging. When finished, this advanced semiconductor packaging RandD facility will enable IME to support Applied Materials’ product development initiatives. The Centre will have a full 300 mm line of Wafer Level Packaging (WLP) and 3DIC processing equipment and will conduct research in semiconductor hardware, process, and device structures.


Applied expects many advanced logic devices at the 40nm and below technology nodes to be packaged at the wafer level. Russell Tham, Regional President – South East Asia, said, “This collaboration is to â??¦. (bring) our development activities closer to our customers in Asia.”

For all the latest in 3D IC and advanced packaging stay linked to IFTLE……




DATE (Design, Automation, Test ��? Europe) was held in Grenoble Fr March 14-18.


Penn State
Yuan Xie from Penn State and IBM collaborators from the System and Technology Group took a look at 3D IC thermally-aware bus optimization.
Given that :
– TSVs are clustered for both signal and power delivery
– TSVs are duplicated (redundancy as high as 20x) for higher reliability and higher yield
What is the impact of these TSV clusters on 3D thermal profile ?

The Tech Design Forum ( formerly EDA Tech Forum), has been restructured to focus on fast-growing technology markets in specific regions and has added panel discussions of industry and media experts, as well as technical sessions. They will hold the following meetings in 2011:


March 10 – Santa Clara; April 11 – Tel Avivl; July 20 – New Delhi; July 22 – Bangalore; August 25 – Tokyo; August 31 – Shanghai; September 6 – Beijing; September 8 – Hsin-Chu; September 8 – Santa Clara.


The March 10th Tech Design Forum "EDA Edition" focused on IC Design and Verification, exploring ecosystem networking and increasing competiveness in IC and system product development. The keynote by Dr. Mario Paniccia, Intel Fellow, titled "Bridging Photonics and Computing" discussed recent advances in silicon photonics, including the first silicon photonics optical link operating at 50 Gbps, the scalability of this technology and its potential applications.


Intel asks the question ��?With all the data that is moving and will need to be moved, how do we connect all these devices?

We have previously discussed what appears to be the planned move of Applied Materials into the IC packaging space [ see PFTLE 72, ��?Samsung 3-D ��?Roadmap��? That Isn��?t��?; PFTLE 41, ��?3D Integration Stays HOT at Semicon West��? ]


Applied Materials has now signed an agreement with Singapore��?s Institute of Microelectronics (IME) to set up a Center of Excellence in Advanced Packaging in Singapore. The Center, to be located at Singapore��?s Science Park II, will focus on new capabilities in advanced packaging. When finished, this advanced semiconductor packaging RandD facility will enable IME to support Applied Materials��? product development initiatives. The Centre will have a full 300 mm line of Wafer Level Packaging (WLP) and 3DIC processing equipment and will conduct research in semiconductor hardware, process, and device structures.


Applied expects many advanced logic devices at the 40nm and below technology nodes to be packaged at the wafer level. Russell Tham, Regional President – South East Asia, said, âÂ??Â??This collaboration is to âÂ??¦. (bring) our development activities closer to our customers in Asia.âÂ??Â??

For all the latest in 3D IC and advanced packaging stay linked to IFTLE……




I recently read of the passing of Dimitry Grabbe and it saddened me deeply. As time passes those that preceded us are often forgotten and their accomplishments overlooked.


The Grabbe obituary indicated that he was 83 and had most recently taught at Worchester Polytech in Mass. He was responsible for more than 500 patents in the areas of machine design, semiconductor packaging, electronics assembly and optoelectronic connector design. Dimitry joined AMP in 1973. He was recognized by AMP with a Lifetime Achievement Award, and by the American Society of Mechanical Engineers, which chose him for its Leonardo da Vinci Award. An IEEE Life Fellow, Grabbe was also a fellow of IMAPS.
In 2007 Grabbe was the fifth recipient of the IEEE Components, Packaging, and Manufacturing Technology award. His citation reads: "For contributions to the fields of electrical/electronic connector technology, and development of multi-layer printed wiring boards."


Dimitry was part of the group Microelectronic Interconnect Greats that lived in the greater NYC metropolitan area in the days before Silicon Valley. When I was still young and impressionable, Dimitry was already a highly respected “leader of the Pack” along with close friends Jack Balde of ATT (who passed away in 2003) and George Messner of AMP AKZO (who passed away in 1996). With Bell Labs in its “hey day” and IBM Yorktown up the river, some would say that metropolitan New York was the center of the microelectronics universe.


What separated these three from the rest of the professionals in the area was that they always had time for discussions with younger colleagues like myself. They understood their responsibility to set up and lead meetings on the topics of the day and to help generate the next generation of technical leaders. They were true scientists who had little respect for “managers” and were always ready to share information with all those who would listen. If there was a rumor anywhere in the industry they knew it !


Some of the greatest meetings I ever went to were local meetings held at the old IEEE headquarters near the UN building in NYC . Grabbe and Messner and Balde were always there learning new things and sharing what they knew. A native New Yorker myself, I was living in Boston at the time and would make up excuses to get to NY to attend these meetings and be around these giants. Grabbe kept a museum of electronic products in his barn in PA. Supposedly he had things in there that no other museum had. Professionals from all over the country were sending him electronic devices knowing that he would take care of them in his personal “museum”. I truly hope all of that has not been lost ! Maybe an IEEE museum in his name would be appropriate? Many colleagues knew that both Messner and Grabbe had immigrated from the old Soviet Union after WWII. Grabbe related to me many times that he had had some problems with the KGB and spent the rest of his life “packing” â??¦not packagingâ??¦but "packing" in the urban context of carrying a handgun in a shoulder holster. For those who did not know this – it was the reason he always kept his jacket on !


In the early 1992 I got the opportunity to edit the first MCM textbook “Thin Film Multichip Modules” with Messner, Balde and Motorolas Iwona Turlik. A great learning experience on how to assemble and share information. (Little did I know what I would be doing later in life)

Grabbe and Balde also share the fact that they have received the IEEE CPMT Society medal, the highest honor available for packaging and interconnect practitioners. It’s worth looking at the list of winners of this award since these are truly the giants in our packaging field.


2004 – Jack Balde – ATT


2005 – Yutaka Tsukada – IBM


2006 – C. P. Wong – ATT, Ga Tech


2007 – Dimitry Grabbe – AMP


2008 – Paul Totta, Karl Puttlitz – IBM


2009 – George Harman – NIST


2010 – Herbert Reichl – Fraunhofer IZM, Berlin


2011 – Rao Tummala – IBM, Ga Tech


If anyone reading this does not know who these men are or why they won these awardsâ??¦well you’ve got some reading to do !


For all the latest on advanced packaging and 3D IC technology stay linked to IFTLEâ??¦

JEDEC ANNOUNCES 3D-IC STANDARDS DEVELOPMENT
JEDEC has recently summarized their ongoing standards development work related to 3D-ICs. The following JEDEC committees and task groups are engaged in developing 3D-IC standards:
Memory:
– the Solid State Memories Committee (JC-42) has been working since 2008 on definitions of standardized 3D memory stacks for DDR3 . Future DDR4 standards will be implemented with 3D input.
– the Multiple Chip Packages Committee (JC-63) is currently developing mixed technology, pad sequence and device package standards.
– a Low Power Memories Subcommittee (JC-42.6) task group is developing standards for Wide I/O Mobile Memory with TSV interconnect stacked on SoC Processors.
Quality
and Reliability:
– the Silicon Devices Reliability Qualification and Monitoring Subcommittee (JC-14.3) is working on reliability interactions of 3D stacks and has released JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions.
– reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.
Packaging :
– the Mechanical Standardization Committee (JC-11) has been working since 2010 on Wide I/O Mobile Memory package outline standardization, including a task group focused on design guide creation.
JEDEC invites interested companies and organizations to participate.
I have previously expressed my concerns over the lack of transparency in JEDEC standards due to their self imposed rule forbidding revealing authorship [companies and /or individuals] up the standards. [ see PFTLE 128 “3D IC Standardizatio Begins” ] Those concerns still stand.

Hynix Semiconductor Joins SEMATECH’s 3D Interconnect Program
Hynix the last top 5 DRAM to not have announce plans for 3D IC has become a member of SEMATECH’s 3D Interconnect program. Dr. Sung Joo Hong, Head of the R and D Division of Hynix Semiconductor commented that "3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction,â??¦.by joining SEMATECH’s 3D Interconnect program and collaborating with industry-leading partners, we expect to play a critical role in accelerating the commercialization of wide I/O DRAMâ??¦” Hong reported that Hynix and SEMATECH will address the commercialization challenges facing the industry as it commercializes wide I/O interface structures using TSVs in high volume manufacturing in the next two years.Hynix will be working with IBM, GlobalFoundries, Toshiba, Samsung, Applied Materials, Tokyo Electron, ASML and Novellus as part of the SEMATECH program.

IC Power Rankings from IC Insights

Semiconductor industry capital spending is becoming more concentrated, with a greater percentage of spending coming from a shrinking number of companies. As a result, IC industry capacity is also becoming more concentrated, and this trend is especially prevalent in 300mm wafer technology.


IC Insights has created a “Power Rating” which is determined by each company’s 300mm wafer capacity and its rank in capital spending.

Overall, IC Insights believes that the top-10 companies in the “Power” ranking will be the primary drivers in adding capacity over the next few years. GlobalFoundries and TSMC get a boost from their currently aggressive capital spending plans and are very likely to add a significant amount of 300mm capacity over the next few years. Among companies ranked between 11 through 22 Renesas, IBM, TI, ST, and Fujitsu are moving to or continuing with a fab-lite strategy. These five companies appear unlikely to add new 300mm capacity in the future. Powerchip, SMIC, ProMOS, Winbond, and Xinxin appear limited by financial where-with-all (e.g.,) or a lack of desire (e.g., Rohm and Panasonic) to add significant amounts of 300mm capacity to produce leading-edge digital ICs.

With only ten major players in the 300mm capacity space, the customer base for leading-edge IC production equipment has become very narrow. It is likely that IC equipment and materials suppliers will be focused on these 10 companies in the future.


For all the latest in 3DIC and advanced packaging news and conference updates stay linked to IFTLEâ??¦

Ft McDowell AZ was once again the site of the IMAPS Global Business Council Meeting and Device Packaging Conference. For a report on last years conference see PFTLE 123,125,126 [link]

Brandon Prior of Prismark Partners pointed out that 3D TSV will be competing with the incumbent mobile phone 3D packaging solutions, PoP and PiP. PoP lacks the ability to interconnect more than 200 – 300 I/O from memory, but offers ease of test. TSV will offer higher speed and many more connections .


James Malatesta of Micron presented his perspective on the work of JEDEC committee JC63, the multichip package committee. First PoP changed the landscape as logic suppliers realized that standard top package “memory modules” were requuired for multiple industry supply sources. He also gave an interesting comparison of low power DDR2 [LPDDR2] vs the wide IO TSV technology that is expected to replace it [see IFTLE 40, “Samsung Wide I/O DRAM for Mobile Productsâ??¦”]

Sitaram Arkalgud, Director of Sematechs 3D IC program described their current acivities on the U Albany campus. They view their role as helping to :

• Develop robust technology solutions
• Assist member company implementation
• Drive convergence of the materials/equipment solutions


Sematech has examined the current 3D TSV tool set and come to the following conclusions:

In Matt Nowak, Sr Director at Qualcomm, presentation he asked the question “since the key attributes of 3D IC are: (1)Performance enhancement; (2) Improved power efficiency; (3) Form factor miniaturization and (4) Cost reduction can 3D IC take the place of scaling as CMOS technology appears to be slowing down or stalling out” . He concludes:

• If performance enhancement and power reduction are the primary motivation, then TSS opens new opportunities for innovative architectural and SW solutions with major improvements possible. But requires Pathfinding and risk taking.
• If form factor miniaturization is the only motivation, then yes
•If cost reduction is the primary motivation, then generally the answer is no. However, TSS can provide cost reduction within a window of time for large die sizes on leading edge nodes.
• If cost improvement from CMOS scaling diminishes in future nodes (due to Adv Litho and FEOL cost), then the window of opportunity for TSS increases.


Taiji Sakai of Fujitsu made a strong case for why low pitch bonding has moved to copper pillar bumps and wants to move to direct Cu-Cu bonding . The limiting factor preventing that move right now is time/temp required.

The 3D panel session was put together by Qualcomm’s Matt Nowak and moderated by Applied Materials Paul Siblerud.

Interposers failing thermal cycling tests


It was the fall of 2009 that everyone became aware of copper protrusion (or pumping ) as a reliability issue in 3DIC technology. This was discssed extensively in last years IMAPS DPC[ see PFTLE 125, "3D IC at Ft McDowell"] . In the last 12 months many major players confirmed the issue, solutions were proposed and our fears were allayed as to this being a showstopper for 3D IC technology [see IFTLE 6, "Cu-Cu and IMC Bonding Studies at 2010 ECTC"; IFTLE 30, "IEEE 3DIC 2010 in Munich" and IFTLE 34, "3D IC at the 2010 IEDM" ].


The rumors going around at this years IMAPS-DPC were concerned with interposers reportedly failing thermal cycling (TC) reliability tests. Word has it that when the interposers are populated with unequal size or thickness silicon chips or stacks the stresses generated on the interposers is so significant that it causes interposer fracture. I asked the panel, which I was part of, to comment on these rumors. Ron Huemoeller, VP of 3D packaging for Amkor answered that this indeed was the case, that they had seen such problems in the Xilinx scaleup. The good news from Ron is that they were able to engineer around these issues. FYI, recall that the Xilinx interposer is 100 um thick. It is unclear from the current rumors at what thicknesses (chips, stacks and interposers) these issues are seen.


Underfill with Interposers


Underfill has been around since Tsukada told us that they allowed bumped chips to reliably be used on laminate substrates back in 1992. Thus, one would think that underfills would not crop up as a problem in todays 3D technology. However, you must recall that for something like the Xilinx structure [see IFTLE 28, "Xilinx 28 nm Multidie FPGA..." we are talking about microbumps on 45 um pitch, not your typical 150 um solder bumps on 400 um pitch. Amkors Huemoeller comments on the 3D panel that the underfill process took a year get to a manufacturable state. Hopefully the underfill supplies now have the formulations set and can recommend solutions that can be implemented much quicker than that.

EMC 3D closing downâ??¦â??¦.


Paul Siblerud of Applied Materials gave the conference pre notification that EMCD 3D consortium members have concluded that they have met their goals and will be closing this summer. Their last presentation as a group is expected to be at Semicon this July.

Memory Stack Usage coming soon
Huemoeller offered the following Amkor roadmap for memory stack usage:

At the GBC, Suresh Ramalingam of Xilinx discussed the key role of supply chain collaboration. The FPGA is basically a programmable SoC of logic, memory and analog circuits.

Customers were asking for more logic capacity, more high speed transceivers, more processing elements and more memory and Xilinx was faced with the reality that yield of the devices is directly proportional to device size. Rather than try to interconnect smaller devices on a PWB or MCM, which did not offer enough I/O and resulted in high latency and high power usage, their preferred solution was to connect FPGA “slices” on a silicon interposer which offered massive low latency interconnect (10K routing connections between slices with ~ 1ns latency) and low power consumption. They claim this gives them a 1.9X advantage over their nearest competitor.

The 28nm Virtex-7 SSIT will reportedly use TSMC fabricated 100µm thick silicon interposers with 10 – 12 µm Cu TSV and 65nm interconnect. The micro-bumps are Cu-SnAg alloys at 45µm pitch.

Mike Kelley, Sr Dir of Advanced 3D Packaging for Amkor indicated that Amkor bumped the FPGA chip wafers whereas the interposers from TSMC arrived bumped and ready for assembly.

Amkor offered the following process flow for test during assembly :

For all the latest in 3DIC and advanced packaging news stay linked to IFTLE………….










Ft. McDowell AZ was once again the site of the annual IMAPS Global Business Council Meeting and Device Packaging Conference. [For reports on last years conference see PFTLE 123,125,126]

Fan out and Embedded Packaging

Andy Strandjord and Linda Ball put on an excellent panel session on fan out and embedded technology.

Thorsten Meyer one of the developers of the Ifineon eWLB fan out technology informed the audience that his group is now part of the Intel purchase of the Infineon wireless business. They are now the stand alone business “Intel Mobile Communications” Infineon retains rights to non wireless applications. Anyone wanting to license the technology moving forward will have to license from both parties.

Navjot Chhabra (recently from the Sematech ultra lowK program) is now Director of the Freescale RCP fanout technology. They are currently running a 200 mm engineering line while licensee Nepes has a 30 mm line running in Singapore. [see IFTLE 25, “IMAPS Part 2: Advanced Packaging] He indicates that qualifications for “â??¦industrial and automotive products are ongoing”

Meyer also reveled that IZM had licensed their embedding technology (shown below) to Infineon.

Tom Strothman of STATSChipPAC indicated that eWLB is today less costly than FcBGA. STATS is currently running a 300 mm line for production of eWLB.

The panel made the interesting comment that both the fan out and embedded technologies were capable of 0.3 mm pitch but that drop test reliability would go down because the UBM cross section would be smaller.

John Hunt of ASE indicated that ASE does not have 300 mm eWLB in production but commented that “..demand just does not warrant putting that capacity in place” . It was news to me, and I’m sure it will be to most of you, that Infineon is the only commercial customer for eWLB today. Reportedly ST Micro is close but today it is only Infineon .

Much has been made of the possibility for eWLB to move to panel production. Having tried to do thin film packaging on 450 mm panels at Micromodule Systems in the mid 90’s (see fig below) I know that this is easier said than done. (FYI that’s AVX’s Bob Heistand 3rd from the left on top row, Intels Mike Skinner to the right of me and Larry Moresco in front of him. MMS program Mgr Chung Ho was absent from the
picture.

Next week we will look at a summary of 3D activity at the IMAPS DPC

For all the latest in 3DIC and advanced packaging information stay linked to Insights from the Leading Edgeâ??¦.



Founded in 1998, the Focus Center Research Program (FCRP), is one of three research program categories of the well known Semiconductor Research Corporation (SRC) [link]. FCRP research is always looking long-term and big-picture, seeking breakthroughs that are “critical to U. S. security and economic competitiveness”. FCRP programs involve 41 universities, 333 faculty and 1215 doctoral graduate students. The Focus Centers themselves are not physical locations, but rather consist of multiple universities which engage the leading experts at the participating institutions. Each Center is managed by Center Director and addresses one of the major technology focus areas of the International Technology Roadmap for Semiconductors (ITRS).
The SRC runs 6 “focus centers” (below). All 6 centers believe 3D is important and are working in the area. On Feb 11th the first cross center 3-D workshop was held.

In agreement with Intels Karnik, Bartley points towards to thermal awareness as a necessary prerequisite for 3D design as shown below.

Andrew Kahng of UC San Diego reviewed IRTS technology working groups which are involved with 3D technology. IFTLE has recently reviewed the same material [ see IFTLE 16, "The 2009 ITRS Roadmap.."] As an example of some of the things being looked at Kahng pointed to the prober challenges we are expected to see after 2013.

Samsung wide I/O DRAM for Mobile Applications

Samsung, who first revealed 3D TSV stacked memory prototypes in 2006, announced 40nm 8GB RDIMM based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology in Dec of 2010. Samsung claimed the 3D TSV technology saves up to 40 percent of the power consumed by a conventional RDIMM and improves the memory chip density. This DRAM chip was suggested for servers to reduce power consumption and save space. They said Samsung planed to apply the higher performance and lower power features of its TSV technology to 30nm-class and finer process nodes.

At the recent plenary lecture of Dr Oh-Hyun Kwon, President of Samsung ‘s semiconductor business, at IEEE ISSCC 2011 (Int Solid State Circuits Conference), he announced the development of wide I/O 1 Gb DRAM. This memory is reportedly aimed at mobile applications like smartphones and tablet computers. Kwon reports that the 3D TSV architecture will be implemented on their 50 nm node DRAM technology. In related disclosure at the ISSCC Samsung researchers offered more details about the wide I/O memory chip in their technical presentation entitled “ A 1.2V 12.8 Gb/s 2 Gb Mobile Wide I/O DRAM with 4 x 128 I/O Using TSV Based Stacking”.
Previous generations of mobile DRAMs used a maximum of 32 pins for I/O. The new wide I/O solution which has 512 I/O (up to 1200 total) pins can transmit data at a rate of 12.8-Gbytes per second resulting in a significant improvement in processing power. In addition it reportedly reduces the power consumption by 75% by reducing load capacitance. It is expected to replace low power DDR2 DRAM (LPDDR2) which runs at approximately 3.2-Gigabytes per second according to Samsung.

Following this wide I/O DRAM launch, Samsung is aiming to provide 20nm, 4Gb wide I/O mobile DRAM sometime in 2013. Traditionally "wide" parallel interfaces have been more expensive to manufacture and package. Samsung claims, however, that its 1Gb memory chip with wide bandwidth can be installed instead of a larger amount of smaller chips which results in reduced costs and higher performance.

The SEMI ISS meeting (Industry Strategy Symposium )[link] is an annual January event in Half Moon Bay, CA where industry experts and other economic prognosticators make predictions about the upcoming year for the semiconductor industry. [ see PFTLE 121, “IC Consolidation, Node Scaling and 3D IC” for last years coverage]

Bill McClean of IC Insights pegged the 2010 semiconductor market at $313.8B, an increase of 32% over 2009. He is predicting a 10% increase for 2011. He claims a 98% increase in capex occurred between 2009 and 2010 and projects a 6% increase in 2011 to $53.8B. The semiconductor materials market saw a 24% increase between 2009 and 2010 to $42.9B and will see a 8% increase in 2011.

When looking at capex by region (2011 projected vs 2005) we see NA holding constant, Japan and Europe going down while Taiwan and Korea are going up.

10 companies held 85% of the worlds 300mm capacity in 2010.

When looking at growth by geographic region IBS sees China becoming 50% of total consumption by 2012-2013. This means foreign supply will remain a significant portion (ca. 90%) of consumption out into he future (2015)

Thus at 28 and 22 nm taking cache off chip into a 3D technology may be a viable economic option.

For all the latest in 3D integration and advanced packaging stay linked to IFTLEâ??¦â??¦.

Hope to see many of you at the IMAPS Device Packaging Symposium in AZ next week !





In November of 2010 MEPTEC (Microelectronics Packaging and Test Engineering Council) : a trade association of semiconductor suppliers and manufacturers)[link] brought together a group experts from AMD, Altera, Amkor, ASE, Cisco, LSI, Micron, TechSearch, Unisem , Yole and others to discuss the status of Semiconductor Packaging Roadmaps. While the presentations themselves may have had more meat on the bone, many of the handouts were short on data and long on marketing fluff or are materials that we have already recently covered. There were, however, a couple of presentations worth looking at.


Bill Bottoms, CEO of 3MTS gave the introductory talk taking a look a collaborative roadmaps and international roadmap perspectives. From his position as chair of the ITRS (Int Technology Roadmap for Semiconductors) packaging and assembly TWG (technical working group) Bill reminded attendees that ITRS is sponsored by Europe, Japan, Korea, Taiwan and the US to:


– forcast semiconductor technology requirements 15 years out and
– forcast emerging semiconductor devices and materials 10 years out


Its relationship to other Microelectronic roadmap activities in the US is shown below where i-NEMI is actually the pivot point for all the microelectronic activities.

– inherently lower cost
– better electrical performance
– lower power requirements
– smaller size


Several architectural variations of WLP are in use today as are shown below.

Bill updated attendees with where the packaging roadmap would be increasing and expanding coverage in 2011. [ see “Packaging, assembly changes coming in next ITRS Update” ]

Bryan Black of AMD looked at why 3D is required if semiconductor technology is to continue to move ahead. In standard fashion Black defines 3D technology in two varieties as shown below, TSV in active devices and TSV on interposers.