Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



SMTA announces IWLPC featured tutorials

08/12/2010 

Tutorials at the October event will cover 3D packaging, future interconnects, WLP, flip chip, and more.

Assembleon intros back-end package assembly robot

08/12/2010 

Assembleon intros back-end package assembly robotAssembléon’s recently released Twin Placement Robot (TPR) will reportedly reduce costs for semiconductor backend manufacturing. The TPR fits on Assembléon’s A-Series pick & place equipment for packaging and IC placement. Plans are in the works for the TPR to do semiconductor manufacturing tasks as well.

Si, glass interposers for 3D packaging: analysts' takes

08/10/2010 

Silicon interposers for advanced packaging Yole reportYole asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on apps and timing for adoption, says TSI in its forecast for Si interposers. Both analyst forecasts are summarized.

New report on embedded and fan-out WLP from Research and Markets

08/09/2010 

Research and Markets released "Embedded Wafer-Level-Packages: Fan-out WLP/Chip Embedding in Substrate - 2010 Report," which covers embedded IC packaging markets, technology innovations, the manufacturing processes for fan-out and embedded wafer-level packaging, cost targets, and more.

STATS ChipPAC announces pricing of new senior notes

08/05/2010 

The senior notes consist of $600.0 million of 7.5% Senior Notes due 2015. The Private Placement is expected to close on Thursday, August 12, 2010.

Look for TSV to take off in 2012: Jan Vardaman

08/03/2010 

In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real engineering world. Especially for 300mm, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV.

UNISEM records 40% jump in Q2 revenue from 2009

08/02/2010 

Semiconductor packaging and test provider Unisem (M) Berhad announced results for the second quarter, ended 30 June 2010 (2Q10).

Market research: Thermal interface materials and fillers

08/02/2010 

Japan Marketing Survey Co. Ltd. (JMS) will publish "Outlook of thermal interface material market 2010) this week, with data on the semiconductor package thermal management market size by application, thermal interface material types' market shares, and more.

Achieving cost and performance goals using 3D semiconductor packaging

08/01/2010  It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA

Take the survey on PoP assembly

07/30/2010 

Package on package (PoP) stacking makes use of the vertical space available on electronics printed circuit boards (PCBs). It increases density, fitting more silicon into the same footprint. However, package stacking can be difficult, as fine pitches require placement accuracy, and taller stacks generally face reliability issues, especially if the stack is reflowed improperly. So where should PoP stacking take place?

Leveraging 3D packaging technologies: Tessera shares its latest work

07/30/2010 

In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.

Teledyne completes Intelek acquisition

07/29/2010 

Teledyne completed the acquisition of Intelek plc. Teledyne was the beneficial owner of, or had received valid acceptances in respect of approximately 93% of Intelek's ordinary shares. The aggregate value for the transaction will be approximately £35 million.

Insights from SEMICON: Video interview with blogger Phil Garrou

07/28/2010 

In this video interview, Philip Garrou, microelectronics consultant and Advanced Packaging blogger, offers information on his blog, Insights from the leading edge, and summarizes reasonable roadmaps for 3D technology and TSV in particular. 2012 mainstream adoption seems too aggressive to Garrou.

Video: Wafer level packaging data from Texas Instruments

07/27/2010 

In this video interview, Dave Stepniak, Texas Instruments, talks about a wafer-level packaging (WLP) trends paper he presented at SEMICON West. He summarizes the paper for senior technical editor Debra Vogler.

ROGERS teams RO4460 prepreg with RO4360 laminate for multilayer HF circuits

07/27/2010 

Rogers Corporation has developed a match for the RO4360 laminate: RO4460 prepreg. Both materials feature dielectric constant (Dk) of 6.15 ±0.15 and low dielectric loss of 0.003 at 2.5GHz. Together, they form an ideal system for fabricating compact, cost-sensitive multilayer high-frequency (HF) circuits in limited space.

SEMICON West Lesson #3: 3D and packaging are hot

07/26/2010 

Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 3: Everything about 3D & packaging was hot, with suppliers jostling to get into this next high-growth market. But are they really prepared for what awaits them?

Henkel releases NCP for copper pillar interconnect

07/26/2010 

Henkel’s Hysol FP5201 NCP offers the underfill protection required for Cu Pillar technology, effectively mitigating the stress between the substrate and the die.

Research updates on EUV, mask, cleaning, etc from Leti

07/23/2010 

In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.

Soft-pad silicone thermal management material from Shin-Etsu

07/23/2010 

Shin-Etsu Silicones of America Inc., U.S. subsidiary of Shin-Etsu Chemical Co. Ltd., Japan, launched the TC-CA Series, comprised of Shin-Etsu’s advanced polymer and thermally conductive filler composite material technologies. The low-hardness silicone soft pad series of products have both high thermal conductivity and excellent electrical insulation properties.

STATS ChipPAC drawdown under credit facility for redemption at maturity of US$150.0 million 7.5% senior notes due July 19

07/19/2010 

STATS ChipPAC drew down US$150.0 million under the Credit Facility, and used the proceeds from this drawdown to redeem all US$150.0 million in outstanding principal amount of its 7.5% Senior Notes due 2010 at their maturity on July 19, 2010.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

Sponsored By:

Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

Sponsored By:

More Webcasts