Category Archives: 3D Integration

by Debra Vogler, senior technical editor

As another SEMICON West opens, IMEC’s experts — coming off a round of paper presentations at the VLSI Symposium — discussed what they see as being key to the future of semiconductor industry.

New markets to explore. Luc Van den hove, EVP and COO of IMEC, believes that it won’t just be traditional scaling that will drive the industry. “The CMOS processes currently used in manufacturing for logic and/or DRAM show the promise of a whole new future industry driver,” he told WaferNEWS. Referring to the development of new devices and systems, such as integrated smart sensors, power devices, CMOS MEMS and NEMS devices, biochips, etc., he noted that, while process scaling R&D is mainly driven by DRAM, processor, and advanced logic applications, these smart devices and systems can be developed using a CMOS baseline process integrating sensor and actuator functions, or modified for optimized power handling capacity, operation voltages and drive currents, or using above IC thin-film technology for integrated passives and MEMS. Aside from customer demand, he believes innovation and creativity will be the major drivers. “Key for these developments will be the combination of an increasingly wider set of expertise, ranging from CMOS process and design technology, over packaging and interconnect technologies to the bio-nano convergence domain. We will see plenty of opportunities and new markets to explore.”

Bringing FinFETs to manufacturing. Serge Biesemans, department director, CMOS device and technology research at IMEC, believes that FinFETs are a promising approach to address short-channel effects and leakage as CMOS is scaled to the 32nm node and beyond. Because the ultra-thin body FinFETs that IMEC has been researching need no channel doping, it is anticipated that concerns with doping fluctuations in nano-scale planar devices can be addressed using this new transistor structure. “This [new structure] results in reduced parametric spread due to dopant fluctuations together with reduced junction leakage,” he said.

While Biesemans notes that the FinFET structure allows for the implementation of a function with less logic gates than a conventional structure, he does allow that there are still some manufacturing bottlenecks that will have to be overcome. However, at the recent VLSI Symposium, IMEC presented data showing that SRAM cells and data path demonstrators with low standby current and good low operating power performance were realized.

Stacking the deck. Referring to 3D integration as the Holy Grail for system integration, scientific director for interconnect, packaging, and systems integration at IMEC, Eric Beyne, hailed the technology — in which different IC layers are vertically stacked — as having a lot of potential. He cited applications such as memory, portable device, and high-performance computers, to heterogeneous integration of biotech with nanotech, and processing power. But as with almost every new technology, some hurdles will have to be overcome. “To fully exploit the potential of these novel 3D technologies and limit the integration cost, developments have to start from a product perspective,” he told WaferNEWS. “Actual system requirements such as cost, testability, functionality and power have to be taken into account. Also, system architectures need to be revised and design tools need to be upgraded to enable 3D optimization across heterogeneous technologies. Both the technology and the design methodologies developments need to be tightly coupled.”

Deposition challenges hit up low-k at advanced nodes. Rudi Cartuyvels, department director for interconnect, packaging, and systems integration at IMEC, told WaferNEWS that gaining early insight into the metallization challenges of sub-32nm (16-32nm) technologies will require test vehicles of narrow trenches. “Good filling can already be achieved down to ~40nm width,” he said. “Surface and phonon scattering of the electrons are the main contributors to the wire resistivity.” He noted that the filling of trenches thinner than 40nm becomes more challenging and will require a better control of the deposition of the barrier and copper seed at the sidewall. — D.V.

June 12, 2007 – Tezzaron Semiconductor says it is ramping its 2D “3T-iRAM” line of 72Mbit memory devices at Singapore foundry Chartered Semiconductor on the foundry’s 0.13-micron process technology, and plans to use this SRAM drop-in replacement as the basis for its first 3D ICs. Robert Patti, Tezzaron CTO, discusses both technologies with WaferNEWS.

Instead of a single transistor like a normal DRAM, the “iRAM” uses three transistors, making it very fast and able to be made in a logic process, according to Robert Patti, Tezzaron’s CTO, who discussed the work with Chartered in an interview with WaferNEWS. “It’s a dynamic memory that’s can access data faster than a normal SRAM,” he explained, adding that the speed hides the need to refresh the device. “To the outside user it runs just like a normal SRAM,” and with three transistors instead of six in a normal SRAM makes it slightly less than half the size.

The 3T-iRAM work with Chartered is Tezzaron’s first production of a commercial standalone product, after the technology has been run in other foundries as embedded memory, and Patti said the company will still honor commitments to customers who need the embedded version.

The 3T-iRAM also is designed to store up to 8 bits/memory on an individual cell thanks to a feature called “novel current sensing,” which gauges how much current is put into and drawn from the device, though Patti said that won’t be enabled “for the foreseeable future.”

Meanwhile, Chartered and Tezzaron are also moving ahead to develop 3D-ICs using Tezzaron’s process, with plans to double-stack the 72Mbit devices to create a 144Mbit SRAM “drop-in” replacement. Eventually, they will offer many types of 3D IC memories in two, three, and up to five layers using the TSV technique.

Patti explained Tezzaron’s 3D process as building hundreds of thousands of embedded through-silicon vias dubbed “super contacts” into the circuitry on each wafer (instead of just connecting at the I/O). The wafers are then aligned, bonded, thinned, and diced. By comparison, Samsung’s 3D process uses TSVs at the I/O, meaning ~60 TSVs connecting to I/O pins, but “all the processing is in BEOL” with laser holes, cutting and metal plating, and some kind of solder or wire bonding.

But “if you want lower costs and improved performance, you need to fundamentally redesign the part…not with 10s of TSVs per die, but millions,” he said. Patti claimed that, assuming an “apple-to-apple basis” in which the costs to build wafers are equal, Tezzaron’s stacking “is up to half the cost per bit of a normal 2D process” compared to Samsung.

The 3T-iRAM also is designed to store up to 8 bits/memory on an individual cell thanks to a feature called “novel current sensing,” which gauges how much current is put into and drawn from the device, though Patti said that won’t be enabled “for the foreseeable future.” He acknowledged that the current-sensing feature is a technical roadblock to using voltage-based EDA tools, but pointed out that EDA has always been a problem. “We have to work primarily with SPICE as a simulation tool,” he said, citing long simulation times and cutdown models when dealing with hundreds of millions of transistors.

Patti noted that not a lot has changed about the company’s 3D process in the past 2+ years, including the tools (still using EVG equipment), for which they still have “pretty relaxed alignments.” “We did that intentionally,” Patti said; “one challenge at a time.”

Instead, he said, the key is focusing on minimizing process complexity, and he touted Tezzaron’s comparatively simplistic 3D techniques requiring no new materials or equipment process qualifications vs. other memory firms. The company’s “super contacts” use tungsten, which can be formed at FEOL (using TSV), in what he called a “via first, frontend aligned process.” he added. The bonding involves Cu-to-Cu thermal diffusion, “that’s very well understood.” “To Chartered it doesn’t look special to them at all — just a top layer of copper interconnect without an aluminum pad layer.”

Tezzaron had initially hoped to have the SRAM part in production by the end of 2005, but a variety of delays including a design error requiring an architectural fix and “initial issues getting into foundry” pushed plans out by a year, Patti explained. The company is starting with the higher-performance SRAMs because the technology “allows us to have relatively lax 3D rules” but still build something that cannot be cost-effectively produced in 2D, at prices customers will pay for, and starting with moderate volumes (unlike DRAM).

Tezzaron has been through qualification on 3D DRAM parts which look “very very good,” Patti said, but they’re still accumulating data. He projects to move to early production of DRAMs “sometime next year” — combining controller (logic) wafers from Chartered with other wafers from DRAM foundries in Taiwan — targeting higher-performance DDR2 (up to 1.2GHz) and DDR3 (2.4GHz) ranging from 512Mbit-2Gbit. — J.M.

by Jeff Demmin, Contributing Editor, WaferNews

Samsung, Hynix, and Akita Elpida have all made announcements recently about their latest achievements in memory stacking technology. There was definitely a competitive tone to these releases, but they actually appear to be pushing somewhat different agendas.

Akita Elpida was set up less than a year ago by Elpida to develop advanced packaging technology for its DRAM products. The technology includes the chip stacking and package-on-package approaches that many companies are using, and Akita Elpida apparently decided to make a splash by pushing the limits on chip stacking. The result was a stack of 20 chips within the 1.4mm vertical envelope that is a typical target for current DRAM products. Akita’s announcement includes many technical details about their wafer thinning, thin-wafer handling, die handling, low-loop wire bonding, and molding technologies. This served as a reminder that DRAM companies other than the top four have some advanced technology too. Akita admits that all of this technology will be put to use in die stacks up to about seven high for now, so the 20-die stack was used at least in part to get some attention. The technology cited by Akita is evolutionary rather than revolutionary, though, so it should make its way into the mainstream soon.

Hynix also announced the capability to stack 20 chips in a 1.4mm thick package. The Korean memory giant noted that it can thin chips to 25µm, compared to 30µm for Akita Elpida, adding some fuel to the competitive fire. The spin for Hynix is that they are doing it with NAND flash memory chips, which was a way for Hynix to promote itself as something other than a DRAM supplier. A recent NAND flash joint venture announcement with SanDisk also emphasized this point. Diversifying beyond DRAM is one way to mitigate the pricing pressures and cycles faced when a company has been focused on just one type of memory. The exploding market for NAND flash has also made it an appealing target for growth.

Samsung’s stacking technology announcement emphasized their capability as a leader in wafer processing technology, extending that to vertical integration. Specifically, a through-silicon via technology tailored for DRAM was introduced and touted as the first all-DRAM TSV technology. Samsung creates the vias by laser-drilling holes through the wafers and filling them with copper. (Other possible TSV approaches include etching trenches through the silicon.) The introductory DRAM product using the technology is a stack of four 512 Mb DDR2 DRAM, which enables a 4GB DIMM.

Samsung’s announcement of this extension of its TSV technology from NAND flash, which was rolled out a year ago, to DRAM is one indication of integrated device manufacturers (IDMs) taking more control of the vertical integration market. A few years ago, most of the stacking announcements came from packaging sub-contractors, which had their own horse race to see who could stack the most packaged or bare die. But with TSVs moving closer to the mainstream, the IDMs are becoming the leaders — the performance, form factor, and supply chain benefits of TSVs have made it an attractive technology for the top IDMs to have in-house. Samsung’s announcement of DRAM TSVs let the market know that their products will be benefiting from an industry-leading technology. — J.D.

IMAGE CAPTION:
Microscopic views of 20-die multi-chip packages of Samsung Electronics (left) and Hynix (right). By stacking up in tilting steps, Hynix’s package is less susceptible to malfunctions, the company claims. (Source: Korea Times)

June 11, 2007 – STATS ChipPAC Ltd. says it will sell certain assembly and test assets for its discrete power packages to China’s Ningbo Mingxin Microelectronics Co. Ltd., following a similar transaction a year ago to farm out some work to mainland China in order to pursue better growth opportunities in areas such as system-in-package, flip-chip, and 3D technologies.

Under the deal, Mingxin, located in Ningbo city, Zhejiang province, will take on assembly and test assets used to manufacture discrete power packages including the TO220, D2Pak, TO247 and Dpak. Transfer of engineering, production, and quality resources is expected to be completed by the end of 2008.

“Transitioning out of the discrete power market will enable STATS ChipPAC to better focus our resources on our strategic advanced products that have better long term growth prospects,” said Tan Lay Koon, President/CEO of STATS ChipPAC, in a statement, adding that handing the lines to Mingxin “offers our existing customers in discrete power packages the best solution for their long term business needs.

“We are pleased to work with a global service provider like STATS ChipPAC and believe the strong alignment between the two companies will provide significant benefits to power customers,” added Mingxin president Zhang Jia Lin.

Mingxin’s Web site claims annual capacity of 1.6 billion discrete pieces and eventual planned capacity of 6 billion pieces/year, with 48,000 sq. m. of total facility housing 15 production lines for various power, medium and small signal semiconductors, including an assembly factory and semiconductor engineering technical center.

A year ago STATS ChipPAC agreed to set up a JV in Wuxi, China, with China Resources Logic Ltd. to provide assembly and test service for STATS’ lower-end leadframe package families, allowing the firm to focus on more leading-edge products such as system-in-package, flip-chip, and 3D technologies. That deal aimed to essentially farm out work for several of STATS ChipPAC’s lower-end leadframe package families, including small outline integrated circuit (SOIC), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), mini small-outline package (MSOP), small shrink outline package (SSOP), and thin-shrink small outline package (TSSOP).

June 7, 2007 – Tronics Microsystems SA and Alcatel Micro Machining Systems (AMMS) say they will jointly develop deep reactive ion etch (DRIE) systems for “extreme-performance” MEMS.

The work will utilize Tronics’ test protocols to evaluate and qualify new advanced DRIE manufacturing processes from Alcatel, which the company will use to further enhance its technology for advanced high-aspect-ratio, high-yield and manufacturing-proven processes. In return, Tronics will gain “priority access” to Alcatel’s latest process modules and services.

“It is a great opportunity for us to benefit from Tronics’ unique manufacturing experience in high- performance SOI-based inertial transducers and 3D packaging to qualify our future DRIE process modules with them,” said Jean-Marc Gruffat, director of products at AMMS, in a statement. “Our goal is to push the limits of high-aspect-ratio DRIE processes with high- accuracy controlled profile, excellent uniformity and reproducibility in order to provide our customers best-in-class, manufacturing-proven and high-yield DRIE production tools for next-generation MEMS and 3D semiconductors.”

“This partnership marks a major milestone in strengthening our technological and market leadership in manufacturing custom products for demanding applications,” including MEMS geophones, miniature SMD accelerometers, and MEMS gyros transducers, noted St

By Phil LoPiccolo, Editor-in-Chief

Among the most significant developments in interconnect slated to appear at this month’s International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH’s interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his “new religion,” because stacked chips allow interconnects to be much shorter than in traditional 2D configurations. This technique, he claims, could be the most promising route to reducing resistance-capacitance (RC) delays, the main stumbling block to higher chip speeds and lower power consumption.

Traditional approaches to reducing RC delays face serious obstacles. For instance, lowering the relative permittivity (k value) of the dielectric materials surrounding metal interconnect lines, in order to reduce the signal-retarding capacitive coupling that occurs when the lines are placed closely together, has progressed more slowly than the International Technology Roadmap for Semiconductors (ITRS) timetable has specified, explained Arkalgud, and that trend could continue. At the 32nm node, the ITRS calls for keff to be between 2.1-2.4, he noted. The problem is that lowering the k value, typically by adding porosity, means the mechanical properties of the materials (hardness, elastic modulus, etc.) all go in the wrong direction, and damage resulting from etch, ash, and CMP processes needs to be eliminated. Also, the use of low-k support layers (etch stop, caps, hard masks) is essential to realize the low-keff value). Consequently, expensive new tools, such as low-downforce CMP, must be integrated into process flow to compensate for the more fragile materials.

Read the complete article.

May 31, 2007 — e2v, developer and manufacturer of electronic components and subsystems, has announced a new generation of high-sensitivity imaging sensors that leverage technology from Tracit Technologies, a new division of the Soitec Group.

Combining e2v’s expertise with Tracit’s circuit layer transfer technology makes available back-illumination capability to medium volume markets for the first time. This promises a dramatic improvement in sensor sensitivity when compared to a standard front-illuminated sensor.

The company says this improvement in sensitivity makes its new sensor ideal for a broad range of applications, especially in medium volume, professional markets. It also complements e2v’s existing back-illumination capability for low-volume markets like aerospace and life sciences.

“We . . . see great potential, particularly in small-pixel CMOS sensors,” said Jean-Philippe Lamarcq, Imaging Business Unit General Manager at e2v.

According to Dr. Bernard Aspar, founder and General Manager of Tracit Technologies, “The ability to move finished circuits onto new supports is a promising way to improve device performance or to enable hetero-structure stacking for 3D integration.”

Both e2v and Tracit are based in Grenoble, France.

By Phil LoPiccolo, Editor-in-Chief, Solid State Technology

In the new consumer-driven electronics industry, where beating your competition to market with innovative technology is the surest route to success, process control equipment suppliers have an expanded role in manufacturing alliances to help dramatically shorten product-development and production-ramp times, and thus significantly improve yield and profitability, according to Brian Trafas, chief marketing officer at KLA-Tencor, in his talk at the Confab in Las Vegas.

Speaking at The ConFab yesterday from the perspective of an equipment supplier managing customer alliances, Trafas explained that while developing high-performance devices at high yield is still a critical requirement for profitability, so is reducing time to market. If you get to market early, you can demand a higher average selling price (ASP), he stressed — but if you’re late, ASPs can plummet below profitable levels.

Trafas outlined the hurdles that hinder efforts to reduce time to market as chipmakers attempt to continue improving price-performance ratios at the speed of Moore’s Law. One obstacle is that the number of new materials used in semiconductor manufacturing will jump from just over 20 to nearly 40 during this decade, roughly triple the rate of increase over previous decades (see Fig.1) To fabricate leading-edge memory or logic devices will require the integration of a host of new materials, he said. And each may require process changes that have the potential to introduce new metrology and defect control challenges, not only during process development when these issues are identified and characterized, but also during volume production, when the process must be monitored closely for yield and reliability excursions.

Another challenge is that to achieve continuing performance improvements, chipmakers must increasingly focus on innovation versus device scaling. Whereas at the 130nm node the vast majority of performance increases were the result of scaling rather than performance increases, at the 90nm and 65nm nodes innovation accounted for ~58% and 64% of performance increases, respectively (see Fig. 1). Clear examples of the impact of innovation in the logic community, Trafas explained, include the impact that strain engineering and the move from 2D to 3D architectures have had in terms of improving system performance.

Going forward, we need to improve the ability to capture defects on new material types as well as to detect both random and systematic defects, Trafas said. But an overarching issue is to improve yield, particularly early in the cycle. It all comes back to the time-to-market issue, and how profitability is determined by how quickly a fab can develop a process with production-level yield, he said, adding that this is the biggest knob to turn to improve profitability.

As a process control equipment supplier, KLA-Tencor has worked in alliances encompassing both chipmakers and process tool suppliers, focusing on collaboration to help improve the fab’s die-yield in a shorter timeframe, Trafas said. In fact, KLA-Tencor has shifted its emphasis in the last four or five years to starting collaborations much earlier than before, he said.

In one such collaboration, KLA-Tencor worked with IBM, Chartered, and several process tool suppliers to help IBM transfer the chipset for the Xbox game console from its “mother fab” in Fishkill, NY, to Chartered’s Fab 7 foundry in Singapore, Trafas explained in an interview. “We identified yield issues at critical points in the line, helped the customers fix those issues, and put in monitoring steps that allowed the customers to quickly fix any yield excursions that might arise,” he said. Ensuring that an effective inspection and metrology strategy was in place, that recipes and tools were matched, and that best known methods were documented was essential in helping IBM and Chartered achieve a parallel-ramp transfer of the 90nm technology within a tight, inflexible time window, he claimed.

The economic benefits of early collaboration can be significant. Trafas showed that by collaborating in a recent alliance with another logic customer, the partners were able to reduce the development time required to achieve 20% yield from 12 months to nine months, which resulted in a savings of $150 million. They were then able to ramp to 20%-50% yield two months faster than expected, for a savings of $200 million. And they reached production at 50%-80% yield nine months sooner than planned, for an additional $120 million in savings, plus a 10% higher overall yield (see Fig. 2).

Clearly, the industry is moving forward through alliances, both in R&D and manufacturing, Trafas noted, and the best strategy for making successful supplier/manufacturer partnerships entails coming together early in the process to define the challenges the customer is trying to solve, getting high-level sponsorship from both sets of management, developing projects with measurable goals, and creating an environment that supports open, collaborative teams working together.

“In the end, we have to have a win-win outcome,” Trafas said. “By understanding what the customer is trying to achieve, we can commit to meeting a mutual goal. This goes beyond just delivering equipment and then moving on.” — P.L.

May 14, 2007 – STATS ChipPAC has formally established its new R&D facility in Singapore, to develop next-generation technologies including through-silicon vias (TSV), microbump bonding methods for 3D die, silicon substrate-based system-in-package solutions, and embedded active die technology.

The new facility includes >10,000 sq. ft. of cleanroom space (Class 10-10,000), which can be nearly doubled for future expansion needs. The R&D operation will “specialize in wafer-level processing,” with an equipment set for photolithography, plasma etching and deep reactive ion etching (DRIE), wafer thinning, and wafer bonding, the company said in a statement.

Operations at the new Singapore R&D site will seek to expand on the company’s silicon-based offerings including integrated passive networks such as baluns, filters, and amplifiers, for new integrated passive devices, in addition to work on TSV, 3D microbumps, etc.

“The new facility fulfills an important role in the Company’s global R&D strategy and will augment our current worldwide R&D operations focusing on advanced packaging solutions,” stated company CTO Han Byung Joon.

By Phil LoPiccolo, Editor-in-Chief

Among the most significant developments in interconnect to look for at the upcoming International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH’s interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his “new religion,” because stacked chips allow interconnects to be much shorter than in traditional 2D configurations. This technique, he claims, could be the most promising route to reducing resistance-capacitance (RC) delays, the main stumbling block to higher chip speeds and lower power consumption.

Traditional approaches to reducing RC delays face serious obstacles. For instance, lowering the relative permittivity (k value) of the dielectric materials surrounding metal interconnect lines, in order to reduce the signal-retarding capacitive coupling that occurs when the lines are placed closely together, has progressed more slowly than the International Technology Roadmap for Semiconductors (ITRS) timetable has specified, explained Arkalgud, and that trend could continue — at the 32nm node, the ITRS calls for keff to be between 2.1-2.4, he noted. The problem is that lowering the k value, typically by adding porosity, means the mechanical properties of the materials (hardness, elastic modulus, etc.) all go in the wrong direction, and damage resulting from etch, ash, and CMP processes needs to be eliminated. Also, the use of low-k support layers (etch stop, caps, hard masks) is essential to realize the low-keff value). Consequently, expensive new tools, such as low-downforce CMP, must be integrated into process flow to compensate for the more fragile materials.

Similarly, reducing resistance in interconnect lines has proven difficult. As copper wires are made thinner, resistivity rises because of volume effects and surface and grain boundary electron scattering, “and there’s little we can do about it, because we’re bumping up against physics,” Arkalgud noted. Moreover, process variations at that scale compounds the problem of controlling line resistance.

“Clearly, we’re up against some big issues in reducing interconnect resistance and capacitance,” says Arkalgud. “While copper and low-k will remain the metallization of choice for most companies, it will be harder to realize the RC benefits of material and linewidth scaling.” So, SEMATECH has turned its attention to the most promising future directions for meeting these challenges, including 3D chip architectures with through-silicon vias, carbon nanotubes, optical interconnects, and guided waves. “And in our opinion, 3D stacking using through-Si vias stood out, for several reasons,” said Arkalgud.

Advantages of 3D

One benefit of 3D stacking is improved performance. “To take interconnect lines, which can be several mm long, and turn them into vertical interconnects that are only 10s to 100s of microns in length, you can significantly cut down the RC delay in a brute force kind of way,” says Arkalgud.

Another advantage is that, for the most part, no new materials would need to be developed and integrated, Arkalgud explains. Apart from the bonding material, 3D stacking uses mostly standard silicon processing.

3D stacking also enables greater integration of heterogeneous layers of functionality, such that any combination of logic, memory, analog, MEMS, sensors, optoelectronics, and bio-devices could be incorporated into the stack.

In addition, from a cost perspective, the most economically feasible processes could be used for each layer of a heterogeneous 3D chip architecture. For example, for some layers (such as analog and low performance logic), a chipmaker might use a depreciated fab running 0.25-micron technology, and run a high performance logic or high-density memory in a state-of-the-art, 65nm fab, and then bring all the layers together in the 3D stack, Arkalgud says. That could avoid the cost issues with system-on-chip (SoC) designs, in which chip manufacturers pay for cutting-edge processes for the entire chip, even for blocks with significantly lower technology requirements.

3D papers

Among papers released in advance of IITC that discuss advances in 3D chip interconnects is one from IMEC researchers, describing how they created 3D chip stacks with improved thermal and mechanical stability by using both copper-to-copper thermocompression bonding and compliant glue layer bonding. The glue layer, which had no impact on the resistance of through-wafer via test structures, allowed separate die-stacking and die-bonding operations. That way, a landing wafer can be populated with dice in a fast pick-and-place operation, then the dice can be bonded collectively later on (see image above).

Another 3D architecture paper, from a Freescale and Leti teamresearchers, explains how they created 3D circuits using a dielectric-to-dielectric wafer bonding process and 90nm low-k interconnect technology. The researchers team reports that the integration technique depends strongly on keeping the respective surfaces clean to ensure reliable, defect-free direct dielectric bonding, as well as precise wafer-to-wafer alignment, backside thinning, and deep through-strata via formation.

Other technologies: CNT, optical, waves

Additional advance-released IITC papers focus on the other leading interconnect technologies that Arkalgud and his team at SEMATECH have been evaluating: carbon nanotubes (CNT), optical interconnects, and guided waves.

On the CNT front, a team at MIRAI-Selete in Japan reports it has designed a mostly CMOS-compatible damascene process for fabricating vertically aligned, multi-walled nanotubes, with 10nm dia. and a density of 3×1011/cm2 in 160nm dia. via holes, and with the lowest resistance (0.05 ohms) reported to date. (See “CNT interconnects target 32nm”, WaferNEWS V14n17, April 24, 2007). In other CNT work, a team from RPI has developed a novel technique to significantly increase the density of CNT bundles, and thereby reduce their resistance, by immersing CVD-grown, CNTs in an organic solvent. When the solvent evaporates, the individual nanotubes aggregate into higher-density bundles by capillary coalescence and remain together by van der Waals forces.

In the realm of optical interconnects, Sun Microsystems researchers have devised a 90nm test chip that integrates optical interconnects employing external lasers and photodiodes with two other types of chip-to-chip interconnects: capacitive interconnects for proximity communication and electrical interconnects using current-model logic for high-speed operation and optical compatibility. The researchers report interoperability between all three interfaces at speeds exceeding 2.5 Gbps, and contend that the work could drive more aggressive interconnects including silicon-based photonics (see image below).

Developments in guided wave interconnect technology are reported in a paper by a Tokyo Institute of Technology team that has built a low-voltage transmission-line interconnect architecture based on a 90nm silicon CMOS process, that transfers signals as electromagnetic waves, using on-chip inductors as transceivers. The team achieved 10Gbps signal transmission with 2.7mW power consumption, and reports that delays were reduced by up to 89% compared to a conventional interconnect stack. — P.L.

CAPTION FOR TOP IMAGE:
At IITC, IMEC researchers will describe how they used copper-to-copper thermocompression bonding with a spin-on compliant dielectric glue layer to create 3D systems with improved thermal and mechanical stability. The illustration shows two thin ICs (IC2 and IC3) stacked on a third device (IC3), with dice separated by a thin dielectric glue layer and integrated with through-silicon copper vias. (Source: IITC, IMEC)

CAPTION FOR BOTTOM IMAGE:
At IITC, Sun Microsystems researchers will describe a 90nm test chip integrating three types of chip-to-chip interconnects: capacitive interconnects for proximity communication, optical interconnects employing a vertical cavity surface emitting laser (VCSEL) and photodiode (PD), and electrical interconnects using current-model logic for high-speed operation and optical compatibility. The illustration shows how these pieces might fit together. (Source: IITC, Sun Microsystems)