By Dick James, Senior Technology Analyst, Chipworks

On December 3^rd – 7^th , the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2016 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Saturday/Sunday

Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

• The Struggle to Keep Scaling BEOL, and What We Can Do Next, Rod Augur, GlobalFoundries
• Physical Characterization of Advanced Devices, Robert Wallace, U. Texas at Dallas
• Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications, Bernard Dieny, Chief Scientist, Spintec CEA
• Electronic Circuits and Architectures for Neuromorphic Computing Platforms, Giacomo Indiveri, U. Zurich/ETH Zurich
• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Dr. Ben Kaczer, imec
• Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00. This year I hope to make it to the Physical Characterization session, and possibly the IoT talk at 4.30.

On Sunday December 14^th, we start with the short courses, “Technology Options at the 5-Nanometer Node” and “Design/Technology Enablers for Computing Applications”.

Last year the process short course was “Emerging CMOS Technology at 5 nm and Beyond”, so I guess we will see how things have evolved at 5 nm.

The course has been organized by An Steegen and Dan Mocuta of Imec. They introduce it bright and early, at 8.30 a.m.

The first session is “Nano Patterning Challenges at the 5nm Node”, given byAkihisa Sekiguchi of Tokyo Electron. Next up is Nadine Collaert from imec, discussing “Novel Channel Materials for High-Performance and Low-Power CMOS”, followed by Aaron Thean, of the National University of Singapore (and formerly imec),who is presenting on “Options beyond FinFETs at 5nm node”.

Contacts are the next topic, “Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance”, by Reza Arghavani of Lam Research.

The back-end stack gets more critical as dimensions shrink, so we have a review of “Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology”, by Theodorus Standaert from IBM.

The last session covers off “Metrology Challenges for 5nm Technology”, by Applied Materials’ Ofer Adan – given that we are now counting atoms, challenging is a good way to describe it.

John Chen of Nvidia set up the Design/Technology short course, which takes a fairly high-level look at the technologies involved in processing Big Data, discussing the different processors themselves, the effects of memory, managing the power and connectivity, and where advanced packaging fits in.

So we have:

• “The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape” – Liam Madden, Xilinx
• “Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective” – Gabriel Molas, Leti
• “Power Management with Integrated Power Devices…and how GaN Changes the Story” –Alberto Doronzo, Texas Instruments
• “Interconnect Challenges for Future Computing” – William J. Dally, NVIDIA/ Stanford U
• “Advanced Packaging Technologies for System Integration” – Douglas Yu, TSMC

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 6.00 CEA-Leti is hosting a Devices Workshop at the Nikko Hotel, across the street from the Hilton.

Monday

Monday morning we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:

• “Technology Scaling Challenges and Opportunities of Memory Devices” – Seok-Hee Lee, Hynix
• “Brain-Inspired Computing” Dharmendra S. Modha – IBM
• “Symbiotic Low-Power, Smart and Secure Technologies in the age of Hyperconnectivity” – Marie-Noëlle Semeria, Leti

Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have seven parallel sessions!

Session 2: Circuit and Device Interaction — Advanced Platform Technologies – including 7 nm finFETs!

Session 2 starts a track on Circuit and Device Interaction, in this case with papers on Advanced Platform Technologies – for me a highlight session, since the session ends with duelling 7-nm late-news papers from TSMC (2.6) and the Samsung/GLOBALFOUNDRIES (GF)/IBM consortium (2.7).

In addition, we have a GF/Leti discussion of the GF 22FDX SOI technology (2.2) announced last year; paper 2.3 is a research paper on 3D monolithic integration of ultra-thin body MOSFETs into a VCO and power management circuit, with a 4-layer Vertical ReRAM, by Taiwan’s National Nano Device Laboratories and National Chiao Tung University.

GF co-authors the next two papers, detailing a high-resistance SOI technology for RF front-end modules (2.4), integrating a power MOSFET with a RF switch by using selective silicon thinning; and (2.5) a look at monolithic 3D IC design partitioning to mitigate the performance limits set by the limited thermal budget of the upper transistor level in the 3D IC stack.

In 2.6, TSMC announces the “world’s first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors”. They claim the world’s smallest-ever SRAM cell at 0.27 µm², and 3x the gate density of the 16-nm process, together with a 35 – 40% speed gain or over 65% power reduction.

In addition, the process uses 93nm immersion lithography, raised source/drain epi, a novel contact technique, and a 12-layer copper/low-k interconnect stack.

By contrast, the finFETs in 2.7 from the GF/IBM/Samsung group consortium (presumably at Albany, NY) were manufactured using EUV, with contacted polysilicon pitch (CPP) of 44/48nm, and metallization pitch of 36nm. It also features dual-strained channels formed on a thick strain-relaxed buffer (SRB) virtual substrate to give tensile-strained NMOS and compressively strained SiGE PMOS for the enhancement of drive current by 11% and 20%,  respectively, when compared with a common planar (my italics) HKMG process. Epitaxy is used in the contact trenches to minimize resistance.

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB (2.7).

Session 3: Compound Semiconductor and High Speed Devices — Compound Semiconductors for High Speed RF and Low Power Logic Applications

The session starts with a paper (3.1) from Germany’s IHP Institute, on their (claimed) fastest silicon-based heterojunction bipolar transistor (HBT), with an f_T/f_max of 505 GHz/720 GHz, respectively, at 1.6 V; they attribute this to optimized vertical profiles of the emitter-base-collector regions, the use of “flash” annealing and low-temperature backend processing to lower base and emitter resistance, and lateral device scaling.

TEM image of a cross-section of an optimized Si HBT device (3.1).

Lund University is up next (3.2), discussing InGaAs tri-gate MOSFETs with record on-current of 650 µA/µm at 0.5 V. Paper 3.3 is an invited talk on “High Frequency GaN HEMTs for RF MMIC Applications”, from HRL Labs.

In paper 3.4, MIT studies a new form of instability due to F- migration and the passivation/depassivation of Si dopants in a n-InAlAs cap layer in InGaAs MOSFETs; it turns out that removing the cap layer gets rid of the instability!

MIT also presents paper 3.7, on using a physical compact model to improve the RF circuit linearity performance of GaN HEMTs, in both device and circuit design techniques. GaN HEMTs are again discussed in 3.5, this time W-band N-polar devices; UCal Santa Barbera claims a record high efficiency of 27.8% at 94 GHz.

And to fill in the gap at 3.40 pm (3.6), IBM gives an invited talk on “Monolithic Integration of Multiple III-V Semiconductors on Si for MOSFETs and TFETs”, using template-assisted selective epitaxy (TASE) for a number of III-V compounds.

Session 4: Memory Technology — RRAM, PRAM and Applications

We start with an invited talk “Towards Ultimate Scaling Limits of Phase-Change Memory” (4.1) by Feng Xiong of Stanford U., reviewing advances in phase-change memory (PCM), which is now down to sub-10 nm scale, with switching energies approaching femtojoules per bit.

Paper 4.2 discusses confined ALD-based PCM with a metallic liner, which is reported to have record endurance of 2e¹² cycles; and 4.3 looks at SiO_x-based RRAM (Resistive Random-Access Memory) in crossbar memory arrays, and also as select devices in the arrays.

Oxygen implantation into Ta₂O₅ and HfO₂ is used to form RRAM devices in the ON state (4.4), which subsequently switch similarly to regularly made reference devices. The correlation between endurance, window margin and retention of RRAM types (oxide RAM and conductive bridge RAM) is studied in 4.5, and the effect of programming parameters on oxide RAM retention is the topic in 4.6.

The intrinsic variability factors of RRAM are quantified in 4.7, to identify the fundamental variability limits of the technology, and the last paper (4.8) details a random number generator fabricated in Panasonic’s 40-nm embedded ReRAM process.

Session 5: Nano Device Technology — 1D and 2D Devices

This session (not surprisingly) is a set of research papers, starting with a pair of carbon nanotube (CNT) transistor studies; 5.1 details CNT-FETs with nickel contacts alloyed into the ends of the CNTs to reduce contact resistance and give scalability to the contact process.

Schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts (5.1)

We look at vertically suspended CNT-FETs in 5.2, which allows a fully gate-all-around (GAA) structure with multiple channels, optimising gate controllability and enhancing charge transport.

In 5.3 we move to graphene FETs, again examining ways of reducing contact resistance, this time using “atomic orbital overlap engineering”.

Paper 5.4 is an invited talk from Mathieu Luisier of ETH Zurich on simulations of 2-D devices, reviewing mobility, I-V characteristics, and contact resistance, with extra detail on contacts to molybdenum disulphide (MoS₂).

Black phosphorus is another potential 2-D transistor material, and PMOSFETs with a boron nitride/alumina gate dielectric are discussed in 5.5.

The last three papers focus on MoS₂, examining 10-nm top-gated transistors in 5.6, and we go beyond transistor studies in 5.7 to develop guidelines for co-optimisation of material, devices, and circuits, to get the yield up and move towards manufacturability. The final paper (5.8) gets back into the detail of the MoS₂ MOS interface trap density created by S vacancies in the MoS₂.

Session 6: Sensors, MEMS, and BioMEMS — Focus Session: Wearables for the Internet-of-Things (IoT)

As a focus session, this features a series of seven invited presentations;

• “High Performance, Flexible CMOS Circuits and Sensors Toward Wearable Healthcare Applications,” by K. Takei, Osaka Prefecture University (6.1)
• “Circuits and Systems for Energy-Efficient Smart Wearables,” by A. Sharma, Texas Instruments (6.2)
• “Flexible Metal-Oxide Thin-Film Transistor Circuits for RFID and Health Patches,” by P. Heremans et al, Imec/University of Leuven/Holst Centre (Belgium)/National Centre for Flexible Electronics (India) (6.3)
• “Challenges and Opportunities in Flexible Electronics,” by R. D. Bringans and J. Veres, Xerox PARC (6.4)
• “Advanced Integrated Sensor and Layer Transfer Technologies for Wearable Bioelectronics,” by D. Shahrjerdi et al, New York University (6.5)
• “Wearable Sweat Biosensors,” by A. Javey et al, University of California, Berkeley (6.6)
• “Flexible Metamaterials, Comprising Multiferroic Films,” by Y. P. Lee et al, Hanyang University (6.7)

Schematics and example of wearable sweat sensor from paper 6.6

Session 7: Modeling and Simulation — Advanced Numerical and Compact Models

The first paper details an electro-thermal compact model for self-heating ICs, including the BEOL, that can predict front-and back-end reliability, and takes account of interconnect layout and geometry (7.1).

In 7.2 we hear about a model that considers the percolation path of the channel current in a transistor to help understand the statistical variability and reliability in nanoscale devices, and compares the different features of 3-D finFETs with planar transistors.

HfOx-based analog synaptic devices are considered in 7.3; the SET, RESET, and retention loss processes are simulated and given experimental verification, capturing the key material parameters and forming optimization guidelines.

P-channel GaN MOSHFETs are the topic in 7.4, examining the electric field distribution to determine why a higher threshold voltage needs reduced channel and oxide layer thicknesses. This led to the introduction of an AlGaN cap layer to modulate the field and increase the on-current.

We move to GAA-MOSFETs in the next presentation, modelling stacked-planar and vertical transistors of circular, square, and rectangular cross-sections (7.5). Then we change technologies again and look at the resistive switching behaviours of CBRAM devices (7.6).

CBRAMs use the property that if amorphous insulating materials contain a relatively large amount of metal, the metal ions they contain can form a conductive path when voltage is applied; this can be reversible, enabling the storage of data as the conductor appears and disappears. The paper studies three modes of filament formation.

3-D cross-point memory cells formed using germanium-selenium telluride (GST) are discussed in the last paper of the session (7.7), extending the model to simulate memory array circuits.

Session 8: Optoelectronics, Displays, and Imagers — Imaging and Photon Counting Sensors

The first paper in the session presents a backside-illuminated (BSI) single photon avalanche diode (SPAD) image sensor (8.1), a claimed first in the field. Most of the CMOS image sensors (CIS) in smartphone cameras these days are BSI, usually with stacked dies and through-silicon vias (TSVs), although the very latest use face-to-face wafer bonding of the metal interconnects.

It looks as though this device also uses stacked dies, since the SPADs are fabbed in a 65-nm process, and the processor is 40-nm.

SPADs are getting attention lately since they are also appearing in mobile phones in time-of-flight auto-focusing devices for the cameras, and in the latest iPhone they are doing double duty as a proximity sensor and autofocus for the selfie camera; see my last blog for more details.

STMicroelectronics time-of-flight sensor from iPhone 7

Paper 8.2 is also focused on SPADs, in this case a 256 x 256 image sensor with 16 µm pixel pitch and a 61% fill factor. Then we have an invited talk from M.Mori of Panasonic (8.3), discussing “An APD-CMOS Image Sensor Toward High Sensitivity and Wide Dynamic Range”; followed by Sony (8.4) showing off their latest die stacking using copper/copper hybrid bonding connecting the image sensor to the image processor (also known as direct bond interconnect (DBI).

We at Chipworks actually found this technology in the Samsung Galaxy S7 Edge back in March, so it is definitely in volume production.

SEM cross-section of Sony image sensor from Samsung Galaxy S7 Edge, showing copper/copper direct bonding

Next up is a global shutter CIS (8.5) which somehow has 480 analog memories/pixel integrated using vertical analog memory technology, which enables 1 Mfps.

In 8.6, Canon exhibits one of their huge 35-mm full-frame sensors, this time a low-noise global shutter device with a 6.4 µm pixel size. Apparently, most CMOS imagers use a rolling shutter, which reads the pixels at different times at different parts of the imager, leading to image artifacts, especially for moving targets (see image below of vibrating ukulele strings).

 
The last paper is another from Sony (8.7), this time detailing a “Four-Directional Pixel-Wise Polarization CMOS Image Sensor Using Air-Gap Wire Grid on 2.5-µm Back-Illuminated Pixels”. If I understand the abstract correctly, this sensor has a wire grid with 150-nm pitch over the pixels which acts as a polarizer, presumably in the four directions of the grid sides.

That is the end of the Monday afternoon sessions, and the reception will start at 6.30 pm in the Grand Ballroom; but if you have links to Stanford U, there is a gathering at 5 before then.

Tuesday

Session 9: Process and Manufacturing Technology — 3D Integration and BEOL

The session starts (9.1) with a discussion of 3D-stackable finFETs compatible with back-end processing, using single-grained silicon fins and laser spike anneal to keep the thermal budget down.

We have seen the use of liquid surface tension for die positioning and self-assembly in years past; in 9.2 we have it applied to 2.5/3D integration of multiple types of die, even those with uneven surfaces and bottom topography.

Next we have an invited presentation (9.3) by Ruth Brain of Intel, on “Interconnect Scaling: Challenges and Opportunities”, focusing on the transistor/interconnect optimization that is necessary now that interconnect delay is dominating circuit performance.

Paper 9.4 looks at a high-k MIM decoupling capacitor aimed at the 7-nm node; and 9.5 discusses graphene-on-copper for improved interconnectivity and enhanced electro-migration lifetime. The last paper (9.6) explores the intriguing concept of vertical-channel devices gated by TSVs.

Session 10: Power Devices — Power Semiconductor Device Technologies

We get into the world of GaN devices in the first four papers – 10.1 details a normally-off V-trench GaN transistor formed on a GaN substrate, with a record 1.7 kV breakdown voltage and on-state resistance of 1.0 mΩcm²; 10.2 describes a vertical GaN Schottky rectifier incorporating trench MIS structures and field rings; 10.3 is about GaN gate injection transistors with high-speed switching, again built on a GaN substrate; and 10.4 presents on high-performance enhancement-mode GaN MIS-FETs with a recessed-gate structure and a SiN_x gate dielectric.

Schematic cross-section of lateral p-type GaN transistor with slanted channel (10.1)

Next we have an invited talk (10.5) on “Superior Performance of SiC Power Devices and Its Limitation by Self-heating” by T. Terashima of Mitsubishi Electric, followed by a paper looking at the 3D scaling of IGBTs (10.6), giving lower on-resistance.

The last two papers go back to SiC devices, with a description of a vertical p-type SiC MOSFET with enhanced breakdown voltage (10.7), and 10.8 is a study of hysteresis in subthreshold drain current in SiC n-MOSFETs, caused by hole capture in border traps.

Session 11: Memory Technology — Charge Based Memories and Scaling

In this second session of the Memory track, we move to other forms of memory and embedded memory. Renesas and Hitachi have worked out a way to build split-gate MONOS flash on finFETs (11.1); then Samsung gives an invited review “A New Ruler on the Storage Market: 3D-NAND Flash for High-density Memory and its Technology Evolutions and Challenges on the Future” (11.2). We have seen 3D-NAND flash go from 24 – 32 – 48 – 64 layers in the last four years, and all four of the flash manufacturers are now in volume production; this review should cover off that evolution, as well as discuss some of the challenges as the process complexity increases.

Macronix has stated that they plan to join the 3D-NAND business, and in 11.3 they study instability caused by the grain boundaries in the polysilicon channel of vertical flash structures. Another invited talk is next, this time by Bosch (11.4), discussing the qualification of non-volatile memories (NVM) for automotive applications, and the resulting requirements for the NVM supplier, and the implications for design and technology of NVMs.

Paper 11.5 is a study of a ferroelectric transistor (FeFET) based eNVM retrofitted into GLOBALFOUNDRIES’ 28SLP HKMG process using an extra layer of SiHFO inserted into the transistor gate stack.

TEM cross-sections of GF 28SLP transistors (left), and FeFET device (right), showing the extra SiHfO layer (11.5)

The next paper (11.6) has an intriguing abstract – how to convert ZrO2-based DRAMs (i.e. most DRAMs) into NVMs – I look forward to the details! The last talk details a tantalum-oxide based selector device that can be formed in a crossbar array, and fitted into the back-end process sequence (11.7).

Session 12: Nano Device Technology — Negative Capacitance and New Material MOSFETs

In this session we have a series of papers on ferroelectric negative capacitance (NC) devices, mostly using HfZrOx. The first describes a NC-finFET with a 1.5-nm thick HfZrOx layer (12.1), then we have HfZrOx germanium (Ge) and Ge-tin p-MOSFETs (12.2), followed by a study on a HfO₂ NC-FET, looking at its polarization-limited operating speed (12.3).

12.4 simulates sub-10-nm NC-finFETs, showing excellent short-channel performance; 12.5 examines InGaAs MOSFETs with a La₂O₃ dielectric, revealing that La₂O₃ can have ferroelectric properties, and can be used to form NC-FETs; and 12.6 analyzes the hole and electron effective masses in the inversion layers of Ge (100), (110) and (111) p- and n-MOSFETs.

Session 13: Optoelectronics, Displays, and Imagers — Focus Session: Quantum Computing

This Focus Session features invited papers describing several technologies to fabricate quantum bits (qubits), including transmon qubits, spin qubits in silicon, and FDSOI qubit technology with silicon nanowire field-effect transistors. There are also discussions of quantum technologies based on luminescent crystalline defects in diamond, and the prospects of scalability, considering the potential fabrication of large-scale systems with millions of qubits.

• “Quantum Computing Within the Framework of Advanced Semiconductor Manufacturing,” by J. S. Clarke et al, Intel/TU Delft
• “Spin-Based Quantum Computing in Silicon CMOS-Compatible Platforms,” by A.S. Dzurak, University of New South Wales
• “Coupled Quantum Dots on SOI as Highly Integrated Si Qubits,” S.Oda, Tokyo Institute of Technology
• “SOI Technology for Quantum Information Processing,” by S. De Franceschi et al, CEA/University Grenoble Alpes
• “Cryo-CMOS for Quantum Computing,” by E. Charbon et al, Delft University of Technology/EPFL/Institut Superieur d’Electronique de Paris/Tsinghua University/Univ. California, Berkeley
• “Diamond–A Quantum Engineer’s Best Friend,” by Marko Lončar, Harvard University
• “Large-Scale Quantum Technology Based on Luminescent Centers in Crystals,” by M. Trupke et al, TU Wien/University of Vienna/Nippon Telegraph and Telephone/National Institute of Informatics (Japan)

Session 14: Modeling and Simulation — 2D Materials and Organic Electronics

Back in session 5 we had some MoS₂ papers, and 14.1 is a study on two MoS₂ transistor types, a lateral heterostructure FET and a “planar barristor”; then we have an invited review (14.2) of “Physics of Electronic Transport in Two-dimensional Materials for Future FETs” by Massimo Fischetti from U. Texas (Dallas).

Next up is an atomic-scale simulation of silicon contact with MoS₂ (14.3), and 14.4 is an examination of graphene/semiconductor contacts for a range of materials. Paper 14.5 predicts the performance of InAs, InN, InP and InSb double-gate, single-layer n- and p-type transistors; and 14.6 is an invited review of the “Current Status and Challenges of the Modeling of Organic Photodiodes and Solar Cells”, by R.R. Clerc of the Institut d’Optique Graduate School.

The session finishes with a discussion of ultra-thin nanowire gated 2D-FETs, focusing on dielectric growth and channel formation (14.7). In one example, a thin (6nm) conformal Al₂O₃ dielectric was formed around Co₂Si nanowires on a carrier wafer, and were then gently pressed against a MoS₂ substrate to transfer them – this avoids having to deposit the dielectric on the MoS₂. The curvature of the nanowire ensures that only a short section of it is in contact with the 2D layer, creating a short channel length.

Schematic illustration of a nanowire-gated 2D FET (left), and TEM cross-section of a fabricated device (14.7)

Session 15: Characterization, Reliability and Yield – FINFET and Nanowire Device Reliability

Samsung is first up this session, characterizing the reliability of their 10-nm process technology (15.1). They presented the basics of it at VLSI at VLSI this year [1]; they described it as:

“Fin and dummy Si gate were defined by sidewall image transfer using a mandrel and sidewall space. 3rd generation Fin features more vertical and thinner shape than previous technologies, which allows for stronger control of the short channel effect. Highly doped S/D with 3rd generation epitaxial process is combined with advanced contact process to boost performance. Copper interconnects were fabricated using conventional immersion bi-directional patterning and CVD-liner process.”

And these are some of the design rules:

In addition to reliability studies, the paper will describe describe process optimizations that overcome problems such as self-heating effects caused by the taller and narrower fin shape.

TSMC contributes an invited talk (15.2) on a similar topic “Consideration of BTI Variability and Product Level Reliability to Expedite Advanced FinFET Process Development”, and we get into serious detail in 15.3 with a statistical model of NBTI degradation of p-finFETs.

IBM reports on hot-carrier reliability in gate-last SiGe-channel p-finFETs in 15.4, and we have a post-mortem study of dielectric breakdown in finFETs in 15.5, including TEM/EELS/EDX analysis; and, according to the abstract “The assumption that the kinetics of failure would remain the same for both planar and FinFET devices is proved to be untrue.”

15.6 is an imec review of self-heating in finFETS and gate-all-around nanowires (GAA-NWs), and 15.7 continues the theme, exploring thermally-aware transistor design to reduce self-heating of floating-body devices such as FD-SOI, SOI-finFETS, and GAA-NWs.

We finish with an invited presentation (15.8) on nano-thermometry, using an AFM-based tool to look at localized hot spots in nano devices.

Session 16: Circuit and Device Interaction – Resistive Device Designs for von-Neumann Computing and Beyond

One of the trends in recent years has been the application of resistive RAM for neuromorphic computing; it appears that RRAM memories have the advantage in that they can hold a range of resistive states that can correspond to the “shades of grey” in human thinking.

The second session in this track continues that theme. The first paper examines the use of vertical RRAM for language recognition (16.1). Here, the RRAM is vertically oriented, whose physical structure corresponds to the team’s hyper-dimensional computing algorithm. This 3D-VRRAM allowed the computing framework to recognize words in 21 different languages from sample texts.

The next paper (16.2) details a binary neural network using 16-Mb RRAM devices for image recognition; 16.3 discusses a novel non-volatile flip-flop with a single RRAM NVM included; 16.4 describes a 50 x 20 crossbar switch block with two a-Si/SiN/a-Si varistors for non-volatile FPGAs; and a 4-transistor NV-SRAM with two RRAMs (4T2R, instead of the usual 6T SRAM cell) is fabricated in TSMC’s 40-nm process in 16.5.

16.6 is a higher-level study of a fully connected neural network using arrays of OxRAM devices, and applying short- and long-term plasticity rules, suitable for (e.g.) visual pattern extraction from highly noisy data.

Image reconstruction is used as a diagnostic tool to evaluate the device variability in memristor crossbar arrays in 16.7, and 16.8 demonstrates unsupervised learning by spike-time dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP) in neural networks using CMOS-based RRAM synapses.

Finally, it’s time for lunch! This year’s speaker at the conference lunch is Prof. Roberto Cingolani from the Istituto Italiano di Tecnologia in Genoa, Italy, presenting on “Translating evolution into technology: from biochemical robots to autonomous anthropomorphic machines”. We are used to the concept of living creatures evolving over time – here we will have a comparison between living and artificial systems, and the attempts to reproduce the characteristics of living things using technology.

Tickets are available online when you register – if you haven’t, there are usually some at the conference front desk. The afternoon sessions start again at 2.15.

Part 2 of the preview will be up in a few days, before the conference!

By Dick James, Senior Technology Analyst, Chipworks

One of the lesser-known stories of mobile phone evolution is the development of proximity sensing in order to save power and disable touch-screen functions when the phone is actually being used as a phone. This essentially means turning off the screen (and the touch-capability tasks) when the phone is brought up to the ear.

In the very early days there was no such thing; then a simple photodiode was used to sense the change in light level. This worked in most circumstances, but under certain conditions (e.g. an old guy with a white beard) it didn’t, to the embarrassment of the manufacturers. With the screen on, of course, the touch function still works, and an inadvertent touch could hang up the call. Apparently the iPhone 4 got a bad name for this particular fault.

So active systems were introduced, usually with an LED in combination with light sensors to sense the change in light as the phone comes to the face, and then confirm facial proximity with active illumination from the LED. If the proximity sensor receives reflected light above a pre-defined threshold level, it turns the screen off; and of course this threshold level has to be set so that it functions in close to 100% of situations, irrespective of the reflectance of the adjacent surface.

Now we are seeing a further step in the sequence in the transition from the iPhone 6s to the iPhone 7. The 6s used the LED + sensors option, but the iPhone 7 appears to have gone to the next stage and introduced a time-of-flight (ToF) sensor.

The advantage of ToF is that is doesn’t depend on reflected light level – it actually measures the time of travel of photons emitted from a laser diode, and this travel time is independent of the reflectance of the target surface.

We first saw a ToF sensor in the Blackberry Passport, which introduced us to the concept, and the STMicroelectronics VL6180. This is a three-in-one smart optical module, incorporating a proximity sensor, an ambient light sensor, and a VCSEL light source. We subsequently found it in a few more phones:

The proximity sensor is actually an array of single photon avalanche diodes (SPADs), which fortunately can be integrated into a regular CMOS process.

The VL6180 actually has two SPAD arrays on-die, together with the ambient light sensor:

The VCSEL is co-packaged with the die to give the complete unit.

In January, ST announced its second-generation sensor, the VL53L0, which we also found in half a dozen phones this year, all from the Asia-Pacific region (don’t forget that Motorola is now Lenovo).

Both of these were used as range-finding devices for the primary camera, not as proximity sensors for phone operation. The VL53L0 has dispensed with the ambient light sensor, and the SPAD arrays have been modified.

Now we get to the iPhone 7 – when we looked at the selfie camera side, and took out the sub-assembly, both the ambient light sensor and the LED/sensor module were different from those in the 6s model.

When we take them off and look at the module, it looks very ST-ish:

And when we get the die out, it is not the same, but definitely is similar style and die numbering (S2L012AC) to the VL53L0/S3L012BA die, with the two SPAD arrays, and this time the VCSEL is bonded on top of the ToF die to give a very compact module.

So we think we can come to the conclusion that the proximity sensor is now a ToF sensor – and it can also act as an accurate rangefinder for the selfie camera. Nothing announced by either Apple or STMicroelectronics, but yet another of the subtle improvements that we see in the evolution of mobile phones. It was also in the 7 Plus, so a good design win for ST.

We also looked at the ambient light sensor, which was actually the same as in the iPhone 6s, and looks fairly conventional. We don’t know who makes it, but it does have Star Trek’s Starship Enterprise on board!

By Dick James, Senior Technology Analyst, Chipworks

As usual, within days of the August 19 launch of the Samsung Galaxy Note 7, we had it in pieces and had identified most of the significant components that were inside.

APU and memory

The application processor that drives our phone is the Exynos 8 Octa (Exynos 8890), similar to the Galaxy S7 and S7 edge. It has an eight-core CPU, with four Samsung-designed M1 cores that can run at 2.3 GHz, and four ARM Cortex A53 cores operating at up to 1.6 GHz. The graphics side of the chip uses an ARM Mali-T880 MP12 GPU (with 12 graphics cores). It has a LTE Category12/13 modem and is made with their latest 14LPP finFET process.

Stacked on top of the CPU in the usual package-on-package (PoP) stack, is 4 GB of Samsung LPDDR4 SDRAM. Now that we have 20 nm DRAM processes, the dies are small enough that they are packaged in a 2 x 2 x 2 configuration. Here is the plan-view X-ray image showing the wire bonding of the memory chips. The four stacks of two 4-Gb memory dies are mirror-imaged, on both the vertical and horizontal axes.

The dies are just about square (5.4 x 5.1 mm); the use of two-die stacks reduces the package thickness to 0.5 mm. This may be the first time we have seen this particular layout.

The 64 GB of flash memory was supplied by a Toshiba THGBF7G9L4LBATR UFS 2.0 part, fabricated using the latest 15 nm generation process.

Cameras

There are three cameras in the Note 7: the usual front- and rear-facing units and an extra one for the iris-scanning security feature of this phone. The main camera is 12 MP with optical image
stabilization (OIS) provided by a STMicroelectronics L2GIS 2-axis gyroscope, the middle chip in this picture:

The selfie camera is a 5 MP Samsung part and the iris scanner is also Samsung-made, but we have not yet characterized it as to size and technology.

Sensors

STMicroelectronics supplies all the MEMS motion sensors in the Note 7. In addition to the OIS sensor, there is a LPS25HB pressure sensor and a LSM6DS2 6-axis gyroscope/accelerometer module. All of these have many design wins in phones and wearables.

In addition to the motion sensors, there is an infrared proximity sensor, a heart-rate sensor, and the now ubiquitous fingerprint sensor. The proximity and heart rate sensors appear to be Samsung products, while the fingerprint sensor is reported to be from Synaptics.

RF front end

The RF front end in a phone these days is a very complex thing. The connectivity specification covers a multitude of bands (2G, 3G, 4G LTE-A), as well as Wi-Fi (802.11 a/b/g/n/ac), Bluetooth v4.2, GPS, A-GPS, GLONASS, BDS, GALILEO, NFC, and wireless charging.  It’s no wonder that we have quite an inventory of parts in that area of the phone:

Touch controllers

The touch control function seems to be distributed in the Note 7, possibly since we also have the S-Pen capability. There is a Cypress CY8CMBR3145 CapSense® Express™ controller, a Samsung S6SY661X, and a Wacom W9018 digitizer, which apparently assesses the different pressure levels applied by the S-Pen to the screen.

Power management

As with every other smartphone, there are multiple power management ICs (PMICs), in this case five:

And what about the batteries?

It’s now well known that, due to some phones exploding or catching fire while being charged, Samsung has launched a recall of the millions of Note 7s already shipped. On their UK website, they clarified that “An overheating of the battery cell occurred when the anode-to-cathode came into contact, which is a very rare manufacturing process error.” In other words, something in the battery shorted out, likely because a separation membrane within the battery was defective.

The problem takes me back to the New Year (after Christmas), when there was a spate of hoverboards catching fire – they also use lithium-ion (Li-ion) batteries, only bigger. As a consequence, K.M. Abraham of Northeastern University published a useful explanation of what happens when Li-ion batteries fail.

“It is safe to say that these well-publicized hazardous events are rooted in the uncontrolled release of the large amount of energy stored in Li-ion batteries as a result of manufacturing defects, inferior active and inactive materials used to build cells and battery packs, substandard manufacturing and quality control practices by a small fraction of cell manufacturers, and user abuses of overcharge and over-discharge, short-circuit, external thermal shocks and violent mechanical impacts. All of these mistreatments can lead Li-ion batteries to thermal runaway reactions accompanied by the release of hot combustible organic solvents which catch fire upon contact with oxygen in the atmosphere.

The specific heat of a typical Li-ion cell has been measured experimentally to be 1 joule per degree Kelvin per gram. A state-of-the-art 18650 Li-ion cell with 3.2 Ah capacity and an average voltage of 3.6V produces 11.5 Wh (41400 Joules) of energy. The weight of the 18650 cell is about 46 grams.

We can calculate that the 41400 Joules of heat will raise the temperature of the 46 gram cell by 900 °C under adiabatic conditions if a short-circuit or another event causes a thermal runaway reaction. That means that if an 18650 Li-ion cell operating at 20 °C short-circuits its temperature under adiabatic conditions can rise as high as 920 °C.”(!!)

Below is a picture of the battery in the phone we dismantled (left), and it’s 3500 mAh (= 3.5 Ah), and 4.4 V, so we have 15.4 Wh of energy in it, 34% more than the unit quoted above; we don’t know the weight, but clearly your phone could get up to ~900 ^oC or more if the battery is faulty.

Note the “Cell Made in China, Assembled in Vietnam” on the battery. Out of curiosity, we checked out the iFixit teardown of the Note 7, and noted that their phone had a different battery (right).

The iFixit phone reads only “Made in China”, so there are two battery sources. If you look closer, model EB-BN930ABE (left) is from Vietnam, and model EB-BN930ABA (right) is the Chinese version.

The Korea Herald added a bit more detail and confirmed the two battery sources as company affiliate Samsung SDI, supplying 70% of Note 7 batteries, and Chinese company ATL, supplying the remaining 30%.

The whole issue is further complicated by the non-removable nature of the batteries in the phone, necessitating a full recall. Unfortunately, we can no longer send ours in to get it replaced!

By Dick James, Senior Technology Analyst, Chipworks

July 11 – 15 was the week for the annual pilgrimage down to the SEMICON West show, though it’s becoming less of a show these days than a gathering place for the industry, with multiple conferences in parallel. Hence the motto for the event, “Definitely Not Business as Usual.”

Of course there were exhibitors, some 700+ I’m told, and we’ll have to wait for the post-show release to see how many attendees. From my observation, things were busy without being hectic on the show floor, and there was the usual slew of press releases and social media postings from both exhibitors and attendees.

One such was a tweet from the French wafer manufacturer Soitec, which specialises in SOI wafers, having pretty well cornered the market with the success of their Smart Cut™ technology. They announced a “new identity”, complete with a new logo, in time for the show and in advance of their AGM on July 25.

While I was at SEMICON West I had the chance to meet with Camille Dufour and Tom Piliszczuk of Soitec – we have seen increasing amounts of SOI devices in the phones that we analyze, so I was curious to find out what their range of materials was and what markets they were targeting. We have all followed the finFET/FDSOI debate in the last few years, and some still doubt that FDSOI will take off; but RFSOI and power SOI are making steady gains in the wireless and automotive sectors.

The logo change is straightforward enough:

The “new identity” reflects a structural change within Soitec in the last year or two. A while back Soitec had decided to leverage their Smart Cut and Smart Stacking techniques to get into the solar cell and lighting businesses. Technologically they did quite well, getting to almost 50% efficiency for solar cells; but they were targeting the concentrated photovoltaic (CPV) market, which turned out to be a much more niche market than they anticipated.

Consequently the balance sheet started to suffer, to the point where some of their customers questioned the viability of the company. So at the beginning of last year the decision was taken to get out of the PV and lighting businesses, and focus on their core business of electronic materials. They also sold off their Altatech equipment subsidiary to Fogale Nanotech.

By the middle of this year all of the financial details were cleared up, and Soitec came back into operating profit. There was still a bit of a financial hangover from the discontinued operations, so a capital investment was arranged and a chunk of the company’s debt was paid off.

All of which is a roundabout way of saying that Soitec now regards itself a re-generated company based solely on the manufacture of electronic materials, so worth an announcement in time for Semicon West, the prime event for semiconductor materials suppliers.

If you peruse the products section of the website, you will see they sell four streams of SOI wafers:

• Digital SOI, which covers off partially-depleted and fully-depleted SOI (PD-SOI and FD-SOI)
• RF-SOI
• Power SOI
• Photonics SOI

Digital SOI is in a bit of a holding pattern right now; PD-SOI is in a slow decline as legacy game console parts and AMD processors fade away, and though IBM is still using PD-SOI for its Power series of processors, that is a fairly niche business and unlikely to consume huge volumes of wafers. (IBM once had the bulk of the game chip business, making chips for Microsoft, Sony, and Nintendo.)

When it comes to FD-SOI, we have seen a lot of hype, but from our perspective, no serious production yet. Soitec says that volume is now into the thousands of wafers per month, and will hit tens of thousands by the end of the year. Some products using FD-SOI have been announced, such as the NXP (formerly Freescale) i.MX 7 and i.MX 8 series of processors. Two foundries are on board, GLOBALFOUNDRIES with their 22FDX suite of processes, and Samsung with their 28 FDSOI offering; both claim multiple tape-outs are in progress (50+ for GF), and Samsung’s Kelvin Low at Semicon West stated that they had shipped thousands of wafers. And both agree that FD-SOI is ideal for IoT, but again we have yet to see volume; so it’s a waiting game at the moment.

FD-SOI is real, though – here’s a cross-section of transistors in a Bitcoin processor chip that we looked at last year.

This was fabbed by STMicroelectronics in their Crolles fab, you can see that it is gate-first HKMG with no SiGe channel used for PMOS, as in PD-SOI. The SOI layer is ~6 nm thick, so definitely FD-SOI!

Overall PD-SOI and FD-SOI, being 300-mm wafer product, make up ~20% of sales, the remaining 80% are 200-mm wafers.

70% of those 200-mm wafers are RF-SOI, which has grown steadily due to its adoption into the RF front end of mobile phones, especially in world-phones that have to cope with more than 40 wireless bands. Soitec claim that there was 18 mm² of RF-SOI in the iPhone 6, and 25 mm² in the iPhone 6s, and we at Chipworks/TechInsights have certainly seen increasing amounts of SOI-based parts in the RF section of the phones that we analyze. The company asserts that 100% of smartphones have their silicon in them these days.

This (together with power SOI, which we will discuss later) has kept Soitec’s 200-mm Bernin fab at full capacity for the last few months, and they expect to ship a million 200-mm wafers this year. Last year the total was 700,000 wafers, and next year they expect it to be 1.3M wafers, though some of these may be from licensees Shin-Etsu and Sun Edison. Soitec has 70% of SOI wafer sales worldwide.

Apparently there are now over ten foundries using SOI, mostly 200-mm, but Tower-Jazz has announced that its TPSCo subsidiary in Japan will be processing 45-nm, 300-mm RF-SOI, and GLOBALFOUNDRIES is now also offering 45-nm RF-SOI; I heard verbally that will be from the East Fishkill fab, but I can’t find documentary support for that at the moment.

Back at the end of 2013, Soitec announced the addition of “trap-rich” RF-SOI technology to their product line, as an enhanced performance substrate for RF products.

As I understand it, the trap-rich layer is a layer of polysilicon formed on the handle wafer, and the multiple traps in the crystal grains and grain boundaries kill any parasitic currents that could be induced by the RF radiation, even in a high-resistivity (HR) substrate. This enables “RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies.”[1]

I was curious to see what the penetration of this new technology was into RF product lines, and was surprised when Tom told me it was 55%, and it had replaced most of the regular HRSOI wafers that they had been selling, even with a 25% cost mark-up (presumably the polysilicon process is VERY specific). He said that manufacturers were willing to pay the higher price because of the improved performance, and it also saves two mask layers. At the moment it’s all 200-mm wafer sales, though 300-mm wafers are available.

As an example of the leading-edge RFSOI, here’s a SEM cross-section of a Murata/Peregrine antenna switch die from one of the RF front-end modules in the iPhone 6s:

The SOI layer is well under 100 nm thick, but we are not into FD-SOI yet, even though some claim that RF can be integrated into FDSOI! As it’s a SEM image with oxide staining, we can’t see if there is a trap-rich layer; that would take a different stain or TEM imaging to show it up.

Moving on to Power SOI, it is now present in 50% of cars, according to the company, with ~70 mm² used per vehicle on average. Automotive usage is the largest sector, followed by industrial, and “other”:

The auto sector has been expanding steadily for the last decade, due to the increasing use of automotive transceivers (CAN/LIN/FlexRay, over 50% in SOI), and class-D amplifiers in infotainment systems. On the industrial front, the driving products have been AC/DC converters, motor drivers, and Power over Ethernet.

The higher voltages and harsh environment have a lot to do with SOI migrating into these spaces – junction temperatures can get up to 225°C, and the dielectric isolation of the buried oxide helps with high-voltage operation, electrostatic discharge (ESD), and electromagnetic interference (EMI) protection. And of course it is inherently radiation-hard for particulate radiation such as alpha-particles or neutrons, great for space and military applications.

In terms of the design considerations, the use of SOI eliminates parasitic latch-up, and the ability to use oxide isolation between circuit elements saves space when compared with diffused isolation in BCDMOS (bipolar-CMOS-DMOS) processes.

This can give a die size reduction of 40 – 50%, depending on the design, so well worth considering even with a higher-priced start wafer.

Photonics SOI uses a different benefit of the buried oxide layer – the ability to confine photons within a silicon waveguide. In yet more of those fortunate properties of silicon, it transmits infra-red light at 1.3 – 1.6 µm, matching the wavelengths used in fibre-optic cables; and there is a large refractive index (RI) contrast between Si (n~3.5) & SiO₂ (n~1.5), giving good total internal reflection to silicon waveguides on oxide.

Schematic of SOI optical waveguide

The higher refractive index also means that the wavelength is shorter in silicon, so we can have much tighter turning radii than in oxide, allowing sharp bends in photonics chips. Add to that the capability of tuning the RI by tuning the doping, and manipulating the light by applying a voltage and injecting carriers to adjust the phase, and we can do photonic processing as well as the usual digital and analog electronic processing.

The main application at present seems to be photonic transceivers, both inside and outside systems, but there is plenty of R&D looking to take advantage of the potential, particularly as data rates move towards 100 Gb/sec.

Currently total production is only about 10,000 wafers/year, but being targeted mainly on interconnect inside and outside data centres, that is a low volume, high value part of the business. Looking to the future, Soitec expects that the growth in data as 5G arrives will push the need for photonics products, and Tom speculated that the high data rates required for 4K/8K virtual reality systems may also drive a consumer need for optical links to the headsets.

Almost four years ago Chipworks analyzed a Luxtera chip from a Molex active fibre optic cable, fabricated by Freescale (at the time, now NXP) in a 130-nm CMOS/photonic SOI process. Here’s an optical plan-view image of a pair of waveguides turning 90^o:

Wide multi-mode waveguides come in from the left, narrow down and become single-mode waveguides before they turn 90^o with a radius of 30 µm and exit at the top of the image.

Here we show a TEM cross-section of the narrow part of the waveguide:

The deep STI through to the buried oxide isolates the waveguide structure, and the shallow STI in the structure confines the optical signal to the central mesa. The extra width and the outer ribs likely act to give mechanical stability and even out the stress in the central mesa, and there is a silicon nitride layer over the waveguide which acts as a silicide mask. They are in general uniformly doped, but when they become part of a Mach-Zender interferometer (MZI), a P-N diode is formed in the waveguide in order to modulate the phase of the optical signal by varying the reverse bias on the diode. Below are junction-stained SEM and scanning capacitance microscopy (SCM) cross-sections of one waveguide in a MZI. In the SEM image, the copper metallization has been etched out, but we can see the pairs of contacts to the SOI to bias the diode.

SEM and SCM cross-sections of waveguide in Mach-Zender interferometer

Germanium photodetectors are formed selectively on the SOI for receive and signal-monitoring functions, and a laser diode module is mounted on the die for transmit capability.

It is obvious from this example that SOI is an almost ideal material for part of the integrated photonics systems that we will need in the not-too-distant future. Unfortunately silicon is not good for generating light, and we still need the interface to cable, so photonics chips will have to be part of an integrated assembly.

Intel made it clear last year at their Data Center Day that they consider silicon photonics a key part of their “Data Center Connectivity Landscape”, from within-rack connection to across the data center itself, which can involve kilometers of interconnects:

They also see ~50% growth in the market in the next few years:

And it is clear from the new roadmaps (Photonic Systems Manufacturing Roadmap, and Heterogeneous Integration Technology Roadmap for Semiconductors) that technology and cost pressures are driving developments both in volume wafer manufacturing and wafer level assembly, as well as other areas such as optical through-silicon vias.

So, if we look at all the above applications, and include the predictions for FD-SOI, Soitec not only has bounced back from its travails of a few years ago, but as the main player in the SOI wafer business, it seems to have a solid future coming up.

Reference:

• Soitec white paper “Innovative RF-SOI Wafers for Wireless Applications”

By Dick James, Senior Technology Analyst, Chipworks

A bit earlier than usual, the IEDM (International Electron Devices Meeting) press kit is available, and among the announcements are a couple of surprises.

The biggest practical change is the addition of an exhibit hall – up to now the conference has been almost religiously anti-commercial, to the extent that forums (fora?) sponsored by (e.g.) Applied Materials, ASM, and Synopsys have had to be held offsite in other hotels.

To quote Tibor Grasser, IEDM 2016 Exhibits Chair, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

There is an element of truth to that, since many of the papers are authored by the R&D groups from equipment companies, and having some systems on site may help cross-fertilise ideas and techniques. Of course, a contribution to conference funds in the form of space rental always helps, too.

Another change is that the submission deadline for papers has been delayed to August 10, though there’s a twist to that too – accepted papers will appear without any modification; so BEWARE, your typos and other errors will follow you into perpetuity. Still, the later date is a good thing, in previous years submissions had to be almost six months before the conference, so finalised work could be almost a year old before presentation. There is still an opportunity for late-news papers to be submitted by 12^th September.

Other than those changes, the conference follows its usual timeline from December 3^rd to December 7^th – tutorials on the Saturday, short courses on Sunday, plenary talks Monday morning, then likely eight parallel sessions of papers, wrapping up on the Wednesday afternoon. Interspersed through this will be the Monday evening reception, Tuesday conference lunch and evening panels, and the Entrepreneurs lunch on Wednesday.

There may also be off-site gatherings or hospitality suites; Applied Materials, ASM, Synopsys, and Silvaco have sponsored them in the past.

I would go through the schedule in more detail, but handily the Solid State Technology editorial staff have done that already. Once the full program is published, I plan on drafting my usual pre-conference review sometime towards the end of November. The conference is now in its permanent location at the San Francisco Union Square Hilton, no more visits to Washington DC.

Notes from Day 1 can be found here.

Notes from Day 2 can be found here.

By Dick James, Senior Technology Analyst, Chipworks

Day 3 was just a morning session, with China being the topic. Sunny Hui, SVP Worldwide Marketing for SMIC, gave (for me) a notable keynote on “Collaborate to Win in the China Market”.

Sunny started by giving some background to China’s economic and technological growth; gross domestic product (GDP), for example, has increased by 35x in the last 30 years, to $10.4 trillion, and 40% of worldwide semiconductor shipments go to China (more is spent on semiconductors than on oil!). Depending on the segment, these semiconductors go into the 70 – 90% of electronics products that are made in China and exported. And Chinese brands are becoming well known in world markets – Huawei, Haier, Lenovo and others are no longer strange names to us in North America and Europe.

Specifically referring to SMIC, we were shown a teardown (something I recognise!) of the Huawei P8 phone, with six parts fabbed by SMIC inside it.

Huawei P8 phone teardown with SMIC-made parts highlighted

The rise in China (and elsewhere) of ubiquitous big data, driven by cloud usage and IoT, pressures users to choose the right technology node for their chips, which gave Sunny a chance to show the SMIC technology portfolio;

Which looks like a challenging range of processes to me! (SPOCULL = SMIC Poly on Contact Ultra Low Leakage.) We were also shown some SMIC finFETs, the first that I have seen.

They now have three 300-mm fabs (Shanghai and Beijing 1 &2), and five 200-mm fabs, with one dedicated to the MEMS, imager and 3D IC specialty platforms, and another to bumping, WLCSP and testing; and they are aware of the need for patent coverage, having filed over 12,000 patents. They claim to be the most preferred foundry among Chinese fabless companies, with revenue from them growing at a 30% CAGR over the last ten years. SMIC has also set up a joint venture with JCET (SJSemiconductor, based in Jiangyin), focusing on wafer-level packaging technology.

In the Q&A session, someone asked if FDSOI was on the roadmap – apparently, nobody is asking, though it’s possible – the focus is still on finFETs. And 28-nm HKMG is now in production.

Next up was Ed Pausa from PricewaterhouseCoopers (PWC); I thought I was an old stager in the business these days, having started in 1970, but Ed started with Fairchild in 1959! PWC recently published a report on China’s impact on the semiconductor industry (available here), and Ed went through it in considerable detail. It appears that China’s semiconductor consumption hit a new record in 2014, at 57% of the worldwide market, and it’s been over 50% for the last four years.

When it comes to revenue, China’s semiconductor industry grew by 17.5% in 2014 to a record US$$77.3bn, making up 13.4% of worldwide semiconductors. That breaks down into 22% IC design, 15% manufacturing, 26.5% package & test, and 36.5% optoelectronics, sensors and discretes.

The gap between consumption and production continues to grow, however, to $140Bn in 2014, and it is expected to keep on growing, despite well-publicised government attempts to reduce it.

As of 2014, there were 165 wafer fabs there, of which ten are 300mm. There are now reported to be more than 660 design houses, though PWC estimates that no more than 100 are actually viable fabless companies. At the packaging, assembly and test end of the spectrum, there were 120 facilities, which gave China 33% of this type of worldwide floor space, the largest share.

In 2014 SK Hynix topped the table of semiconductor revenue, followed by HiSilicon and SMIC. Only four of the top ten appear to be domestic Chinese companies, the others are all subsidiaries of foreign multinationals.

After Ed it was my turn to speak, and the topic of my talk was “China’s Penetration into Mobiles – Real or Imaginary?”, which gave me the chance to show a few teardowns of Chinese-made phones, and do a comparison with the iPhone SE. I started with a quick look at some smartphone statistics – by coincidence ICInsights had published them a week before The ConFab;

And we can see that eight out the top twelve companies are China-based. Then I did a quick run through design wins by Mediatek, Spreadtrum and HiSilicon, before getting into the teardowns.

First we looked at a Huawei Mate 8, a high-end phone targeting the same space as the Samsung Galaxy 7 and the iPhone. This has a complex bill of materials (BOM), but the lead chips are from Huawei’s subsidiary HiSilicon, including their Kirin 950 application processor fabbed in TSMC’s 16FF+ process.

Then we had a value 4G device, the JXD T5 (Blaster Mini) one of the top 10 phones in the Asia-Pacific region in March. Now that we have moved down-market, it is less complex, focused on Chinese cellphone bands, and with a cheaper camera. Mediatek dominated the silicon here, but the touchscreen controller and camera were also Chinese, from Focaltech and Omnivision.

When we get to basic 2G/3G phones (a Lenovo T2 and a Lava Iris Atom), the only non-Chinese chips are the memories and the accelerometers – everything else originated from China, including the RF front end.

For comparison we then examined the Apple iPhone SE, which of course is a complex worldphone; the winners here (apart from Apple’s own designs) were Qualcomm and Texas Instruments, and in the RF front end, Qorvo and Skyworks.

In part my talk was a not-so-subtle sales pitch for our new “Inside Technology” service, which is basically a subscription portal to our database of teardowns and parts analyses – in the case of semiconductor processes, down to the atomic scale, since it includes access to TEM images and materials analyses. Since we’ve been doing it for over twenty years, that’s a lot of data!

As with many product launches, we’ve made a video – I think it’s quite impressive, but then I am a little biased, since in the case of the teardowns, I showed, it was the tool that I used to compile the design win information and the teardown BOMs for the different phones, and in the iPhone I showed that we can see that the QFE1100 envelope tracker chip was used in 67 different phones, and that there were three different versions from two different foundries.

Then we had a quick look at patent landscapes for Mediatek, Huawei, and Apple, and the penultimate slide told the story that I was focused on; using ICInsights’ categorization of the types of chips in a mobile phone, Chinese-made chips are in seven of the eight categories.

In retrospect I should not have included Mediatek, since they are Taiwan-based, but that does not change the essential nature of the story, that China-designed and fabbed chips are making their way into mobile phones, especially at the value end of the market.

 
Given my liberal use of ICInsights’ information as background for my talk, it was slightly ironic that the final keynote speaker was Bill McClean himself, of ICInsights.

Bill started out with the background that in the last decade our IC industry cycles have morphed from a capacity/capital spending driven cycle to one that is much more controlled by world GDP.

Then he moved on to China’s role in the IC world, echoing Ed Pausa’s comments that the IC consumption vs IC production gap is growing, and their government is making a well-funded push to reduce that gap. His slightly surprising conclusion (at least to me) is that this effort is failing.

His contention is that there is not yet a strong indigenous pure-play foundry industry, nor a strong presence in the fabless IC supplier space, since fabs there only take ~7% of the world market (and that includes foreign-owned fabs), and the fabless companies are at 10% market share.

There have been some successes – several joint venture fabs are being set up, notably with UMC, Powerchip, and GLOBALFOUNDRIES, and on the acquisition front, (e.g.) NXP has sold two divisions to JAC Capital, and Omnivision is now China-owned. On the other hand, moves to buy Micron, Fairchild, and a chunk of Western Digital have failed, and Bill’s opinion is that any significant purchases of US-based companies are now highly unlikely, and other governments are taking a similar position.

That wrapped up the Confab for this year, just a final networking lunch to finish, and then we all went our different ways. The ConFab in 2017 will be on June 14 – 17, again at the Encore in Las Vegas.

Notes from Day 1 can be found here.

By Dick James, Senior Technology Analyst, Chipworks

The opening keynote for Day 2 was Wally Rhines of Mentor Graphics, always a lively and entertaining speaker. His topic this time was “What Will Stimulate the Next Wave of Semiconductor Industry Growth?”

Wally Rhines of Mentor talking foundry costs at his ConFab keynote

Wally started by putting Moore’s Law in the context of a learning curve, in which

• cumulative transistors produced increase exponentially with time (e.g. 2x cumulative volume -> fixed % cost decrease)
• almost all cost reduction comes from shrinking feature sizes and growing wafer diameter

That gives us a nice log/log plot of revenue/transistor vs cumulative transistors produced;

He spent the first part of his talk putting the rest of the industry segments (equipment, EDA etc.) into that context, until we got to discussing the 28 – 20 nm transition, with no cost reduction, and with a 40% cost/wafer increase as we get to finFET-based 14-nm products.

However, the transistor learning curve continues, despite these challenges, because memory, especially NAND flash memory, dominates the transistor count – 99.7% of all transistors are now in memory chips, and 80% of those are flash. Now that we are in the 3D-NAND era, that trend will only keep going, Wally claims for the next 10 – 20 years.

A major driver for this will be image storage and processing; IC Insights predicts that the image sensor market will not flatten out until it reaches 30+ billion units per year, from the current ~6 billion; aside from consumer usage, autonomous vehicles and security applications will almost certainly demand more image handling.

Wally finished up by making the point that the conventional von Neumann computer architecture is not adequate for image processing, and if the transistor learning curve does continue, then different architectures will be needed, more akin to the human brain in terms of pattern recognition and power dissipation.

The theme of the morning session was “Success in Fab Management” and featured four speakers, the first Rick Glasmann from Infineon’s 150 mm fab in Temecula, a former International Rectifier fab. He described a case study whereby they tightened up the fab process control and achieved 19% improvement in on-time delivery, and a 10% improvement in Cpk, amongst other measures.

Second up was Sanchali Bhattacharjee of Intel, describing a SEMI initiative to drive defect control within equipment, specifically the SCIS (subcomponents instruments and systems) working group. Co-optimization is not just a buzz-word for product development, it also applies across the fab supply chain from the wafer level down to the individual components within the fab manufacturing equipment – valves, pumps, RF generator, seals, etc.

The components theme continued in the next talk by Ardy Sidwha, detailing QuantumClean’s capabilities of creating Atomically Clean Surface™ surfaces on everything from quartz components to complex showerheads. It was a bit of a sales pitch, but still impressive since the need is obviously there to maximize yields and reduce cost of ownership.

The last speaker of the morning was Mike Czerniak (Edwards), who went through the efforts by the industry to get rid of greenhouse gases. That has been successful in the case of per-fluorinated compounds (PFCs) such as carbon tetrafluoride, meeting the target to limit PFC emissions to 90% of 1995 levels by 2010, a significant challenge given the growth of the industry in that time period. This was mostly achieved by the replacement of PFC CVD chamber clean gases by nitrogen trifluoride, which is efficiently consumed by the process tool.

The World Semiconductor Council has now tightened up the target for equivalent carbon dioxide emissions, looking for a 30% reduction from 2010 levels.
Mike gave an example of a fab footprint, showing quite impressive reductions in emissions going across the fab:

Equivalent CO2 emission data + abatement for a 200mm fab

Newer fabs start off with the advantage that they are designed for abatement, so the figures are actually better; though it seems that etch chemistries are more difficult, and the focus is now in that area.

After lunch we had set of four presentations preceding another panel, this time focusing on system level integration via packaging.

Bill Bottoms of 3MTS was the first up, noting that we have seen the final edition of the ITRS roadmap; essentially, CMOS has run out of steam. In its place we have a plethora of new roadmaps (or at least four) – the International Electronics Manufacturing Initiative (INEMI) Roadmap, the International Roadmap for Devices and Systems (IRDS), the Photonic Systems Manufacturing Roadmap (PSMR), and the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS).

Bill went on to describe HITRS, sponsored by IEEE CPMT Society, The IEEE Electron Devices Society and SEMI. There are working groups within the overall roadmap envelope;

• Heterogeneous Integration Components
• Cross Cutting Topics (Emerging Research Materials, Emerging Research Devices, Integrated Power Devices, Interconnect, and Test)
• Integration Processes (System in Package, 2.5D and 3D, Integrated Power Devices, Wafer Level Packaging)
• Packaging for Specialized Functions (Mobile, IoT and Wearables, Medical, Automotive)

The roadmap has an active workshop schedule, with nine meetings before year end, two during Semicon West week, one at the show and one in Palo Alto.
Brian Black (AMD) gave a review of the design/packaging co-optimization (there’s that word again!) of the Fiji chip in the new AMD Radeon Fury (Fiji) graphics processor. This is notable in that it uses the Hynix High-Bandwidth Memory (HBM), together with a silicon interposer, to give 60% higher memory bandwidth for 60% less power than GDDR5 memory.

AMD’s Fiji chip

As an illustration of the benefits of this type of integration, the GPU is made in 28nm technology, and the HBM is 25nm generation, and the performance is better than a competing graphics unit using 20nm logic and 20nm DRAM.

Islam Salama of Intel then detailed their approach to increasing memory bandwidth; one of their metrics is the number of I/O wires escaping per millimeter of die edge for each layer of the package, as a way of comparing different technologies.

This can then be used to help decide the most appropriate package type for a specific product, whether it be a co-packaged e-DRAM as in the Iris Pro series of processors, or a more complex multi-chip package as used in the new Knight’s Landing series.

Intel has been promoting their EMIB™ architecture of late, and claims an advantage over the silicon interposer in that it does not need a large piece of silicon, or TSVs, but gives similar bandwidth.

Intel’s EMIB architecture

Rama Alapati from Amkor finished up; he gave a short and sweet exposition of integration trends across five key segments – mobility, IoT, auto, high-performance computing, and memory, and across those segments, Amkor’s place in the ecosystem. Considering that he had only been with the company for six weeks, he did pretty well!

The panel was moderated by Li Li of Cisco, and was also short and sweet, only half an hour or so, then a rest before the Tuesday night reception. Brian was asked if die stacking would help just as much with a 14 or 10-nm process; his answer was that a 14-nm die-stack would be better than a 7-nm fully integrated chip. Another question was about the high cost of 3D packaging, and Bill responded by saying that the high cost was due to high-aspect ratio TSVs, and most heterogeneous integration does not need them –simply thin the wafers, then 2D/3D becomes a cost reducer, not a cost adder.

All in all, a good afternoon session.

Stay tuned for a review of Day 3…

By Dick James, Senior Technology Analyst, Chipworks

The ConFab 2016 kicked off June 13 in the Encore Hotel in Las Vegas, the 12^th in the series, presented by Solid State Technology (part of Extension Media), which they promote as the “Premier Conference and Networking Event for the Semiconductor Manufacturing & Design Industry.”

The event started with a networking reception Sunday night, giving the early arrivals a chance to mingle with some good food and wine. A feature of The Confab is that networking lunches and receptions are a focused part of the agenda, and time is set aside for face-to-face meetings; these can be pre-arranged by the event staff. Attendance is usually limited to ~150 so that there is ample time for everyone to get together over the three days.

As usual, Pete Singer was the conference chair, and the keynote speaker opening the event was Tom Caulfield, SVP and GM of GLOBALFOUNDRIES’ (GF) Fab 8 in Malta, New York, speaking on “Unlocking the IoT Opportunity for the Next Golden Age.” He surprised me at the start by saying that “the best years of semiconductors are ahead of us, not behind us,” given that it is hard to see even five years ahead at the moment, and pessimists are predicting that leading edge technologies will price themselves out of the business.

Tom Caulfield evangelizing the Next Golden Age of Semiconductors

Tom then made the point that the main driver for the industry through its existence has been the evolution of connectivity, and the next phase will be as well.

And of course that takes us to the Internet of Things (IoT), currently at the peak of the hype curve, but undoubtedly a real phenomenon. McKinsey & Co. have predicted that by 2019/20 the IoT semiconductor value will be $50B – $75B, and they have broken it down nicely into segments and technologies;

What this doesn’t show is that all of the things will generate vast amounts of data, which will need a 5G communications infrastructure, which Tom described as huge, and maybe the biggest opportunity, rather than the silicon in the things themselves.

Then we moved on to the need for collaboration, the business model needs to innovate as well as the technology; though my perception is that there’s a good deal of collaboration in the industry already, though maybe not as much as needed. The GF-Samsung 14 nm agreement was mentioned (though I gather that it is 14 nm only), and design/technology co-optimization, which is now essential in the foundry business – Intel has been doing it for years.

The need for cooperation goes beyond the chip industry, though, and the Albany area was used as an example, since it embodies the three “E”s – education, economy, and ecosystem, i.e. workforce development, government support, and access to the tech cluster around CNSE.

Tom finished up with a plug for the new AMD Radeon 480 GPU, fabbed on the GF 14LPP process (we have one on order!), and a wrap-up of the above.

The theme of the morning session was “The Semiconductor Industry Outlook for 2016 and Beyond”. First up was Dan Armbrust, CEO of Silicon Catalyst, the industry’s first incubator company, which is trying to fill the void of start-up funding for new chip companies. I had not realised it, but the amount of venture capital (VC) money for start-up semiconductor companies has declined to near zero, even though VC funding is itself at almost record levels. Dan and his colleagues have set up a model whereby their partners provide in-kind support, reducing the need for actual seed capital, and Silicon Catalyst will also provide mentoring, physical space, business and legal services, and “lots of pizza”! Contributing partners

include TSMC, Synopsys, Advantest, Keysight, imec, PDF Solutions, Autodesk, Open Silicon, and the
MEMS foundry imt.

The next slide summarizes the model:

So far they have had three screening events, looked at 80+ applications, and selected ten companies for incubation. Seems like a good idea!

Lode Lauwers from imec was the next speaker; he did the usual obligatory description of imec’s capabilities and ecosystem, but once he got into the technical discussion, he put up a roadmap that extended to N+5, i.e. 2 nm, which is the first that I have seen.

In terms of possible technologies, I don’t think there’s anything new, but on our (now failing) two-year process cadence, that takes us out to 2026, so imec is looking a fair way ahead, and it seems the guys in R&D will have jobs for a while.

He also showed the following graphic of where broad applications fit on the roadmaps, so one perception is that IoT will only need technology down to 14 nm – I’m not sure the FDSOI lobby will agree with that, now that some of them are talking about stretching it to 7 nm.

He finished up with some examples of the collaborations that they are doing, using different flows and products such as memory and imagers.

My new colleague Kevin Gibb of TechInsights (TechInsights and Chipworks are now merging) next reviewed recent trends in chips, showing the scaling and some of the process changes we have seen in logic, DRAM and NAND flash technologies, and touching briefly on the die stacking in the Hynix HBM and a ReRAM example.

Kevin was followed by Hughes Metras, speaking for Europe’s other semiconductor collaborative research institute, CEA-Leti, with a slightly different roadmap, including FDSOI and their Coolcube monolithic 3D-stacking.

They are also looking at other forms of 3D integration, and Hughes showed examples of 2.5D/3D interposers showed Hughes showed examples of others that also include photonics devices amongst others. Of course we had examples of IoT – CEA-Leti has found applications in everything from medical to truck tires to pipelines.

Mark Reynolds from New York Empire State Development finished the morning session, describing the incentive programs that the state has in place to attract high-tech companies with high-income jobs there.

In essence this boils down to keeping the real estate off the books of the manufacturing company, by providing ready-to-go sites, infrastructure, and workforce, even going as far as building fabs with long term leases at incredibly competitive rates (e.g. $1!), and oftentimes including tooling and equipment. In addition there are tax credits, and the state has pumped oodles of cash into their schools, community colleges and universities to ensure a world class workforce.

We all know this has worked in luring AMD to build what is now the GLOBALFOUNDRIES fab in Malta; more recent examples are the new 300-mm ams fab in Utica (which has just started construction) Solar City in Buffalo (the largest PV plant in the US), the Soraa LED fab in Syracuse, and the GE SiC operation, with the fab in Albany and the packaging operation in Utica.

One could argue that it’s cheaper and easier just to write unemployment or welfare cheques for those in need, but the key to this strategy is the high-income jobs – surveys have shown (I’m told) that one job in a plant such as Malta has a five-to-one multiplier for other jobs, due to the infrastructure and social support (e.g. anything from schools to coffee shops) needed in the local area.

After lunch the main event of the afternoon was a panel on IoT, with Kelvin Low from Samsung Foundry, Rajeev Rajan from GF (VP IoT Product), Uday Tennety of GE Digital, and Jim Hewitt from Siemens as the moderator. There were lots of questions about applications and security, but occasionally we got onto the technology needed for IoT, and how compact the devices could be.

I was curious if the different elements could be integrated into one chip, since the basics of an IoT part are sensor(s), a microcontroller to process the data, a wireless interface, maybe some memory, and power management. These at the least require a range of process technology, since RF processes are usually different from logic and power, never mind the possibly of a MEMS sensor of some sort.

So I put the question, and was mildly surprised that both the foundry guys agreed that it is becoming possible, since FDSOI, with its back bias capability, allows a wider range of voltages and frequencies, and they clearly see this as an opportunity for them to get seriously into the IoT chip market.

The panel lasted an hour and a half or so, then we had a break before another reception.

By Dick James, Senior Technology Analyst, Chipworks

It’s spring in the north-eastern part of North America, and that means it’s the time of year for the Advanced Semiconductor Manufacturing Conference, in the amiable ambiance of Saratoga Springs, New York. The conference took place a couple of weeks ago, on May 16 – 19.

As the name says, ASMC is an annual conference focused on the manufacturing of semiconductor devices; in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers – some are better described as “tales from the fab”! After all, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.

I always come away impressed by the quality of the engineering involved; not being a fab person myself any more, it’s easy to get disconnected from the density of effort required to equip a fab, keep it running and bring new products/processes into production. Usually the guys in the fab only get publicity if something goes wrong!

There were 96 papers spread over the three days, 60 presentations and 36 posters, and the highest attendance ever at 350+ (registration was actually closed on day 1 – we ran out of room!). In addition we had keynotes from Don O’Toole of IBM and Christine Furstoss of GE Global Research, a tutorial on Nanoscale III-V CMOS by Jesús del Alamo from MIT, and to finish the Wednesday afternoon there was a panel discussion on “Moore’s Law Wall vs. Moore’s Wallet, and Where Do We Grow From Here?”. Bob Maire of Semiconductor Advisors wrapped up the conference Thursday lunchtime with a talk on China’s effect on the semiconductor biz; “Mergers & Acquisitions in the Semiconductor Industry – Could China Cause Continued Consolidation?”

Full House at Don O’Toole’s ASMC Keynote

I guess it’s a reflection of the location, but 46 out of the 96 papers were from Silicon on the Hudson – GLOBALFOUNDRIES, IBM, and CNSE/G450 affiliates. Having said that, there were papers from the likes of Samsung, TSMC, and UMC, not to mention NXP, Infineon, ON Semi, and others, plus some academic and student papers. It’s always tough to get papers from far afield these days, especially with tightening travel budgets and visa requirements, not to mention the gut desire to keep internal information in-house.

And of course Chipworks usually has an offering, though we missed out last year due to personal circumstances, otherwise it would be twelve years in a row. It’s a bit of an odd fit, since we are a service company that doesn’t make anything; but we do take the leading edge chips apart, and it seems the fab guys at the conference like seeing the competition’s stuff – and their own – since, if you’re deep into running the fab, you don’t get much of a chance to look at the final product.

And, now that we’ve been presenting since 2005, our papers are actually a condensed history of the technology from the 90-nm era down to 14-nm finFETs – if you read the references at the end of the blog you’ll see we’ve covered a fair spread of technology, not just logic transistors, but also flash and DRAM memory.

The initial reason for my submitting a paper back in 2004 for the 2005 conference was that ASMC that year was co-located with Semicon Europa – and I liked the idea of a trip to Munich! We were also a growing company, and starting to flex some of our marketing muscles by presenting at, rather than just attending conferences. In that context, the 2005 conference was a success, since Tom Cheyney, editor of the now-defunct Micro magazine, invited me to write regular articles for the publication, and that led to a series of articles and blogs that is still going.

Looking back at the older presentations, they really are a trip down memory lane – remember that first Intel 90-nm transistor with embedded silicon-germanium source/drains for the PMOS? We looked at that in 2005 [1].

The compressive stress given by the SiGe turned out to be a very effective tool for cranking up the strain in the channel, to the extent that PMOS and NMOS drive currents are now comparable, definitely a different design paradigm from the days of my youth.

And it turned out that the technology was transferable to high-k, metal-gate (HKMG) finFETs – witness the latest 14-nm Intel PMOS device:

Taking a different tack, IBM was already using SOI, but before they used embedded stress techniques, the SOI layer was only 45 nm thick – not quite FDSOI, but thinner than their current (GLOBALFOUNDRIES) HKMG offering that uses 80-nm thick SOI.

As you can see below, things are considerably more complex these days!

When it comes to memory, 90-nm DRAM was the order of the day, and the recessed channel array transistor (RCAT) had just been introduced:

Now we have 10-nm class (likely 18-nm) 8-Gb DRAMs, though the latest I reviewed at ASMC [9] was a 26-nm 4-Gb part in 2013 – that was three generations ago!

In the meantime we have seen the introduction of buried tungsten saddle-fin transistors for the wordlines (buried wordlines – BWL), ZAZ (zirconia/alumina/zirconia) high-k capacitor dielectrics, and air-gaps; shrinking cell area by more than a factor of ten. The node definition has also moved from half the M1 pitch to half of the active silicon pitch, nothing stays the same in our business.

I didn’t talk about flash that first year, but a couple of years later [3] the leading edge was a 62-nm, 8-Gb part, and 50-nm was starting to come into production. The conference that year was in Stresa, on Lake Maggiore in Italy, one of the more exotic locations that we’ve been to.

The latest in planar flash in 2013 [9] was a 19-nm Toshiba 128-Gb device:

We still have the conventional floating gate/control gate structure, but cell size has shrunk by an order of magnitude, we have air gaps between cells, and in order to keep effective coupling between control gate and floating gate, the aspect ratio of the floating gate has increased from ~1.3 to ~4.8.

In 2016, of course, we have planar flash down to the 15-nm generation, including the use of high-k dielectric, and we are into the third-generation vertical flash parts.

So much for then and now – this year’s conference had 15 different sessions:

• Contamination Free Manufacturing (CFM)
• Advanced Metrology I & II
• Defect Inspection I & II
• Factory Optimization I & II
• Advanced Equipment and Materials Processes
• Yield Enhancement & Yield Learning
• Advanced Equipment/CFM
• Advanced Patterning/CFM
• Advanced Process Control (APC)
• Yield Enhancement
• 3D TSV

Including a poster session for shorter papers that covered all the above topics.
The subjects of individual papers ranged from improvements to chemical-mechanical planarization, through threshold voltage variations in HKMG gates due to non-uniform alloying, to ‘smart manufacturing’ in legacy 200mm fabs, and multiple papers on virtual metrology – i.e. a broad swath of the practical wafer manufacturing problems to fab loading algorithms and everything in between. The detailed schedule can be found here, and no doubt the proceedings will be available through IEEE Xplore in due course.

Next year’s ASMC will again be in Saratoga Springs, on May 15 – 18; we hope to see you there!

References

• James, 2004 – The Year of 90-nm: A Review of 90 nm Devices, Proc. ASMC 2005
• James, Low-K and Interconnect Stacks – a Status Report, Proc. ASMC 2006
• James, Nano-Scale Flash in the Mid-Decade, Proc. ASMC 2007
• James, From Strain to High K/Metal Gate – the 65/45 nm Transition, Proc. ASMC 2008
• James, Design-for-Manufacturing Features in Nanometer Processes – A Reverse Engineering Perspective, Proc. ASMC 2009
• James, Recent Innovations in DRAM Manufacturing, Proc. ASMC 2010
• Fontaine, Recent Innovations in CMOS Image Sensors, Proc. ASMC 2011
• James, High-k/Metal Gates in Leading Edge Silicon Devices, Proc. ASMC 2012
• James, Recent Advances in Memory Technology, Proc. ASMC 2013
• James, 3D ICs in the Real World, Proc. ASMC 2014
• James, High-k/Metal Gates in the 2010s, Proc. ASMC 2014
• James, Moore’s Law Continues into the 1x-nm Era, Proc. ASMC 2016

By Dick James, Senior Technology Analyst, Chipworks

It’s the time in the media world that we see a frenzy of predictions for the coming year. They are mostly business or tech trends, so I figured I might as well chip in (har! har!), and give a more detailed idea of what new semiconductor products we look forward to this year, now that we are in 2016.

This might seem to be a bit like fortune-telling, but it’s actually a compilation of the notes we’ve made from this year’s press announcements, coupled with the trends we’ve observed in our reverse engineering, and keeping an open ear at the industry events that we’ve attended.

Logic & Foundries

2016 will be a relatively quiet year when it comes to the leading-edge processes, since we do not expect to see a high-volume of 10 nm products this year. There has been a fair bit of comment that the upcoming Apple A10 processor might be on 10 nm this autumn, but to me it seems a real stretch to expect a full node advance barely 18 months after the introduction of a 14 nm product from Samsung, and a 16 nm product from TSMC, especially in the volume that Apple would require.

We do expect to see the second generation 14/16 nm processes, FinFET Plus (16FF+) from TSMC and 14LPP from Samsung and possibly their co-supplier GLOBALFOUNDRIES. The second-tier foundries such as UMC and SMIC will be ramping up their 28 nm high-k metal gate (HKMG) product, so we will be monitoring those as we get them. It appears that UMC will be skipping 20 nm and going straight to 14 nm, but that will not likely appear until 2017.

When it comes to fully depleted silicon on insulator (FD-SOI), we expect to see a mainstream 28 nm product this year, since Samsung has stated that they are producing, and have shipped more than a million wafers, with STMicroelectronics as one of their lead customers. Chipworks has already analyzed a custom 28 nm FD-SOI ASIC manufactured at STMicroelectronics, which was a simple implementation without back-bias. For the mainstream parts, we will be analyzing back-bias implementation, if found, as it is touted as one of the big advantages of FD-SOI.

GLOBALFOUNDRIES is also on the FD-SOI bandwagon, but they seem to be concentrating on their 22FDX™ processes. A number of the ASIC design houses are claiming to be designing into those, so with luck we will see some very early product by year-end.

There will also be a continued emphasis on low power variants of older generation processes, such as 40 and 55 nm, aimed at mobile/wearable devices where battery life is critical.

To finish up, another process sector where we expect to see development is radio frequency silicon on insulator (RF-SOI). We are already seeing the introduction of RF-SOI into products such as antenna switches for the RF front end of mobile phones.

DRAM

This will be another year of evolution for dynamic random-access memory (DRAM), with the introduction of 1X nm generation memories by the big three (Micron, Samsung, and SK Hynix), although possibly not until year-end.

Micron has 1X and 1Y nm nodes in its roadmap (above), enabling 1X volume mid-2016.

Samsung predicts three 1X nm nodes (see above), though there is no time scale here; however, we already have their 20 nm part, which is in volume production, so it’s reasonable to expect a 1X nm part this year. We haven’t heard anything formal from SK Hynix, but again, we already have their 20 nm part, so we would expect a 1X nm device in 2016.

The other facet of the DRAM business is stacked memory using through-silicon vias (TSVs); in 2015 we saw the Samsung version, and the SK Hynix High Bandwidth Memory (HBM). We’re still waiting for the Intel/Micron Hybrid Memory Cube (HMC), and we expect to get our hands on that this year, as well as the HBM2 from SK Hynix AND Flash.

The big news in NAND flash memory is the introduction of 3D/vertical technology, with the bitcells stacked one above another instead of on the die surface. Samsung launched their V-NAND over a year ago, with 32 active layers in both multi-level cell (MLC) and tri-level cell (TLC) versions, using charge-trap storage technology. They are now shipping the third generation part (256 Gb) with 48 layers, so we should see that in the near future.

Last month, at IEDM (International Electron Devices Meeting), Intel/Micron detailed their 3D-NAND, a 32-layer device, this time using conventional floating gate charge storage. According to their investor calls, they are sampling these at the moment and should be shipping volume in the second half of this year.

SEM cross-section of Intel/Micron vertical-channel 3D-NAND structure

SanDisk/Toshiba are also sampling, but their 3D-NAND is a 48-layer, 256-Gb TLC device, built using their own Bit-Cost Scalable (BiCS) charge-trap technology. They have been more cautious about the economics of launching 3D technology, but again I look forward to getting some in 2016. Last, but not necessarily least, SK Hynix claim that they are already in 3D production, and we should also see their floating-gate version this year.

In parallel, all the companies are still evolving planar flash products – we will likely find 13 – 15 nm planar flash chips being launched, since the 15/16-nm ones are already here.
Emerging Memory
The highest-profile announcement this year for this memory class was from Intel/Micron, on their 3D XPoint memory; this appears to be some sort of resistive random-access memory (RRAM), using “bulk properties” to provide memory storage in a cross-point layout. Both Intel and Micron predict a big future for this product; Micron claims that the 3D XPoint business could easily be of the same order of magnitude as their DRAM businesses by 2018, and Intel sees broad applications for 3D XPoint memory (dubbed Optane), and says that it will be available this year for PC and server usage.

Less noticed was a similar release from SanDisk and HP, also detailing storage-class RRAM-based memory, but with no details as to launch dates. Micron and Sony also have a jointly developed RRAM, but again no dates.

Image Sensors

There has been a steady evolution in the image sensor biz, with Sony leading the pack, and culminating in the deep-trench isolation between pixels in the Apple 6s/6s Plus camera. Sony has had a two year+ lead in stacking the sensor on top of the image processor and connecting the two with custom TSVs, but we now see OmniVision and Samsung with design wins using multiple versions of its new stacked chip products.

We can, no doubt, expect to see a further-evolved camera chip in the iPhone 7, and Apple’s competitors will also be pushing the envelope, so we will be monitoring every new smartphone to see what appears.

Meanwhile, other sectors are developing fast – to name two, the push on automated driver self-assist (ADAS) and self-driving vehicles is providing a new space for lower-tech (but different specifications) image sensors, and security is likely to be a hot market given last year’s terror attacks.
Advanced Packaging

Packaging technology has been in as much ferment as any of the wafer fab technologies, with 2.5/3D stacking getting most of the press. We expect 2016 to be a busy year in that space too; TSMC is producing its Chip-on-Wafer-on-Substrate (CoWoS) silicon interposer for a limited range of products, and seems about to launch its cheaper integrated fan-out (InFO) organic substrate, possibly using it for the Apple A10 system-on-chip (SoC) this fall.

TSMC has TSVs in volume production, though not high-density for 2.5/3D; the new fingerprint sensor in the Apple 6s/6s Plus uses TSVs so that the wire bonds don’t get in the way of the sapphire touchpad.

Intel has a parallel “Embedded Multi-die Interconnect Bridge” (EMIB) technology (to TSMC’s InFO), and given the completed Altera deal, we may finally see a 14 nm field-programmable gate array (FPGA) product with EMIB this year.

Add in the Intel/Micron HMC, SK Hynix’s HBM2 and Wide IO2 stack, and the OSATs are also pushing the envelope and likely to ship new formats this year, so there will be plenty for us to look at.
Wrap-up

This has been a relatively high-level review of what we expect this year, but as you can see from the above, it will be quite a hectic year – lots of new technology for us to analyze!